commit bc67cef3e3dc9e7fe9c4331495009eda48c89527
author Narumol Prangnawarat <narumol.prangnawarat@arm.com> Thu Jan 31 15:31:54 2019 +0000
committer Narumol Prangnawarat <narumol.prangnawarat@arm.com> Mon Feb 04 10:57:48 2019 +0000
tree 6a15af84fbc5989d25213790554acbb46cda5165
parent c981df3bb24df1f98c233d885e73a2ea5c6d3449

IVGCVSW-2557 Ref Workload Implementation for Detection PostProcess

 * implementation of DetectionPostProcessQueueDescriptor validate
 * add Uint8ToFloat32Workload
 * add implementation of Detection PostProcess functionalities
 * add ref workload implemenentation for float and uint8
 * add layer support for Detection PostProcess in ref
 * unit tests

Change-Id: I650461f49edbb3c533d68ef8700377af51bc3592

src/backends/reference/RefLayerSupport.hpp

diff --git a/src/backends/reference/RefLayerSupport.hpp b/src/backends/reference/RefLayerSupport.hpp
index 5fe111b..3b73f22 100644
--- a/src/backends/reference/RefLayerSupport.hpp
+++ b/src/backends/reference/RefLayerSupport.hpp
@@ -66,6 +66,11 @@
                                          const Optional<TensorInfo>& biases,
                                          Optional<std::string&> reasonIfUnsupported = EmptyOptional()) const override;
 
+    bool IsDetectionPostProcessSupported(const TensorInfo& input0,
+                                         const TensorInfo& input1,
+                                         const DetectionPostProcessDescriptor& descriptor,
+                                         Optional<std::string&> reasonIfUnsupported = EmptyOptional()) const override;
+
     bool IsDivisionSupported(const TensorInfo& input0,
                              const TensorInfo& input1,
                              const TensorInfo& output,