IVGCVSW-2972 Support QSymm16 for Merger
Change-Id: If2289b2d1fc20f4524fcf4620f01ea3a36d727d2
Signed-off-by: Jim Flynn <jim.flynn@arm.com>
diff --git a/src/backends/reference/workloads/CMakeLists.txt b/src/backends/reference/workloads/CMakeLists.txt
index b1cdef9..8c8aa6f 100644
--- a/src/backends/reference/workloads/CMakeLists.txt
+++ b/src/backends/reference/workloads/CMakeLists.txt
@@ -83,10 +83,8 @@
RefL2NormalizationFloat32Workload.hpp
RefLstmWorkload.cpp
RefLstmWorkload.hpp
- RefMergerFloat32Workload.cpp
- RefMergerFloat32Workload.hpp
- RefMergerUint8Workload.cpp
- RefMergerUint8Workload.hpp
+ RefMergerWorkload.cpp
+ RefMergerWorkload.hpp
RefNormalizationFloat32Workload.cpp
RefNormalizationFloat32Workload.hpp
RefPadWorkload.cpp
diff --git a/src/backends/reference/workloads/Merger.cpp b/src/backends/reference/workloads/Merger.cpp
index 8877ee2..e0b70ee 100644
--- a/src/backends/reference/workloads/Merger.cpp
+++ b/src/backends/reference/workloads/Merger.cpp
@@ -5,43 +5,19 @@
#include "Merger.hpp"
#include "RefWorkloadUtils.hpp"
+#include "Decoders.hpp"
+#include "Encoders.hpp"
namespace armnn
{
-template <>
-void CopyValue<float>(const float& source, const TensorInfo& sourceInfo, float& dest, const TensorInfo& destInfo)
-{
- dest = source;
-}
-
-template <>
-void CopyValue<uint8_t>(const uint8_t& source, const TensorInfo& sourceInfo, uint8_t& dest, const TensorInfo& destInfo)
-{
- if (sourceInfo.GetQuantizationScale() != destInfo.GetQuantizationScale() ||
- sourceInfo.GetQuantizationOffset() != destInfo.GetQuantizationOffset())
- {
- // Dequantize value according to sourceInfo params
- float dequantizedValue = armnn::Dequantize<uint8_t>(source,
- sourceInfo.GetQuantizationScale(),
- sourceInfo.GetQuantizationOffset());
-
- // Quantize again according to destInfo paramns
- dest = armnn::Quantize<uint8_t>(dequantizedValue,
- destInfo.GetQuantizationScale(),
- destInfo.GetQuantizationOffset());
- }
- else
- {
- dest = source;
- }
-}
-
-template <typename DataType>
void Merger(const MergerQueueDescriptor& data)
{
const TensorInfo& outputInfo0 = GetTensorInfo(data.m_Outputs[0]);
+ std::unique_ptr<Encoder<float>> encoderPtr = MakeEncoder<float>(outputInfo0, data.m_Outputs[0]->Map());
+ Encoder<float>& encoder = *encoderPtr;
+
for (unsigned int index = 0 ; index < outputInfo0.GetNumElements(); ++index)
{
unsigned int indices[MaxNumOfTensorDimensions] = { 0 };
@@ -80,6 +56,9 @@
if (insideView)
{
+ std::unique_ptr<Decoder<float>> decoderPtr =
+ MakeDecoder<float>(inputInfo, data.m_Inputs[viewIdx]->Map());
+ Decoder<float>& decoder = *decoderPtr;
unsigned int inIndex = 0;
unsigned int dimensionStride = 1;
@@ -88,11 +67,8 @@
inIndex += dimensionStride * (indices[i] - view.m_Origin[i]);
dimensionStride *= inputInfo.GetShape()[i];
}
-
- CopyValue<DataType>((GetInputTensorData<DataType>(viewIdx, data))[inIndex],
- GetTensorInfo(data.m_Inputs[viewIdx]),
- (GetOutputTensorData<DataType>(0, data))[index],
- outputInfo0);
+ decoder += inIndex;
+ encoder.Set(decoder.Get());
//What should we do if input views overlap on the output tensor?
//We could error, take the average, or shm else...
@@ -100,11 +76,8 @@
break;
}
}
+ ++encoder;
}
}
-template void Merger<float>(const MergerQueueDescriptor& data);
-
-template void Merger<uint8_t>(const MergerQueueDescriptor& data);
-
} //namespace armnn
diff --git a/src/backends/reference/workloads/Merger.hpp b/src/backends/reference/workloads/Merger.hpp
index ba3b99b..eaa154d 100644
--- a/src/backends/reference/workloads/Merger.hpp
+++ b/src/backends/reference/workloads/Merger.hpp
@@ -10,11 +10,5 @@
namespace armnn
{
-
-template <typename DataType>
-void CopyValue(const DataType& source, const TensorInfo& sourceInfo, DataType& dest, const TensorInfo& destInfo);
-
-template <typename DataType>
void Merger(const MergerQueueDescriptor& data);
-
} //namespace armnn
diff --git a/src/backends/reference/workloads/RefMergerFloat32Workload.cpp b/src/backends/reference/workloads/RefMergerFloat32Workload.cpp
deleted file mode 100644
index b1f8a32..0000000
--- a/src/backends/reference/workloads/RefMergerFloat32Workload.cpp
+++ /dev/null
@@ -1,21 +0,0 @@
-//
-// Copyright © 2017 Arm Ltd. All rights reserved.
-// SPDX-License-Identifier: MIT
-//
-
-#include "RefMergerFloat32Workload.hpp"
-
-#include "Merger.hpp"
-
-#include "Profiling.hpp"
-
-namespace armnn
-{
-
-void RefMergerFloat32Workload::Execute() const
-{
- ARMNN_SCOPED_PROFILING_EVENT(Compute::CpuRef, "RefMergerFloat32Workload_Execute");
- Merger<float>(m_Data);
-}
-
-} //namespace armnn
diff --git a/src/backends/reference/workloads/RefMergerFloat32Workload.hpp b/src/backends/reference/workloads/RefMergerFloat32Workload.hpp
deleted file mode 100644
index 8d7b270..0000000
--- a/src/backends/reference/workloads/RefMergerFloat32Workload.hpp
+++ /dev/null
@@ -1,21 +0,0 @@
-//
-// Copyright © 2017 Arm Ltd. All rights reserved.
-// SPDX-License-Identifier: MIT
-//
-
-#pragma once
-
-#include <backendsCommon/Workload.hpp>
-#include <backendsCommon/WorkloadData.hpp>
-
-namespace armnn
-{
-
-class RefMergerFloat32Workload : public Float32Workload<MergerQueueDescriptor>
-{
-public:
- using Float32Workload<MergerQueueDescriptor>::Float32Workload;
- virtual void Execute() const override;
-};
-
-} //namespace armnn
diff --git a/src/backends/reference/workloads/RefMergerUint8Workload.cpp b/src/backends/reference/workloads/RefMergerUint8Workload.cpp
deleted file mode 100644
index 47ce1cf..0000000
--- a/src/backends/reference/workloads/RefMergerUint8Workload.cpp
+++ /dev/null
@@ -1,21 +0,0 @@
-//
-// Copyright © 2017 Arm Ltd. All rights reserved.
-// SPDX-License-Identifier: MIT
-//
-
-#include "RefMergerUint8Workload.hpp"
-
-#include "Merger.hpp"
-
-#include "Profiling.hpp"
-
-namespace armnn
-{
-
-void RefMergerUint8Workload::Execute() const
-{
- ARMNN_SCOPED_PROFILING_EVENT(Compute::CpuRef, "RefMergerUint8Workload_Execute");
- Merger<uint8_t>(m_Data);
-}
-
-} //namespace armnn
diff --git a/src/backends/reference/workloads/RefMergerWorkload.cpp b/src/backends/reference/workloads/RefMergerWorkload.cpp
new file mode 100644
index 0000000..5b42e82
--- /dev/null
+++ b/src/backends/reference/workloads/RefMergerWorkload.cpp
@@ -0,0 +1,21 @@
+//
+// Copyright © 2017 Arm Ltd. All rights reserved.
+// SPDX-License-Identifier: MIT
+//
+
+#include "RefMergerWorkload.hpp"
+
+#include "Merger.hpp"
+
+#include "Profiling.hpp"
+
+namespace armnn
+{
+
+void RefMergerWorkload::Execute() const
+{
+ ARMNN_SCOPED_PROFILING_EVENT(Compute::CpuRef, "RefMergerWorkload_Execute");
+ Merger(m_Data);
+}
+
+} //namespace armnn
diff --git a/src/backends/reference/workloads/RefMergerUint8Workload.hpp b/src/backends/reference/workloads/RefMergerWorkload.hpp
similarity index 67%
rename from src/backends/reference/workloads/RefMergerUint8Workload.hpp
rename to src/backends/reference/workloads/RefMergerWorkload.hpp
index df23af0..138838a 100644
--- a/src/backends/reference/workloads/RefMergerUint8Workload.hpp
+++ b/src/backends/reference/workloads/RefMergerWorkload.hpp
@@ -11,10 +11,10 @@
namespace armnn
{
-class RefMergerUint8Workload : public Uint8Workload<MergerQueueDescriptor>
+class RefMergerWorkload : public BaseWorkload<MergerQueueDescriptor>
{
public:
- using Uint8Workload<MergerQueueDescriptor>::Uint8Workload;
+ using BaseWorkload<MergerQueueDescriptor>::BaseWorkload;
virtual void Execute() const override;
};
diff --git a/src/backends/reference/workloads/RefWorkloads.hpp b/src/backends/reference/workloads/RefWorkloads.hpp
index 8ffd348..9a2eb0a 100644
--- a/src/backends/reference/workloads/RefWorkloads.hpp
+++ b/src/backends/reference/workloads/RefWorkloads.hpp
@@ -16,11 +16,10 @@
#include "RefActivationWorkload.hpp"
#include "RefPooling2dFloat32Workload.hpp"
#include "RefWorkloadUtils.hpp"
-#include "RefMergerUint8Workload.hpp"
+#include "RefMergerWorkload.hpp"
#include "RefFullyConnectedFloat32Workload.hpp"
#include "RefGatherWorkload.hpp"
#include "Softmax.hpp"
-#include "RefMergerFloat32Workload.hpp"
#include "TensorBufferArrayView.hpp"
#include "RefBatchNormalizationFloat32Workload.hpp"
#include "Splitter.hpp"