commit cd066ca52d661adf042f0a3122e809ca8769309c
author Nattapat Chaimanowong <nattapat.chaimanowong@arm.com> Wed Oct 10 12:11:50 2018 +0100
committer Matthew Bentham <matthew.bentham@arm.com> Mon Oct 22 16:57:53 2018 +0100
tree 9dae1983ad299bea37a9097afddef4a6304a8b21
parent 6b0b53d307f956c3d67429f2a93df91f2eb2f483

IVGCVSW-1951-Remove type templating from ClAdditionWorkload

Change-Id: Ic16c4505bac9c9025856aa4eac1127ad957c9d75

src/backends/cl/workloads/ClAdditionWorkload.cpp

diff --git a/src/backends/cl/workloads/ClAdditionWorkload.cpp b/src/backends/cl/workloads/ClAdditionWorkload.cpp
index ec0dd30..c9ac958 100644
--- a/src/backends/cl/workloads/ClAdditionWorkload.cpp
+++ b/src/backends/cl/workloads/ClAdditionWorkload.cpp
@@ -17,10 +17,9 @@
 
 static constexpr arm_compute::ConvertPolicy g_AclConvertPolicy = arm_compute::ConvertPolicy::SATURATE;
 
-template <armnn::DataType... T>
-ClAdditionWorkload<T...>::ClAdditionWorkload(const AdditionQueueDescriptor& descriptor,
-                                                  const WorkloadInfo& info)
-    : TypedWorkload<AdditionQueueDescriptor, T...>(descriptor, info)
+ClAdditionWorkload::ClAdditionWorkload(const AdditionQueueDescriptor& descriptor,
+                                       const WorkloadInfo& info)
+    : BaseWorkload<AdditionQueueDescriptor>(descriptor, info)
 {
     this->m_Data.ValidateInputsOutputs("ClAdditionWorkload", 2, 1);
 
@@ -30,8 +29,7 @@
     m_Layer.configure(&input0, &input1, &output, g_AclConvertPolicy);
 }
 
-template <armnn::DataType... T>
-void ClAdditionWorkload<T...>::Execute() const
+void ClAdditionWorkload::Execute() const
 {
     ARMNN_SCOPED_PROFILING_EVENT_CL("ClAdditionWorkload_Execute");
     m_Layer.run();
@@ -54,6 +52,3 @@
 }
 
 } //namespace armnn
-
-template class armnn::ClAdditionWorkload<armnn::DataType::Float16, armnn::DataType::Float32>;
-template class armnn::ClAdditionWorkload<armnn::DataType::QuantisedAsymm8>;