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+<a href="_ref_arg_min_max_workload_8cpp.html">Go to the documentation of this file.</a><div class="fragment"><div class="line"><a name="l00001"></a><span class="lineno">    1</span>&#160;<span class="comment">//</span></div><div class="line"><a name="l00002"></a><span class="lineno">    2</span>&#160;<span class="comment">// Copyright © 2019 Arm Ltd. All rights reserved.</span></div><div class="line"><a name="l00003"></a><span class="lineno">    3</span>&#160;<span class="comment">// SPDX-License-Identifier: MIT</span></div><div class="line"><a name="l00004"></a><span class="lineno">    4</span>&#160;<span class="comment">//</span></div><div class="line"><a name="l00005"></a><span class="lineno">    5</span>&#160;</div><div class="line"><a name="l00006"></a><span class="lineno">    6</span>&#160;<span class="preprocessor">#include &quot;<a class="code" href="_ref_arg_min_max_workload_8hpp.html">RefArgMinMaxWorkload.hpp</a>&quot;</span></div><div class="line"><a name="l00007"></a><span class="lineno">    7</span>&#160;</div><div class="line"><a name="l00008"></a><span class="lineno">    8</span>&#160;<span class="preprocessor">#include &quot;<a class="code" href="_arg_min_max_8hpp.html">ArgMinMax.hpp</a>&quot;</span></div><div class="line"><a name="l00009"></a><span class="lineno">    9</span>&#160;<span class="preprocessor">#include &quot;<a class="code" href="_ref_workload_utils_8hpp.html">RefWorkloadUtils.hpp</a>&quot;</span></div><div class="line"><a name="l00010"></a><span class="lineno">   10</span>&#160;<span class="preprocessor">#include &quot;<a class="code" href="_decoders_8hpp.html">Decoders.hpp</a>&quot;</span></div><div class="line"><a name="l00011"></a><span class="lineno">   11</span>&#160;<span class="preprocessor">#include &quot;<a class="code" href="_encoders_8hpp.html">Encoders.hpp</a>&quot;</span></div><div class="line"><a name="l00012"></a><span class="lineno">   12</span>&#160;<span class="preprocessor">#include &quot;<a class="code" href="_profiling_8hpp.html">Profiling.hpp</a>&quot;</span></div><div class="line"><a name="l00013"></a><span class="lineno">   13</span>&#160;</div><div class="line"><a name="l00014"></a><span class="lineno">   14</span>&#160;<span class="keyword">namespace </span><a class="code" href="namespacearmnn.html">armnn</a></div><div class="line"><a name="l00015"></a><span class="lineno">   15</span>&#160;{</div><div class="line"><a name="l00016"></a><span class="lineno"><a class="line" href="classarmnn_1_1_ref_arg_min_max_workload.html#a1a99463578f57c24906126f682521200">   16</a></span>&#160;<a class="code" href="classarmnn_1_1_ref_arg_min_max_workload.html#a1a99463578f57c24906126f682521200">RefArgMinMaxWorkload::RefArgMinMaxWorkload</a>(</div><div class="line"><a name="l00017"></a><span class="lineno">   17</span>&#160;        <span class="keyword">const</span> <a class="code" href="structarmnn_1_1_arg_min_max_queue_descriptor.html">ArgMinMaxQueueDescriptor</a>&amp; descriptor,</div><div class="line"><a name="l00018"></a><span class="lineno">   18</span>&#160;        <span class="keyword">const</span> <a class="code" href="structarmnn_1_1_workload_info.html">WorkloadInfo</a>&amp; info)</div><div class="line"><a name="l00019"></a><span class="lineno">   19</span>&#160;        : <a class="code" href="classarmnn_1_1_base_workload.html">BaseWorkload</a>&lt;<a class="code" href="structarmnn_1_1_arg_min_max_queue_descriptor.html">ArgMinMaxQueueDescriptor</a>&gt;(descriptor, info) {}</div><div class="line"><a name="l00020"></a><span class="lineno">   20</span>&#160;</div><div class="line"><a name="l00021"></a><span class="lineno"><a class="line" href="classarmnn_1_1_ref_arg_min_max_workload.html#ae071e8822437c78baea75c3aef3a263a">   21</a></span>&#160;<span class="keywordtype">void</span> <a class="code" href="classarmnn_1_1_ref_arg_min_max_workload.html#ae071e8822437c78baea75c3aef3a263a">RefArgMinMaxWorkload::Execute</a>()<span class="keyword"> const</span></div><div class="line"><a name="l00022"></a><span class="lineno">   22</span>&#160;<span class="keyword"></span>{</div><div class="line"><a name="l00023"></a><span class="lineno">   23</span>&#160;    <a class="code" href="_profiling_8hpp.html#a5ccc65e2c464ac05ce311fdae7ede03a">ARMNN_SCOPED_PROFILING_EVENT</a>(<a class="code" href="namespacearmnn.html#ae2f04a162585c0a5222a537efd5456aea83c2c4e9b658ccafbcbe6309c5d84c64">Compute::CpuRef</a>, <span class="stringliteral">&quot;RefArgMinMaxWorkload_Execute&quot;</span>);</div><div class="line"><a name="l00024"></a><span class="lineno">   24</span>&#160;</div><div class="line"><a name="l00025"></a><span class="lineno">   25</span>&#160;    <span class="keyword">const</span> <a class="code" href="classarmnn_1_1_tensor_info.html">TensorInfo</a> &amp;inputTensorInfo = <a class="code" href="namespacearmnn.html#a93d269806f34407695dc10f510001c30">GetTensorInfo</a>(<a class="code" href="classarmnn_1_1_base_workload.html#a0a487c549c63319505095b855ea3c195">m_Data</a>.<a class="code" href="structarmnn_1_1_queue_descriptor.html#a4b50e46a6810018f3edecfb68b2a76b3">m_Inputs</a>[0]);</div><div class="line"><a name="l00026"></a><span class="lineno">   26</span>&#160;</div><div class="line"><a name="l00027"></a><span class="lineno">   27</span>&#160;    std::unique_ptr&lt;Decoder&lt;float&gt;&gt; decoderPtr = MakeDecoder&lt;float&gt;(inputTensorInfo, <a class="code" href="classarmnn_1_1_base_workload.html#a0a487c549c63319505095b855ea3c195">m_Data</a>.<a class="code" href="structarmnn_1_1_queue_descriptor.html#a4b50e46a6810018f3edecfb68b2a76b3">m_Inputs</a>[0]-&gt;Map());</div><div class="line"><a name="l00028"></a><span class="lineno">   28</span>&#160;    <a class="code" href="classarmnn_1_1_decoder.html">Decoder&lt;float&gt;</a> &amp;decoder = *decoderPtr;</div><div class="line"><a name="l00029"></a><span class="lineno">   29</span>&#160;</div><div class="line"><a name="l00030"></a><span class="lineno">   30</span>&#160;    <span class="keyword">const</span> <a class="code" href="classarmnn_1_1_tensor_info.html">TensorInfo</a> &amp;outputTensorInfo = <a class="code" href="namespacearmnn.html#a93d269806f34407695dc10f510001c30">GetTensorInfo</a>(<a class="code" href="classarmnn_1_1_base_workload.html#a0a487c549c63319505095b855ea3c195">m_Data</a>.<a class="code" href="structarmnn_1_1_queue_descriptor.html#a6abd491bb99ffe88bd472c1ae5a1ed1a">m_Outputs</a>[0]);</div><div class="line"><a name="l00031"></a><span class="lineno">   31</span>&#160;</div><div class="line"><a name="l00032"></a><span class="lineno">   32</span>&#160;    int32_t* output = GetOutputTensorData&lt;int32_t&gt;(0, <a class="code" href="classarmnn_1_1_base_workload.html#a0a487c549c63319505095b855ea3c195">m_Data</a>);</div><div class="line"><a name="l00033"></a><span class="lineno">   33</span>&#160;</div><div class="line"><a name="l00034"></a><span class="lineno">   34</span>&#160;    <a class="code" href="namespacearmnn.html#a56943a0946e5f15e5e58054b8e7a04a4a2139684546b147c106b329f41547640c">ArgMinMax</a>(decoder, output, inputTensorInfo, outputTensorInfo, <a class="code" href="classarmnn_1_1_base_workload.html#a0a487c549c63319505095b855ea3c195">m_Data</a>.<a class="code" href="structarmnn_1_1_queue_descriptor_with_parameters.html#aad91b9bbf7aa365d304febe79a3d1333">m_Parameters</a>.<a class="code" href="structarmnn_1_1_arg_min_max_descriptor.html#ab1ae6f520bb1a4da191a0ae907477f23">m_Function</a>,</div><div class="line"><a name="l00035"></a><span class="lineno">   35</span>&#160;              <a class="code" href="classarmnn_1_1_base_workload.html#a0a487c549c63319505095b855ea3c195">m_Data</a>.<a class="code" href="structarmnn_1_1_queue_descriptor_with_parameters.html#aad91b9bbf7aa365d304febe79a3d1333">m_Parameters</a>.<a class="code" href="structarmnn_1_1_arg_min_max_descriptor.html#a214c3636fdf0ea5bac8edb42d0e6c7f0">m_Axis</a>);</div><div class="line"><a name="l00036"></a><span class="lineno">   36</span>&#160;}</div><div class="line"><a name="l00037"></a><span class="lineno">   37</span>&#160;</div><div class="line"><a name="l00038"></a><span class="lineno">   38</span>&#160;} <span class="comment">//namespace armnn</span></div><div class="ttc" id="_profiling_8hpp_html_a5ccc65e2c464ac05ce311fdae7ede03a"><div class="ttname"><a href="_profiling_8hpp.html#a5ccc65e2c464ac05ce311fdae7ede03a">ARMNN_SCOPED_PROFILING_EVENT</a></div><div class="ttdeci">#define ARMNN_SCOPED_PROFILING_EVENT(backendId, name)</div><div class="ttdef"><b>Definition:</b> <a href="_profiling_8hpp_source.html#l00170">Profiling.hpp:170</a></div></div>
+<div class="ttc" id="structarmnn_1_1_queue_descriptor_with_parameters_html_aad91b9bbf7aa365d304febe79a3d1333"><div class="ttname"><a href="structarmnn_1_1_queue_descriptor_with_parameters.html#aad91b9bbf7aa365d304febe79a3d1333">armnn::QueueDescriptorWithParameters::m_Parameters</a></div><div class="ttdeci">LayerDescriptor m_Parameters</div><div class="ttdef"><b>Definition:</b> <a href="_workload_data_8hpp_source.html#l00049">WorkloadData.hpp:49</a></div></div>
+<div class="ttc" id="_ref_arg_min_max_workload_8hpp_html"><div class="ttname"><a href="_ref_arg_min_max_workload_8hpp.html">RefArgMinMaxWorkload.hpp</a></div></div>
+<div class="ttc" id="classarmnn_1_1_tensor_info_html"><div class="ttname"><a href="classarmnn_1_1_tensor_info.html">armnn::TensorInfo</a></div><div class="ttdef"><b>Definition:</b> <a href="_tensor_8hpp_source.html#l00053">Tensor.hpp:53</a></div></div>
+<div class="ttc" id="classarmnn_1_1_ref_arg_min_max_workload_html_ae071e8822437c78baea75c3aef3a263a"><div class="ttname"><a href="classarmnn_1_1_ref_arg_min_max_workload.html#ae071e8822437c78baea75c3aef3a263a">armnn::RefArgMinMaxWorkload::Execute</a></div><div class="ttdeci">virtual void Execute() const override</div><div class="ttdef"><b>Definition:</b> <a href="_ref_arg_min_max_workload_8cpp_source.html#l00021">RefArgMinMaxWorkload.cpp:21</a></div></div>
+<div class="ttc" id="structarmnn_1_1_workload_info_html"><div class="ttname"><a href="structarmnn_1_1_workload_info.html">armnn::WorkloadInfo</a></div><div class="ttdef"><b>Definition:</b> <a href="include_2armnn_2backends_2_workload_info_8hpp_source.html#l00016">WorkloadInfo.hpp:16</a></div></div>
+<div class="ttc" id="classarmnn_1_1_decoder_html"><div class="ttname"><a href="classarmnn_1_1_decoder.html">armnn::Decoder&lt; float &gt;</a></div></div>
+<div class="ttc" id="structarmnn_1_1_arg_min_max_descriptor_html_ab1ae6f520bb1a4da191a0ae907477f23"><div class="ttname"><a href="structarmnn_1_1_arg_min_max_descriptor.html#ab1ae6f520bb1a4da191a0ae907477f23">armnn::ArgMinMaxDescriptor::m_Function</a></div><div class="ttdeci">ArgMinMaxFunction m_Function</div><div class="ttdoc">Specify if the function is to find Min or Max. </div><div class="ttdef"><b>Definition:</b> <a href="_descriptors_8hpp_source.html#l00056">Descriptors.hpp:56</a></div></div>
+<div class="ttc" id="structarmnn_1_1_arg_min_max_descriptor_html_a214c3636fdf0ea5bac8edb42d0e6c7f0"><div class="ttname"><a href="structarmnn_1_1_arg_min_max_descriptor.html#a214c3636fdf0ea5bac8edb42d0e6c7f0">armnn::ArgMinMaxDescriptor::m_Axis</a></div><div class="ttdeci">int m_Axis</div><div class="ttdoc">Axis to reduce across the input tensor. </div><div class="ttdef"><b>Definition:</b> <a href="_descriptors_8hpp_source.html#l00058">Descriptors.hpp:58</a></div></div>
+<div class="ttc" id="classarmnn_1_1_base_workload_html_a0a487c549c63319505095b855ea3c195"><div class="ttname"><a href="classarmnn_1_1_base_workload.html#a0a487c549c63319505095b855ea3c195">armnn::BaseWorkload&lt; ArgMinMaxQueueDescriptor &gt;::m_Data</a></div><div class="ttdeci">const ArgMinMaxQueueDescriptor m_Data</div><div class="ttdef"><b>Definition:</b> <a href="_workload_8hpp_source.html#l00046">Workload.hpp:46</a></div></div>
+<div class="ttc" id="_arg_min_max_8hpp_html"><div class="ttname"><a href="_arg_min_max_8hpp.html">ArgMinMax.hpp</a></div></div>
+<div class="ttc" id="_decoders_8hpp_html"><div class="ttname"><a href="_decoders_8hpp.html">Decoders.hpp</a></div></div>
+<div class="ttc" id="namespacearmnn_html"><div class="ttname"><a href="namespacearmnn.html">armnn</a></div><div class="ttdef"><b>Definition:</b> <a href="_backend_helper_8hpp_source.html#l00011">BackendHelper.hpp:11</a></div></div>
+<div class="ttc" id="namespacearmnn_html_a56943a0946e5f15e5e58054b8e7a04a4a2139684546b147c106b329f41547640c"><div class="ttname"><a href="namespacearmnn.html#a56943a0946e5f15e5e58054b8e7a04a4a2139684546b147c106b329f41547640c">armnn::LayerType::ArgMinMax</a></div></div>
+<div class="ttc" id="namespacearmnn_html_ae2f04a162585c0a5222a537efd5456aea83c2c4e9b658ccafbcbe6309c5d84c64"><div class="ttname"><a href="namespacearmnn.html#ae2f04a162585c0a5222a537efd5456aea83c2c4e9b658ccafbcbe6309c5d84c64">armnn::Compute::CpuRef</a></div><div class="ttdoc">CPU Execution: Reference C++ kernels. </div></div>
+<div class="ttc" id="_encoders_8hpp_html"><div class="ttname"><a href="_encoders_8hpp.html">Encoders.hpp</a></div></div>
+<div class="ttc" id="_profiling_8hpp_html"><div class="ttname"><a href="_profiling_8hpp.html">Profiling.hpp</a></div></div>
+<div class="ttc" id="structarmnn_1_1_queue_descriptor_html_a6abd491bb99ffe88bd472c1ae5a1ed1a"><div class="ttname"><a href="structarmnn_1_1_queue_descriptor.html#a6abd491bb99ffe88bd472c1ae5a1ed1a">armnn::QueueDescriptor::m_Outputs</a></div><div class="ttdeci">std::vector&lt; ITensorHandle * &gt; m_Outputs</div><div class="ttdef"><b>Definition:</b> <a href="_workload_data_8hpp_source.html#l00031">WorkloadData.hpp:31</a></div></div>
+<div class="ttc" id="structarmnn_1_1_queue_descriptor_html_a4b50e46a6810018f3edecfb68b2a76b3"><div class="ttname"><a href="structarmnn_1_1_queue_descriptor.html#a4b50e46a6810018f3edecfb68b2a76b3">armnn::QueueDescriptor::m_Inputs</a></div><div class="ttdeci">std::vector&lt; ITensorHandle * &gt; m_Inputs</div><div class="ttdef"><b>Definition:</b> <a href="_workload_data_8hpp_source.html#l00030">WorkloadData.hpp:30</a></div></div>
+<div class="ttc" id="classarmnn_1_1_ref_arg_min_max_workload_html_a1a99463578f57c24906126f682521200"><div class="ttname"><a href="classarmnn_1_1_ref_arg_min_max_workload.html#a1a99463578f57c24906126f682521200">armnn::RefArgMinMaxWorkload::RefArgMinMaxWorkload</a></div><div class="ttdeci">RefArgMinMaxWorkload(const ArgMinMaxQueueDescriptor &amp;descriptor, const WorkloadInfo &amp;info)</div><div class="ttdef"><b>Definition:</b> <a href="_ref_arg_min_max_workload_8cpp_source.html#l00016">RefArgMinMaxWorkload.cpp:16</a></div></div>
+<div class="ttc" id="classarmnn_1_1_base_workload_html"><div class="ttname"><a href="classarmnn_1_1_base_workload.html">armnn::BaseWorkload</a></div><div class="ttdef"><b>Definition:</b> <a href="_workload_8hpp_source.html#l00028">Workload.hpp:28</a></div></div>
+<div class="ttc" id="namespacearmnn_html_a93d269806f34407695dc10f510001c30"><div class="ttname"><a href="namespacearmnn.html#a93d269806f34407695dc10f510001c30">armnn::GetTensorInfo</a></div><div class="ttdeci">const TensorInfo &amp; GetTensorInfo(const ITensorHandle *tensorHandle)</div><div class="ttdoc">float32 helpers </div><div class="ttdef"><b>Definition:</b> <a href="_ref_workload_utils_8hpp_source.html#l00025">RefWorkloadUtils.hpp:25</a></div></div>
+<div class="ttc" id="_ref_workload_utils_8hpp_html"><div class="ttname"><a href="_ref_workload_utils_8hpp.html">RefWorkloadUtils.hpp</a></div></div>
+<div class="ttc" id="structarmnn_1_1_arg_min_max_queue_descriptor_html"><div class="ttname"><a href="structarmnn_1_1_arg_min_max_queue_descriptor.html">armnn::ArgMinMaxQueueDescriptor</a></div><div class="ttdef"><b>Definition:</b> <a href="_workload_data_8hpp_source.html#l00135">WorkloadData.hpp:135</a></div></div>
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