commit ded87bba2c6bbbf93a6db54b5034adf57de39bd3
author Teresa Charlin <teresa.charlinreyes@arm.com> Wed Nov 15 15:42:45 2023 +0000
committer TeresaARM <teresa.charlinreyes@arm.com> Thu Nov 16 09:13:18 2023 +0000
tree ab53066e7155603faab01a976e5878b2b9f58be4
parent d7e3b75ed641406e44dd2b256ad7b0fad931dc1f

IVGCVSW-7937 Review and update documentation related with new operators for 23.11

* GELU added to activation operators, despite not being part of Android NDK
* BROADCAST_TO added to layers, despite not being implemented in any backend
* CAST SIGNED64 added

Change-Id: I32edb9939d28cb997432762e8ea5904f92c12687

Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com>
Change-Id: I6a27ebc1233d77522c1bed1c7e89df95e4d55177

docs/02_operator_list.dox

diff --git a/docs/02_operator_list.dox b/docs/02_operator_list.dox
index a37b6fa..fa386f2 100644
--- a/docs/02_operator_list.dox
+++ b/docs/02_operator_list.dox
@@ -109,6 +109,7 @@
        <li>ANEURALNETWORKS_RELU6
        <li>ANEURALNETWORKS_SQRT
        <li>ANEURALNETWORKS_TANH
+       <li>GELU
       </ul>
    <td>CpuRef
      <td>
@@ -407,6 +408,45 @@
     <tr><td>All
     </table>
 <tr>
+  <td rowspan="3">BroadcastToLayer
+  <td rowspan="3" style="width:200px;"> Layer to broadcast a tensor to a given size.
+  <td rowspan="3">
+      <ul>
+       <li>N/A
+      </ul>
+    <td>CpuRef
+      <td>
+          <ul>
+           <li>N/A
+          </ul>
+      <td>
+       <table>
+       <tr><th>
+       <tr><td>N/A
+       </table>
+  <tr>
+    <td>CpuAcc
+    <td>
+        <ul>
+         <li>N/A
+        </ul>
+    <td>
+      <table>
+      <tr><th>
+      <tr><td>N/A
+      </table>
+  <tr>
+    <td>GpuAcc
+    <td>
+        <ul>
+         <li>N/A
+        </ul>
+    <td>
+      <table>
+      <tr><th>
+      <tr><td>N/A
+      </table>
+  <tr>
   <td rowspan="3">CastLayer
   <td rowspan="3" style="width:200px;"> Layer to cast a tensor to a type.
   <td rowspan="3">
@@ -429,6 +469,7 @@
        <tr><td>QASYMMU8
        <tr><td>QSYMMS16
        <tr><td>SIGNED32
+       <tr><td>SIGNED64
       </table>
 <tr>
   <td>CpuAcc
@@ -439,11 +480,12 @@
   <td>
     <table>
     <tr><th>
+    <tr><td>FLOAT32
+    <tr><td>FLOAT16
     <tr><td>QASYMMS8
     <tr><td>QASYMMU8
-    <tr><td>FLOAT16
     <tr><td>SIGNED32
-    <tr><td>FLOAT32
+    <tr><td>SIGNED64
     </table>
 <tr>
   <td>GpuAcc
@@ -454,11 +496,12 @@
   <td>
     <table>
     <tr><th>
+    <tr><td>FLOAT32
+    <tr><td>FLOAT16
     <tr><td>QASYMMS8
     <tr><td>QASYMMU8
     <tr><td>SIGNED32
-    <tr><td>FLOAT16
-    <tr><td>FLOAT32
+    <tr><td>SIGNED64
     </table>
 <tr>
   <td rowspan="3">ChannelShuffleLayer