commit e4dfd6ead59e17828f8814f0ecc5fa67f0c72868
author Nikhil Raj <nikhil.raj@arm.com> Thu Oct 18 10:11:04 2018 +0100
committer Matthew Bentham <matthew.bentham@arm.com> Mon Oct 22 16:57:54 2018 +0100
tree bb3da260b428d16987374ad3482c46ebb68c20fc
parent 3e9e11541c177abd7101962ef1e703d70d718c56

IVGCVSW-1865 - Support NHWC for Convolution2D (CpuRef)

	* Updated the ConvImpl.hpp to use DataLayoutIndex
	* Enabled unit test for CpuRef
	* Update CreateWorkload Tests for ref with NHWC

Change-Id: Id309b7ef677489d63dcb5e09bd48ab9624b5ebfb

src/backends/reference/test/RefLayerTests.cpp

diff --git a/src/backends/reference/test/RefLayerTests.cpp b/src/backends/reference/test/RefLayerTests.cpp
index 2137161..259739b 100644
--- a/src/backends/reference/test/RefLayerTests.cpp
+++ b/src/backends/reference/test/RefLayerTests.cpp
@@ -36,6 +36,8 @@
     Convolution2dAsymmetricPaddingLargerThanHalfKernelSizeTest)
 ARMNN_AUTO_TEST_CASE(SimpleConvolution2dAsymmetricPadding, Convolution2dAsymmetricPaddingTest)
 
+ARMNN_AUTO_TEST_CASE(SimpleConvolution2dSquareNhwc, SimpleConvolution2d3x3NhwcTest, false)
+
 // Depthwise Convolution
 ARMNN_AUTO_TEST_CASE(DepthwiseConvolution2d, DepthwiseConvolution2dTest, true)
 ARMNN_AUTO_TEST_CASE(DepthwiseConvolution2dUint8, DepthwiseConvolution2dUint8Test, true)