MLCE-156: Add Division workload in CpuAcc
Change-Id: I1f228fcaf1077867d9755a2b850c6703387fab34
Signed-off-by: Pablo Tello <pablo.tello@arm.com>
diff --git a/src/backends/neon/workloads/CMakeLists.txt b/src/backends/neon/workloads/CMakeLists.txt
index d2c549e..46b5332 100644
--- a/src/backends/neon/workloads/CMakeLists.txt
+++ b/src/backends/neon/workloads/CMakeLists.txt
@@ -52,6 +52,8 @@
NeonMinimumWorkload.hpp
NeonMultiplicationWorkload.cpp
NeonMultiplicationWorkload.hpp
+ NeonDivisionWorkload.cpp
+ NeonDivisionWorkload.hpp
NeonNormalizationFloatWorkload.cpp
NeonNormalizationFloatWorkload.hpp
NeonPadWorkload.cpp
diff --git a/src/backends/neon/workloads/NeonDivisionWorkload.cpp b/src/backends/neon/workloads/NeonDivisionWorkload.cpp
new file mode 100644
index 0000000..6fdb455
--- /dev/null
+++ b/src/backends/neon/workloads/NeonDivisionWorkload.cpp
@@ -0,0 +1,45 @@
+//
+// Copyright © 2020 Arm Ltd. All rights reserved.
+// SPDX-License-Identifier: MIT
+//
+
+#include "NeonDivisionWorkload.hpp"
+#include <aclCommon/ArmComputeTensorUtils.hpp>
+#include <backendsCommon/CpuTensorHandle.hpp>
+
+namespace armnn
+{
+
+arm_compute::Status NeonDivisionWorkloadValidate(const TensorInfo& input0,
+ const TensorInfo& input1,
+ const TensorInfo& output)
+{
+ const arm_compute::TensorInfo aclInput0 = armcomputetensorutils::BuildArmComputeTensorInfo(input0);
+ const arm_compute::TensorInfo aclInput1 = armcomputetensorutils::BuildArmComputeTensorInfo(input1);
+ const arm_compute::TensorInfo aclOutput = armcomputetensorutils::BuildArmComputeTensorInfo(output);
+
+ return arm_compute::NEElementwiseDivision::validate(&aclInput0,
+ &aclInput1,
+ &aclOutput);
+}
+
+NeonDivisionWorkload::NeonDivisionWorkload(const DivisionQueueDescriptor& descriptor,
+ const WorkloadInfo& info)
+ : BaseWorkload<DivisionQueueDescriptor>(descriptor, info)
+{
+ m_Data.ValidateInputsOutputs("NeonDivisionWorkload", 2, 1);
+
+ arm_compute::ITensor& input0 = boost::polymorphic_downcast<IAclTensorHandle*>(m_Data.m_Inputs[0])->GetTensor();
+ arm_compute::ITensor& input1 = boost::polymorphic_downcast<IAclTensorHandle*>(m_Data.m_Inputs[1])->GetTensor();
+ arm_compute::ITensor& output = boost::polymorphic_downcast<IAclTensorHandle*>(m_Data.m_Outputs[0])->GetTensor();
+
+ m_DivLayer.configure(&input0, &input1, &output);
+}
+
+void NeonDivisionWorkload::Execute() const
+{
+ ARMNN_SCOPED_PROFILING_EVENT_NEON("NeonDivisionWorkload_Execute");
+ m_DivLayer.run();
+}
+
+} //namespace armnn
diff --git a/src/backends/neon/workloads/NeonDivisionWorkload.hpp b/src/backends/neon/workloads/NeonDivisionWorkload.hpp
new file mode 100644
index 0000000..2405d9a
--- /dev/null
+++ b/src/backends/neon/workloads/NeonDivisionWorkload.hpp
@@ -0,0 +1,30 @@
+//
+// Copyright © 2020 Arm Ltd. All rights reserved.
+// SPDX-License-Identifier: MIT
+//
+
+#pragma once
+
+#include <neon/workloads/NeonWorkloadUtils.hpp>
+
+#include <arm_compute/runtime/NEON/functions/NEElementwiseOperations.h>
+
+namespace armnn
+{
+
+arm_compute::Status NeonDivisionWorkloadValidate(const TensorInfo& input0,
+ const TensorInfo& input1,
+ const TensorInfo& output);
+
+class NeonDivisionWorkload : public BaseWorkload<DivisionQueueDescriptor>
+{
+public:
+ NeonDivisionWorkload(const DivisionQueueDescriptor& descriptor, const WorkloadInfo& info);
+
+ virtual void Execute() const override;
+
+private:
+ mutable arm_compute::NEElementwiseDivision m_DivLayer;
+};
+
+} //namespace armnn
diff --git a/src/backends/neon/workloads/NeonWorkloads.hpp b/src/backends/neon/workloads/NeonWorkloads.hpp
index 104504e..39cf044 100644
--- a/src/backends/neon/workloads/NeonWorkloads.hpp
+++ b/src/backends/neon/workloads/NeonWorkloads.hpp
@@ -7,6 +7,7 @@
#include "NeonAbsWorkload.hpp"
#include "NeonActivationWorkload.hpp"
#include "NeonAdditionWorkload.hpp"
+#include "NeonDivisionWorkload.hpp"
#include "NeonArgMinMaxWorkload.hpp"
#include "NeonBatchNormalizationWorkload.hpp"
#include "NeonConstantWorkload.hpp"