IVGCVSW-5420 'Add CL support for CAST'
Signed-off-by: Sadik Armagan <sadik.armagan@arm.com>
Change-Id: I1bbf1f2edf7282cb69b99e22de1b8a2fe6e443c2
diff --git a/src/backends/cl/ClLayerSupport.cpp b/src/backends/cl/ClLayerSupport.cpp
index cdbbf0c..aa83826 100644
--- a/src/backends/cl/ClLayerSupport.cpp
+++ b/src/backends/cl/ClLayerSupport.cpp
@@ -25,6 +25,7 @@
#include "workloads/ClArgMinMaxWorkload.hpp"
#include "workloads/ClBatchNormalizationFloatWorkload.hpp"
#include "workloads/ClBatchToSpaceNdWorkload.hpp"
+#include "workloads/ClCastWorkload.hpp"
#include "workloads/ClComparisonWorkload.hpp"
#include "workloads/ClConstantWorkload.hpp"
#include "workloads/ClConvertFp16ToFp32Workload.hpp"
@@ -239,6 +240,16 @@
nullptr);
}
+bool ClLayerSupport::IsCastSupported(const TensorInfo& input,
+ const TensorInfo& output,
+ Optional<std::string&> reasonIfUnsupported) const
+{
+ FORWARD_WORKLOAD_VALIDATE_FUNC(ClCastValidate,
+ reasonIfUnsupported,
+ input,
+ output);
+}
+
bool ClLayerSupport::IsBatchToSpaceNdSupported(const TensorInfo& input,
const TensorInfo& output,
const BatchToSpaceNdDescriptor& descriptor,
diff --git a/src/backends/cl/ClLayerSupport.hpp b/src/backends/cl/ClLayerSupport.hpp
index 8b87391..b781541 100644
--- a/src/backends/cl/ClLayerSupport.hpp
+++ b/src/backends/cl/ClLayerSupport.hpp
@@ -52,6 +52,10 @@
const BatchToSpaceNdDescriptor& descriptor,
Optional<std::string&> reasonIfUnsupported = EmptyOptional()) const override;
+ bool IsCastSupported(const TensorInfo& input,
+ const TensorInfo& output,
+ Optional<std::string&> reasonIfUnsupported = EmptyOptional()) const override;
+
bool IsComparisonSupported(const TensorInfo& input0,
const TensorInfo& input1,
const TensorInfo& ouput,
diff --git a/src/backends/cl/ClTensorHandle.hpp b/src/backends/cl/ClTensorHandle.hpp
index 2798de6..061117e 100644
--- a/src/backends/cl/ClTensorHandle.hpp
+++ b/src/backends/cl/ClTensorHandle.hpp
@@ -146,6 +146,7 @@
armcomputetensorutils::CopyArmComputeITensorData(this->GetTensor(),
static_cast<uint8_t*>(memory));
break;
+ case arm_compute::DataType::QSYMM8:
case arm_compute::DataType::QSYMM8_PER_CHANNEL:
case arm_compute::DataType::QASYMM8_SIGNED:
armcomputetensorutils::CopyArmComputeITensorData(this->GetTensor(),
@@ -192,6 +193,7 @@
this->GetTensor());
break;
case arm_compute::DataType::S16:
+ case arm_compute::DataType::QSYMM8:
case arm_compute::DataType::QSYMM8_PER_CHANNEL:
case arm_compute::DataType::QASYMM8_SIGNED:
armcomputetensorutils::CopyArmComputeITensorData(static_cast<const int8_t*>(memory),
@@ -283,6 +285,7 @@
armcomputetensorutils::CopyArmComputeITensorData(this->GetTensor(),
static_cast<armnn::Half*>(memory));
break;
+ case arm_compute::DataType::QSYMM8:
case arm_compute::DataType::QSYMM8_PER_CHANNEL:
case arm_compute::DataType::QASYMM8_SIGNED:
armcomputetensorutils::CopyArmComputeITensorData(this->GetTensor(),
@@ -324,6 +327,7 @@
armcomputetensorutils::CopyArmComputeITensorData(static_cast<const armnn::Half*>(memory),
this->GetTensor());
break;
+ case arm_compute::DataType::QSYMM8:
case arm_compute::DataType::QSYMM8_PER_CHANNEL:
case arm_compute::DataType::QASYMM8_SIGNED:
armcomputetensorutils::CopyArmComputeITensorData(static_cast<const int8_t*>(memory),
diff --git a/src/backends/cl/ClWorkloadFactory.cpp b/src/backends/cl/ClWorkloadFactory.cpp
index 8ff82f2..19ad773 100644
--- a/src/backends/cl/ClWorkloadFactory.cpp
+++ b/src/backends/cl/ClWorkloadFactory.cpp
@@ -236,6 +236,12 @@
return MakeWorkload<ClBatchToSpaceNdWorkload>(descriptor, info, m_CLCompileContext);
}
+std::unique_ptr<IWorkload> ClWorkloadFactory::CreateCast(const CastQueueDescriptor& descriptor,
+ const WorkloadInfo& info) const
+{
+ return MakeWorkload<ClCastWorkload>(descriptor, info, m_CLCompileContext);
+}
+
std::unique_ptr<IWorkload> ClWorkloadFactory::CreateComparison(const ComparisonQueueDescriptor& descriptor,
const WorkloadInfo& info) const
{
diff --git a/src/backends/cl/ClWorkloadFactory.hpp b/src/backends/cl/ClWorkloadFactory.hpp
index 1d2c572..32b0d48 100644
--- a/src/backends/cl/ClWorkloadFactory.hpp
+++ b/src/backends/cl/ClWorkloadFactory.hpp
@@ -74,6 +74,9 @@
std::unique_ptr<IWorkload> CreateBatchToSpaceNd(const BatchToSpaceNdQueueDescriptor& descriptor,
const WorkloadInfo& info) const override;
+ std::unique_ptr<IWorkload> CreateCast(const CastQueueDescriptor& descriptor,
+ const WorkloadInfo& info) const override;
+
std::unique_ptr<IWorkload> CreateComparison(const ComparisonQueueDescriptor& descriptor,
const WorkloadInfo& info) const override;
diff --git a/src/backends/cl/backend.mk b/src/backends/cl/backend.mk
index c097a03..976f614 100644
--- a/src/backends/cl/backend.mk
+++ b/src/backends/cl/backend.mk
@@ -31,6 +31,7 @@
workloads/ClArgMinMaxWorkload.cpp \
workloads/ClBatchNormalizationFloatWorkload.cpp \
workloads/ClBatchToSpaceNdWorkload.cpp \
+ workloads/ClCastWorkload.cpp \
workloads/ClComparisonWorkload.cpp \
workloads/ClConcatWorkload.cpp \
workloads/ClConstantWorkload.cpp \
diff --git a/src/backends/cl/test/ClLayerTests.cpp b/src/backends/cl/test/ClLayerTests.cpp
index 2c6ebf9..e1729fc 100644
--- a/src/backends/cl/test/ClLayerTests.cpp
+++ b/src/backends/cl/test/ClLayerTests.cpp
@@ -1286,6 +1286,12 @@
ARMNN_AUTO_TEST_CASE_WITH_THF(ReduceMinFloat32, ReduceMinSimpleTest<DataType::Float32>)
ARMNN_AUTO_TEST_CASE_WITH_THF(ReduceMinNegativeAxisFloat32, ReduceMinNegativeAxisTest<DataType::Float32>)
+// Cast
+ARMNN_AUTO_TEST_CASE_WITH_THF(CastInt32ToFloat, CastInt32ToFloat2dTest)
+ARMNN_AUTO_TEST_CASE_WITH_THF(CastFloat16ToFloat32, CastFloat16ToFloat322dTest)
+ARMNN_AUTO_TEST_CASE_WITH_THF(CastFloatToFloat16, CastFloat32ToFloat162dTest)
+ARMNN_AUTO_TEST_CASE_WITH_THF(CastFloatToUInt8, CastFloat32ToUInt82dTest)
+
#if defined(ARMNNREF_ENABLED)
// The ARMNN_COMPARE_REF_AUTO_TEST_CASE and the ARMNN_COMPARE_REF_FIXTURE_TEST_CASE test units are not available
diff --git a/src/backends/cl/workloads/CMakeLists.txt b/src/backends/cl/workloads/CMakeLists.txt
index 04821bf..9f1a02f 100644
--- a/src/backends/cl/workloads/CMakeLists.txt
+++ b/src/backends/cl/workloads/CMakeLists.txt
@@ -1,5 +1,5 @@
#
-# Copyright © 2017 Arm Ltd anc Contributors. All rights reserved.
+# Copyright © 2017 Arm Ltd and Contributors. All rights reserved.
# SPDX-License-Identifier: MIT
#
@@ -16,6 +16,8 @@
ClBatchNormalizationFloatWorkload.hpp
ClBatchToSpaceNdWorkload.cpp
ClBatchToSpaceNdWorkload.hpp
+ ClCastWorkload.cpp
+ ClCastWorkload.hpp
ClComparisonWorkload.cpp
ClComparisonWorkload.hpp
ClConcatWorkload.cpp
diff --git a/src/backends/cl/workloads/ClCastWorkload.cpp b/src/backends/cl/workloads/ClCastWorkload.cpp
new file mode 100644
index 0000000..e995e42
--- /dev/null
+++ b/src/backends/cl/workloads/ClCastWorkload.cpp
@@ -0,0 +1,47 @@
+//
+// Copyright © 2021 Arm Ltd and Contributors. All rights reserved.
+// SPDX-License-Identifier: MIT
+//
+
+#include "ClCastWorkload.hpp"
+#include "ClWorkloadUtils.hpp"
+
+#include <armnn/utility/PolymorphicDowncast.hpp>
+
+#include <aclCommon/ArmComputeTensorUtils.hpp>
+
+#include <cl/ClTensorHandle.hpp>
+
+namespace armnn
+{
+
+static constexpr arm_compute::ConvertPolicy g_AclConvertPolicy = arm_compute::ConvertPolicy::SATURATE;
+
+arm_compute::Status ClCastValidate(const TensorInfo& input, const TensorInfo& output)
+{
+ const arm_compute::TensorInfo aclInput = armcomputetensorutils::BuildArmComputeTensorInfo(input);
+ const arm_compute::TensorInfo aclOutput = armcomputetensorutils::BuildArmComputeTensorInfo(output);
+
+ return arm_compute::CLCast::validate(&aclInput, &aclOutput, g_AclConvertPolicy);
+}
+
+ClCastWorkload::ClCastWorkload(const CastQueueDescriptor& descriptor,
+ const WorkloadInfo& info,
+ const arm_compute::CLCompileContext& clCompileContext)
+ : BaseWorkload<CastQueueDescriptor>(descriptor, info)
+{
+ m_Data.ValidateInputsOutputs("ClCastWorkload", 1, 1);
+
+ arm_compute::ICLTensor& input = PolymorphicDowncast<ClTensorHandle*>(m_Data.m_Inputs[0])->GetTensor();
+ arm_compute::ICLTensor& output = PolymorphicDowncast<ClTensorHandle*>(m_Data.m_Outputs[0])->GetTensor();
+
+ m_CastLayer.configure(clCompileContext, &input, &output, g_AclConvertPolicy);
+}
+
+void ClCastWorkload::Execute() const
+{
+ ARMNN_SCOPED_PROFILING_EVENT_CL("ClCastWorkload_Execute");
+ RunClFunction(m_CastLayer, CHECK_LOCATION());
+}
+
+} // namespace armnn
diff --git a/src/backends/cl/workloads/ClCastWorkload.hpp b/src/backends/cl/workloads/ClCastWorkload.hpp
new file mode 100644
index 0000000..ef4c767
--- /dev/null
+++ b/src/backends/cl/workloads/ClCastWorkload.hpp
@@ -0,0 +1,30 @@
+//
+// Copyright © 2021 Arm Ltd and Contributors. All rights reserved.
+// SPDX-License-Identifier: MIT
+//
+
+#pragma once
+
+#include <backendsCommon/Workload.hpp>
+
+#include <arm_compute/core/Error.h>
+#include <arm_compute/runtime/CL/functions/CLCast.h>
+
+namespace armnn
+{
+
+arm_compute::Status ClCastValidate(const TensorInfo& input, const TensorInfo& output);
+
+class ClCastWorkload : public BaseWorkload<CastQueueDescriptor>
+{
+public:
+ ClCastWorkload(const CastQueueDescriptor& descriptor,
+ const WorkloadInfo& info,
+ const arm_compute::CLCompileContext& clCompileContext);
+ virtual void Execute() const override;
+
+private:
+ mutable arm_compute::CLCast m_CastLayer;
+};
+
+} // namespace armnn
diff --git a/src/backends/cl/workloads/ClWorkloads.hpp b/src/backends/cl/workloads/ClWorkloads.hpp
index 0ae7f4e..5488fcd 100644
--- a/src/backends/cl/workloads/ClWorkloads.hpp
+++ b/src/backends/cl/workloads/ClWorkloads.hpp
@@ -12,6 +12,7 @@
#include "ClConstantWorkload.hpp"
#include "ClBatchNormalizationFloatWorkload.hpp"
#include "ClBatchToSpaceNdWorkload.hpp"
+#include "ClCastWorkload.hpp"
#include "ClConvolution2dWorkload.hpp"
#include "ClDepthToSpaceWorkload.hpp"
#include "ClDepthwiseConvolutionWorkload.hpp"