telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 1 | // |
| 2 | // Copyright © 2017 Arm Ltd. All rights reserved. |
David Beck | ecb56cd | 2018-09-05 12:52:57 +0100 | [diff] [blame] | 3 | // SPDX-License-Identifier: MIT |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 4 | // |
| 5 | #include <boost/test/unit_test.hpp> |
| 6 | |
| 7 | #include "test/TensorHelpers.hpp" |
| 8 | #include "LayerTests.hpp" |
| 9 | |
| 10 | #include "backends/CpuTensorHandle.hpp" |
| 11 | #include "backends/NeonLayerSupport.hpp" |
| 12 | #include "backends/NeonWorkloadFactory.hpp" |
| 13 | #include "backends/RefWorkloadFactory.hpp" |
| 14 | #include "backends/test/TensorCopyUtils.hpp" |
| 15 | #include "ActivationFixture.hpp" |
| 16 | |
| 17 | #include "WorkloadTestUtils.hpp" |
| 18 | |
| 19 | #include "test/UnitTests.hpp" |
| 20 | |
| 21 | BOOST_AUTO_TEST_SUITE(Compute_ArmComputeNeon) |
| 22 | using FactoryType = armnn::NeonWorkloadFactory; |
| 23 | |
| 24 | // ============================================================================ |
| 25 | // UNIT tests |
| 26 | |
| 27 | // Convolution |
| 28 | ARMNN_AUTO_TEST_CASE(SimpleConvolution1d, Convolution1dTest, true) |
| 29 | |
| 30 | ARMNN_AUTO_TEST_CASE(SimpleConvolution2d, SimpleConvolution2d3x5Test, true) |
| 31 | ARMNN_AUTO_TEST_CASE(SimpleConvolution2dSquare, SimpleConvolution2d3x3Test, true) |
| 32 | ARMNN_AUTO_TEST_CASE(UnbiasedConvolution2d, SimpleConvolution2d3x5Test, false) |
| 33 | ARMNN_AUTO_TEST_CASE(UnbiasedConvolution2dSquare, SimpleConvolution2d3x3Test, false) |
| 34 | ARMNN_AUTO_TEST_CASE(SimpleConvolution2dAsymmetricPadding, Convolution2dAsymmetricPaddingTest) |
| 35 | |
| 36 | namespace |
| 37 | { |
| 38 | |
| 39 | armnn::Convolution2dDescriptor MakeConv2dDesc(uint32_t strideX, uint32_t strideY, |
| 40 | uint32_t padLeft = 0, uint32_t padRight = 0, uint32_t padTop = 0, uint32_t padBottom = 0) |
| 41 | { |
| 42 | armnn::Convolution2dDescriptor result; |
| 43 | result.m_StrideX = strideX; |
| 44 | result.m_StrideY = strideY; |
| 45 | result.m_PadLeft = padLeft; |
| 46 | result.m_PadRight = padRight; |
| 47 | result.m_PadTop = padTop; |
| 48 | result.m_PadBottom = padBottom; |
| 49 | result.m_BiasEnabled = true; |
| 50 | return result; |
| 51 | } |
| 52 | |
| 53 | } |
| 54 | |
| 55 | BOOST_AUTO_TEST_CASE(Conv2dUtils) |
| 56 | { |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 57 | // The only preferred Neon convolution is 1x1 with padding=0 and stride size {1,2,3}. |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 58 | armnn::TensorShape shape1x1({ 1,1,1,1 }); |
| 59 | armnn::TensorInfo info1x1(shape1x1, armnn::DataType::Float32); |
| 60 | BOOST_TEST(armnn::IsNeonDirectConvolutionPreferred(info1x1, MakeConv2dDesc(1, 1))); |
| 61 | BOOST_TEST(armnn::IsNeonDirectConvolutionPreferred(info1x1, MakeConv2dDesc(1, 2))); |
| 62 | BOOST_TEST(armnn::IsNeonDirectConvolutionPreferred(info1x1, MakeConv2dDesc(1, 3))); |
| 63 | BOOST_TEST(armnn::IsNeonDirectConvolutionPreferred(info1x1, MakeConv2dDesc(2, 1))); |
| 64 | BOOST_TEST(armnn::IsNeonDirectConvolutionPreferred(info1x1, MakeConv2dDesc(2, 2))); |
| 65 | BOOST_TEST(armnn::IsNeonDirectConvolutionPreferred(info1x1, MakeConv2dDesc(2, 3))); |
| 66 | BOOST_TEST(armnn::IsNeonDirectConvolutionPreferred(info1x1, MakeConv2dDesc(3, 1))); |
| 67 | BOOST_TEST(armnn::IsNeonDirectConvolutionPreferred(info1x1, MakeConv2dDesc(3, 2))); |
| 68 | BOOST_TEST(armnn::IsNeonDirectConvolutionPreferred(info1x1, MakeConv2dDesc(3, 3))); |
| 69 | |
| 70 | BOOST_TEST(!armnn::IsNeonDirectConvolutionPreferred(info1x1, MakeConv2dDesc(4, 1))); |
| 71 | BOOST_TEST(!armnn::IsNeonDirectConvolutionPreferred(info1x1, MakeConv2dDesc(4, 5))); |
| 72 | BOOST_TEST(!armnn::IsNeonDirectConvolutionPreferred(info1x1, MakeConv2dDesc(3, 6))); |
| 73 | |
| 74 | // non zero padding is not preferred for direct convolution |
| 75 | BOOST_TEST(!armnn::IsNeonDirectConvolutionPreferred(info1x1, MakeConv2dDesc(1, 1, 1, 0))); |
| 76 | BOOST_TEST(!armnn::IsNeonDirectConvolutionPreferred(info1x1, MakeConv2dDesc(1, 1, 0, 1))); |
| 77 | BOOST_TEST(!armnn::IsNeonDirectConvolutionPreferred(info1x1, MakeConv2dDesc(1, 1, 1, 1))); |
| 78 | |
| 79 | // 2x2 filter not preferred for direct convolution |
| 80 | armnn::TensorShape shape2x2({ 1,1,2,2 }); |
| 81 | armnn::TensorInfo info2x2(shape2x2, armnn::DataType::Float32); |
| 82 | BOOST_TEST(!armnn::IsNeonDirectConvolutionPreferred(info2x2, MakeConv2dDesc(1, 1))); |
| 83 | } |
| 84 | |
| 85 | // Depthwise Convolution |
| 86 | ARMNN_AUTO_TEST_CASE(DepthwiseConvolution2dDepthMul1, DepthwiseConvolution2dDepthMul1Test, true) |
| 87 | ARMNN_AUTO_TEST_CASE(UnbiasedDepthwiseConvolution2dDepthMul1, DepthwiseConvolution2dDepthMul1Test, false) |
| 88 | ARMNN_AUTO_TEST_CASE(DepthwiseConvolution2dDepthMul1Uint8, DepthwiseConvolution2dDepthMul1Uint8Test, true) |
| 89 | ARMNN_AUTO_TEST_CASE(UnbiasedDepthwiseConvolution2dDepthMul1Uint8, DepthwiseConvolution2dDepthMul1Uint8Test, false) |
| 90 | |
surmeh01 | 3537c2c | 2018-05-18 16:31:43 +0100 | [diff] [blame] | 91 | ARMNN_AUTO_TEST_CASE(DepthwiseConvolution2dAsymmetric, DepthwiseConvolution2dAsymmetricTest, true) |
| 92 | ARMNN_AUTO_TEST_CASE(UnbiasedDepthwiseConvolution2dAsymmetric, DepthwiseConvolution2dAsymmetricTest, false) |
| 93 | |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 94 | namespace |
| 95 | { |
| 96 | |
| 97 | armnn::DepthwiseConvolution2dDescriptor MakeDepthwiseConv2dDesc(uint32_t strideX, uint32_t strideY, |
| 98 | uint32_t depthMultiplier = 1, uint32_t padLeft = 0, uint32_t padRight = 0, |
| 99 | uint32_t padTop = 0, uint32_t padBottom = 0) |
| 100 | { |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 101 | boost::ignore_unused(depthMultiplier); |
| 102 | |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 103 | armnn::DepthwiseConvolution2dDescriptor desc; |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 104 | |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 105 | desc.m_PadLeft = padLeft; |
| 106 | desc.m_PadRight = padRight; |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 107 | |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 108 | desc.m_PadTop = padTop; |
| 109 | desc.m_PadBottom = padBottom; |
| 110 | desc.m_StrideX = strideX; |
| 111 | desc.m_StrideY = strideY; |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 112 | desc.m_BiasEnabled = false; |
| 113 | |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 114 | return desc; |
| 115 | } |
| 116 | |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 117 | armnn::TensorInfo CreateOutputTensorInfo(const armnn::TensorInfo& inputInfo, |
| 118 | const armnn::TensorInfo& weightsInfo, |
| 119 | const armnn::DepthwiseConvolution2dDescriptor& descriptor, |
| 120 | armnn::DataType dataType) |
| 121 | { |
| 122 | const armnn::TensorShape& inputShape = inputInfo.GetShape(); |
| 123 | const armnn::TensorShape& filterShape = weightsInfo.GetShape(); |
| 124 | |
| 125 | unsigned int inWidth = inputShape[3]; |
| 126 | unsigned int inHeight = inputShape[2]; |
| 127 | unsigned int inBatchSize = inputShape[0]; |
| 128 | |
| 129 | unsigned int filterWidth = filterShape[3]; |
| 130 | unsigned int readWidth = (inWidth + descriptor.m_PadLeft + descriptor.m_PadRight) - (filterWidth); |
| 131 | unsigned int outWidth = 1u + (readWidth / descriptor.m_StrideX); |
| 132 | |
| 133 | unsigned int filterHeight = filterShape[2]; |
| 134 | unsigned int readHeight = (inHeight + descriptor.m_PadTop + descriptor.m_PadBottom) - (filterHeight); |
| 135 | unsigned int outHeight = 1u + (readHeight / descriptor.m_StrideY); |
| 136 | unsigned int depthMultiplier = filterShape[0]; |
| 137 | |
| 138 | unsigned int outChannels = filterShape[1] * depthMultiplier; |
| 139 | unsigned int outBatchSize = inBatchSize; |
| 140 | |
| 141 | armnn::TensorShape outputShape({outBatchSize, outChannels, outHeight, outWidth}); |
| 142 | return armnn::TensorInfo(outputShape, dataType); |
| 143 | } |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 144 | } |
| 145 | |
| 146 | BOOST_AUTO_TEST_CASE(DepthwiseConv2dUtils) |
| 147 | { |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 148 | const armnn::DataType dataType = armnn::DataType::Float32; |
| 149 | |
| 150 | armnn::TensorInfo inputInfo({1, 1, 10, 10 }, dataType); |
| 151 | armnn::TensorInfo outputInfo; |
| 152 | armnn::TensorInfo weightsInfo3x3({ 1, 1, 3, 3 }, dataType); |
| 153 | armnn::TensorInfo biasesInfo; |
| 154 | |
| 155 | armnn::DepthwiseConvolution2dDescriptor descriptor; |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 156 | |
| 157 | // Strides supported: 1,2,3 |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 158 | descriptor = MakeDepthwiseConv2dDesc(1, 1); |
| 159 | outputInfo = CreateOutputTensorInfo(inputInfo, weightsInfo3x3, descriptor, dataType); |
| 160 | BOOST_TEST(armnn::IsDepthwiseConvolutionSupportedNeon(inputInfo, outputInfo, descriptor, |
| 161 | weightsInfo3x3, biasesInfo)); |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 162 | |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 163 | descriptor = MakeDepthwiseConv2dDesc(1, 2); |
| 164 | outputInfo = CreateOutputTensorInfo(inputInfo, weightsInfo3x3, descriptor, dataType); |
| 165 | BOOST_TEST(armnn::IsDepthwiseConvolutionSupportedNeon(inputInfo, outputInfo, descriptor, |
| 166 | weightsInfo3x3, biasesInfo)); |
| 167 | |
| 168 | descriptor = MakeDepthwiseConv2dDesc(1, 3); |
| 169 | outputInfo = CreateOutputTensorInfo(inputInfo, weightsInfo3x3, descriptor, dataType); |
| 170 | BOOST_TEST(armnn::IsDepthwiseConvolutionSupportedNeon(inputInfo, outputInfo, descriptor, |
| 171 | weightsInfo3x3, biasesInfo)); |
| 172 | |
| 173 | descriptor = MakeDepthwiseConv2dDesc(2, 1); |
| 174 | outputInfo = CreateOutputTensorInfo(inputInfo, weightsInfo3x3, descriptor, dataType); |
| 175 | BOOST_TEST(armnn::IsDepthwiseConvolutionSupportedNeon(inputInfo, outputInfo, descriptor, |
| 176 | weightsInfo3x3, biasesInfo)); |
| 177 | |
| 178 | descriptor = MakeDepthwiseConv2dDesc(2, 2); |
| 179 | outputInfo = CreateOutputTensorInfo(inputInfo, weightsInfo3x3, descriptor, dataType); |
| 180 | BOOST_TEST(armnn::IsDepthwiseConvolutionSupportedNeon(inputInfo, outputInfo, descriptor, |
| 181 | weightsInfo3x3, biasesInfo)); |
| 182 | |
| 183 | descriptor = MakeDepthwiseConv2dDesc(2, 3); |
| 184 | outputInfo = CreateOutputTensorInfo(inputInfo, weightsInfo3x3, descriptor, dataType); |
| 185 | BOOST_TEST(armnn::IsDepthwiseConvolutionSupportedNeon(inputInfo, outputInfo, descriptor, |
| 186 | weightsInfo3x3, biasesInfo)); |
| 187 | |
| 188 | descriptor = MakeDepthwiseConv2dDesc(3, 1); |
| 189 | outputInfo = CreateOutputTensorInfo(inputInfo, weightsInfo3x3, descriptor, dataType); |
| 190 | BOOST_TEST(armnn::IsDepthwiseConvolutionSupportedNeon(inputInfo, outputInfo, descriptor, |
| 191 | weightsInfo3x3, biasesInfo)); |
| 192 | |
| 193 | descriptor = MakeDepthwiseConv2dDesc(3, 2); |
| 194 | outputInfo = CreateOutputTensorInfo(inputInfo, weightsInfo3x3, descriptor, dataType); |
| 195 | BOOST_TEST(armnn::IsDepthwiseConvolutionSupportedNeon(inputInfo, outputInfo, descriptor, |
| 196 | weightsInfo3x3, biasesInfo)); |
| 197 | |
| 198 | descriptor = MakeDepthwiseConv2dDesc(3, 3); |
| 199 | outputInfo = CreateOutputTensorInfo(inputInfo, weightsInfo3x3, descriptor, dataType); |
| 200 | BOOST_TEST(armnn::IsDepthwiseConvolutionSupportedNeon(inputInfo, outputInfo, descriptor, |
| 201 | weightsInfo3x3, biasesInfo)); |
| 202 | |
| 203 | // Supported stride 4 |
| 204 | descriptor = MakeDepthwiseConv2dDesc(4, 1); |
| 205 | outputInfo = CreateOutputTensorInfo(inputInfo, weightsInfo3x3, descriptor, dataType); |
| 206 | BOOST_TEST(armnn::IsDepthwiseConvolutionSupportedNeon(inputInfo, outputInfo, descriptor, |
| 207 | weightsInfo3x3, biasesInfo)); |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 208 | |
| 209 | // Supported weights shape 1x1 |
| 210 | armnn::TensorInfo weightsInfo1x1({ 1, 1, 1, 1 }, armnn::DataType::Float32); |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 211 | descriptor = MakeDepthwiseConv2dDesc(1, 1); |
| 212 | outputInfo = CreateOutputTensorInfo(inputInfo, weightsInfo1x1, descriptor, dataType); |
| 213 | BOOST_TEST(armnn::IsDepthwiseConvolutionSupportedNeon(inputInfo, outputInfo, descriptor, |
| 214 | weightsInfo1x1, biasesInfo)); |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 215 | |
| 216 | // Supported shape 2x2 |
| 217 | armnn::TensorInfo weightsInfo2x2({ 1, 1, 2, 2 }, armnn::DataType::Float32); |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 218 | descriptor = MakeDepthwiseConv2dDesc(1, 1); |
| 219 | outputInfo = CreateOutputTensorInfo(inputInfo, weightsInfo2x2, descriptor, dataType); |
| 220 | BOOST_TEST(armnn::IsDepthwiseConvolutionSupportedNeon(inputInfo, outputInfo, descriptor, |
| 221 | weightsInfo2x2, biasesInfo)); |
surmeh01 | 3537c2c | 2018-05-18 16:31:43 +0100 | [diff] [blame] | 222 | |
| 223 | // Asymmetric padding |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 224 | descriptor = MakeDepthwiseConv2dDesc(1, 1, 1, 1, 2, 1, 2); |
| 225 | outputInfo = CreateOutputTensorInfo(inputInfo, weightsInfo3x3, descriptor, dataType); |
| 226 | BOOST_TEST(armnn::IsDepthwiseConvolutionSupportedNeon(inputInfo, outputInfo, descriptor, |
| 227 | weightsInfo3x3, biasesInfo)); |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 228 | } |
| 229 | |
| 230 | // Pooling |
| 231 | ARMNN_AUTO_TEST_CASE(SimpleMaxPooling2dSize3x3Stride2x4, SimpleMaxPooling2dSize3x3Stride2x4Test, true) |
| 232 | ARMNN_AUTO_TEST_CASE(SimpleMaxPooling2dSize3x3Stride2x4Uint8, SimpleMaxPooling2dSize3x3Stride2x4Uint8Test, true) |
| 233 | ARMNN_AUTO_TEST_CASE(SimpleAveragePooling2d, SimpleAveragePooling2dTest) |
| 234 | ARMNN_AUTO_TEST_CASE(SimpleAveragePooling2dUint8, SimpleAveragePooling2dUint8Test) |
surmeh01 | bceff2f | 2018-03-29 16:29:27 +0100 | [diff] [blame] | 235 | |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 236 | ARMNN_AUTO_TEST_CASE(LargeTensorsAveragePooling2d, LargeTensorsAveragePooling2dTest) |
| 237 | ARMNN_AUTO_TEST_CASE(LargeTensorsAveragePooling2dUint8, LargeTensorsAveragePooling2dUint8Test) |
| 238 | |
| 239 | ARMNN_AUTO_TEST_CASE(SimpleL2Pooling2d, SimpleL2Pooling2dTest) |
| 240 | ARMNN_AUTO_TEST_CASE(UNSUPPORTED_SimpleL2Pooling2dUint8, SimpleL2Pooling2dUint8Test) |
| 241 | ARMNN_AUTO_TEST_CASE(L2Pooling2dSize3Stride1, L2Pooling2dSize3Stride1Test) |
| 242 | ARMNN_AUTO_TEST_CASE(UNSUPPORTED_L2Pooling2dSize3Stride1Uint8, L2Pooling2dSize3Stride1Uint8Test) |
| 243 | ARMNN_AUTO_TEST_CASE(L2Pooling2dSize3Stride3, L2Pooling2dSize3Stride3Test) |
| 244 | ARMNN_AUTO_TEST_CASE(UNSUPPORTED_L2Pooling2dSize3Stride3Uint8, L2Pooling2dSize3Stride3Uint8Test) |
| 245 | ARMNN_AUTO_TEST_CASE(L2Pooling2dSize3Stride4, L2Pooling2dSize3Stride4Test) |
| 246 | ARMNN_AUTO_TEST_CASE(UNSUPPORTED_L2Pooling2dSize3Stride4Uint8, L2Pooling2dSize3Stride4Uint8Test) |
| 247 | ARMNN_AUTO_TEST_CASE(L2Pooling2dSize7, L2Pooling2dSize7Test) |
| 248 | ARMNN_AUTO_TEST_CASE(UNSUPPORTED_L2Pooling2dSize7Uint8, L2Pooling2dSize7Uint8Test) |
| 249 | ARMNN_AUTO_TEST_CASE(L2Pooling2dSize9, L2Pooling2dSize9Test) |
| 250 | ARMNN_AUTO_TEST_CASE(UNSUPPORTED_L2Pooling2dSize9Uint8, L2Pooling2dSize9Uint8Test) |
| 251 | |
| 252 | // Ignore padding values for pooling but count padding fields into the divisor |
| 253 | ARMNN_AUTO_TEST_CASE(IgnorePaddingSimpleMaxPooling2d, IgnorePaddingSimpleMaxPooling2dTest) |
| 254 | ARMNN_AUTO_TEST_CASE(IgnorePaddingSimpleMaxPooling2dUint8, IgnorePaddingSimpleMaxPooling2dUint8Test) |
| 255 | ARMNN_AUTO_TEST_CASE(IgnorePaddingMaxPooling2dSize3, IgnorePaddingMaxPooling2dSize3Test) |
| 256 | ARMNN_AUTO_TEST_CASE(IgnorePaddingMaxPooling2dSize3Uint8, IgnorePaddingMaxPooling2dSize3Uint8Test) |
| 257 | |
| 258 | ARMNN_AUTO_TEST_CASE(IgnorePaddingSimpleAveragePooling2d, IgnorePaddingSimpleAveragePooling2dTest) |
| 259 | ARMNN_AUTO_TEST_CASE(IgnorePaddingSimpleAveragePooling2dUint8, IgnorePaddingSimpleAveragePooling2dUint8Test) |
| 260 | ARMNN_AUTO_TEST_CASE(IgnorePaddingSimpleAveragePooling2dNoPadding, IgnorePaddingSimpleAveragePooling2dNoPaddingTest) |
| 261 | ARMNN_AUTO_TEST_CASE(IgnorePaddingSimpleAveragePooling2dNoPaddingUint8, |
| 262 | IgnorePaddingSimpleAveragePooling2dNoPaddingUint8Test) |
| 263 | ARMNN_AUTO_TEST_CASE(IgnorePaddingAveragePooling2dSize3, IgnorePaddingAveragePooling2dSize3Test) |
| 264 | ARMNN_AUTO_TEST_CASE(IgnorePaddingAveragePooling2dSize3Uint8, IgnorePaddingAveragePooling2dSize3Uint8Test) |
surmeh01 | bceff2f | 2018-03-29 16:29:27 +0100 | [diff] [blame] | 265 | ARMNN_AUTO_TEST_CASE(IgnorePaddingAveragePooling2dSize3x2Stride2x2, |
| 266 | IgnorePaddingAveragePooling2dSize3x2Stride2x2Test, false) |
| 267 | ARMNN_AUTO_TEST_CASE(IgnorePaddingAveragePooling2dSize3x2Stride2x2NoPadding, |
| 268 | IgnorePaddingAveragePooling2dSize3x2Stride2x2Test, |
| 269 | true) |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 270 | |
| 271 | ARMNN_AUTO_TEST_CASE(IgnorePaddingSimpleL2Pooling2d, IgnorePaddingSimpleL2Pooling2dTest) |
| 272 | ARMNN_AUTO_TEST_CASE(UNSUPPORTED_IgnorePaddingSimpleL2Pooling2dUint8, IgnorePaddingSimpleL2Pooling2dUint8Test) |
| 273 | ARMNN_AUTO_TEST_CASE(IgnorePaddingL2Pooling2dSize3, IgnorePaddingL2Pooling2dSize3Test) |
| 274 | ARMNN_AUTO_TEST_CASE(UNSUPPORTED_IgnorePaddingL2Pooling2dSize3Uint8, IgnorePaddingL2Pooling2dSize3Uint8Test) |
| 275 | |
| 276 | // Activation |
| 277 | ARMNN_AUTO_TEST_CASE(ConstantLinearActivation, ConstantLinearActivationTest) |
| 278 | |
| 279 | ARMNN_AUTO_TEST_CASE(SimpleSoftmaxBeta1, SimpleSoftmaxTest, 1.0f) |
| 280 | ARMNN_AUTO_TEST_CASE(SimpleSoftmaxBeta2, SimpleSoftmaxTest, 2.0f) |
| 281 | |
| 282 | ARMNN_AUTO_TEST_CASE(SimpleSoftmaxBeta1Uint8, SimpleSoftmaxUint8Test, 1.0f) |
| 283 | ARMNN_AUTO_TEST_CASE(SimpleSoftmaxBeta2Uint8, SimpleSoftmaxUint8Test, 2.0f) |
| 284 | |
| 285 | ARMNN_AUTO_TEST_CASE(ReLu1Uint8, BoundedReLuUint8UpperAndLowerBoundTest) |
| 286 | ARMNN_AUTO_TEST_CASE(ReLu6Uint8, BoundedReLuUint8UpperBoundOnlyTest) |
| 287 | |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 288 | // Softmax |
| 289 | BOOST_AUTO_TEST_CASE(Softmax4dSupport) |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 290 | { |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 291 | const unsigned int numDimensions = 4u; |
| 292 | std::array<unsigned int, numDimensions> dimensionSizes; |
| 293 | dimensionSizes.fill(1u); |
| 294 | |
| 295 | const armnn::TensorInfo inputInfo(numDimensions, &dimensionSizes.front(), armnn::DataType::Float32); |
| 296 | const armnn::TensorInfo outputInfo(numDimensions, &dimensionSizes.front(), armnn::DataType::Float32); |
| 297 | |
| 298 | // 4D Softmax should be reported as unsupported on the NEON backend |
| 299 | BOOST_TEST(!armnn::IsSoftmaxSupportedNeon(inputInfo, outputInfo, armnn::SoftmaxDescriptor())); |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 300 | } |
| 301 | |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 302 | // Splitter |
| 303 | ARMNN_AUTO_TEST_CASE(SimpleSplitter, SplitterTest) |
| 304 | ARMNN_AUTO_TEST_CASE(SimpleSplitterUint8, SplitterUint8Test) |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 305 | |
| 306 | ARMNN_AUTO_TEST_CASE(CopyViaSplitter, CopyViaSplitterTest) |
| 307 | ARMNN_AUTO_TEST_CASE(CopyViaSplitterUint8, CopyViaSplitterUint8Test) |
| 308 | |
| 309 | // Merger |
| 310 | ARMNN_AUTO_TEST_CASE(SimpleMerger, MergerTest) |
| 311 | ARMNN_AUTO_TEST_CASE(MergerUint8, MergerUint8Test) |
| 312 | |
| 313 | // Fully Connected |
| 314 | ARMNN_AUTO_TEST_CASE(SimpleFullyConnected, FullyConnectedFloat32Test, false, false) |
| 315 | ARMNN_AUTO_TEST_CASE(SimpleFullyConnectedWithBias, FullyConnectedFloat32Test, true, false) |
| 316 | ARMNN_AUTO_TEST_CASE(SimpleFullyConnectedWithTranspose, FullyConnectedFloat32Test, false, true) |
| 317 | ARMNN_AUTO_TEST_CASE(FullyConnectedLarge, FullyConnectedLargeTest, false) |
| 318 | ARMNN_AUTO_TEST_CASE(FullyConnectedLargeTransposed, FullyConnectedLargeTest, true) |
| 319 | |
| 320 | // Add |
| 321 | ARMNN_AUTO_TEST_CASE(SimpleAdd, AdditionTest) |
David Beck | bc39245 | 2018-09-10 14:47:28 +0100 | [diff] [blame] | 322 | ARMNN_AUTO_TEST_CASE(AddBroadcast, AdditionBroadcastTest) |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 323 | ARMNN_AUTO_TEST_CASE(AddBroadcast1Element, AdditionBroadcast1ElementTest) |
| 324 | |
David Beck | bc39245 | 2018-09-10 14:47:28 +0100 | [diff] [blame] | 325 | // Sub |
| 326 | ARMNN_AUTO_TEST_CASE(SimpleSub, SubtractionTest) |
| 327 | |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 328 | // Mul |
| 329 | ARMNN_AUTO_TEST_CASE(SimpleMultiplication, MultiplicationTest) |
surmeh01 | 3537c2c | 2018-05-18 16:31:43 +0100 | [diff] [blame] | 330 | ARMNN_AUTO_TEST_CASE(MultiplicationBroadcast1Element, MultiplicationBroadcast1ElementTest) |
| 331 | ARMNN_AUTO_TEST_CASE(MultiplicationBroadcast1DVector, MultiplicationBroadcast1DVectorTest) |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 332 | |
| 333 | // Batch Norm |
| 334 | ARMNN_AUTO_TEST_CASE(BatchNorm, BatchNormTest) |
| 335 | |
| 336 | // Constant |
| 337 | ARMNN_AUTO_TEST_CASE(Constant, ConstantTest) |
| 338 | ARMNN_AUTO_TEST_CASE(ConstantUint8, ConstantTestUint8) |
| 339 | |
| 340 | // Concatenation |
| 341 | ARMNN_AUTO_TEST_CASE(Concatenation1d, Concatenation1dTest) |
| 342 | ARMNN_AUTO_TEST_CASE(Concatenation1dUint8, Concatenation1dUint8Test) |
| 343 | |
| 344 | ARMNN_AUTO_TEST_CASE(Concatenation2dDim0, Concatenation2dDim0Test) |
| 345 | ARMNN_AUTO_TEST_CASE(Concatenation2dDim0Uint8, Concatenation2dDim0Uint8Test) |
| 346 | ARMNN_AUTO_TEST_CASE(Concatenation2dDim1, Concatenation2dDim1Test) |
| 347 | ARMNN_AUTO_TEST_CASE(Concatenation2dDim1Uint8, Concatenation2dDim1Uint8Test) |
| 348 | |
| 349 | ARMNN_AUTO_TEST_CASE(Concatenation2dDim0DiffInputDims, Concatenation2dDim0DiffInputDimsTest) |
| 350 | ARMNN_AUTO_TEST_CASE(Concatenation2dDim0DiffInputDimsUint8, Concatenation2dDim0DiffInputDimsUint8Test) |
| 351 | ARMNN_AUTO_TEST_CASE(Concatenation2dDim1DiffInputDims, Concatenation2dDim1DiffInputDimsTest) |
| 352 | ARMNN_AUTO_TEST_CASE(Concatenation2dDim1DiffInputDimsUint8, Concatenation2dDim1DiffInputDimsUint8Test) |
| 353 | |
| 354 | ARMNN_AUTO_TEST_CASE(Concatenation3dDim0, Concatenation3dDim0Test) |
| 355 | ARMNN_AUTO_TEST_CASE(Concatenation3dDim0Uint8, Concatenation3dDim0Uint8Test) |
| 356 | ARMNN_AUTO_TEST_CASE(Concatenation3dDim1, Concatenation3dDim1Test) |
| 357 | ARMNN_AUTO_TEST_CASE(Concatenation3dDim1Uint8, Concatenation3dDim1Uint8Test) |
| 358 | ARMNN_AUTO_TEST_CASE(Concatenation3dDim2, Concatenation3dDim2Test) |
| 359 | ARMNN_AUTO_TEST_CASE(Concatenation3dDim2Uint8, Concatenation3dDim2Uint8Test) |
| 360 | |
| 361 | ARMNN_AUTO_TEST_CASE(Concatenation3dDim0DiffInputDims, Concatenation3dDim0DiffInputDimsTest) |
| 362 | ARMNN_AUTO_TEST_CASE(Concatenation3dDim0DiffInputDimsUint8, Concatenation3dDim0DiffInputDimsUint8Test) |
| 363 | ARMNN_AUTO_TEST_CASE(Concatenation3dDim1DiffInputDims, Concatenation3dDim1DiffInputDimsTest) |
| 364 | ARMNN_AUTO_TEST_CASE(Concatenation3dDim1DiffInputDimsUint8, Concatenation3dDim1DiffInputDimsUint8Test) |
| 365 | ARMNN_AUTO_TEST_CASE(Concatenation3dDim2DiffInputDims, Concatenation3dDim2DiffInputDimsTest) |
| 366 | ARMNN_AUTO_TEST_CASE(Concatenation3dDim2DiffInputDimsUint8, Concatenation3dDim2DiffInputDimsUint8Test) |
| 367 | |
| 368 | // L2 Normalization |
| 369 | ARMNN_AUTO_TEST_CASE(L2Normalization1d, L2Normalization1dTest); |
| 370 | ARMNN_AUTO_TEST_CASE(L2Normalization2d, L2Normalization2dTest); |
| 371 | ARMNN_AUTO_TEST_CASE(L2Normalization3d, L2Normalization3dTest); |
| 372 | ARMNN_AUTO_TEST_CASE(L2Normalization4d, L2Normalization4dTest); |
| 373 | |
| 374 | // Floor |
| 375 | ARMNN_AUTO_TEST_CASE(SimpleFloor, SimpleFloorTest) |
| 376 | |
| 377 | // Reshape |
| 378 | ARMNN_AUTO_TEST_CASE(SimpleReshapeFloat32, SimpleReshapeFloat32Test) |
| 379 | ARMNN_AUTO_TEST_CASE(SimpleReshapeUint8, SimpleReshapeUint8Test) |
| 380 | |
| 381 | // Permute |
| 382 | ARMNN_AUTO_TEST_CASE(SimplePermuteFloat32, SimplePermuteFloat32Test) |
| 383 | ARMNN_AUTO_TEST_CASE(SimplePermuteUint8, SimplePermuteUint8Test) |
surmeh01 | bceff2f | 2018-03-29 16:29:27 +0100 | [diff] [blame] | 384 | ARMNN_AUTO_TEST_CASE(PermuteFloat32ValueSet1, PermuteFloat32ValueSet1Test) |
| 385 | ARMNN_AUTO_TEST_CASE(PermuteFloat32ValueSet2, PermuteFloat32ValueSet2Test) |
| 386 | ARMNN_AUTO_TEST_CASE(PermuteFloat32ValueSet3, PermuteFloat32ValueSet3Test) |
| 387 | |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 388 | // ============================================================================ |
| 389 | // COMPARE tests |
| 390 | |
| 391 | ARMNN_COMPARE_REF_AUTO_TEST_CASE(CompareConv2dWithReference, CompareConvolution2dTest) |
| 392 | |
| 393 | ARMNN_COMPARE_REF_AUTO_TEST_CASE(CompareDepthwiseConv2dWithReferenceFloat32, CompareDepthwiseConvolution2dTest<float>) |
| 394 | ARMNN_COMPARE_REF_AUTO_TEST_CASE(CompareDepthwiseConv2dWithReferenceUint8, CompareDepthwiseConvolution2dTest<uint8_t>) |
| 395 | |
| 396 | ARMNN_COMPARE_REF_AUTO_TEST_CASE(CompareNormalizationWithinWithReference, CompareNormalizationTest, |
| 397 | armnn::NormalizationAlgorithmChannel::Within, |
| 398 | armnn::NormalizationAlgorithmMethod::LocalBrightness) |
| 399 | ARMNN_COMPARE_REF_AUTO_TEST_CASE(CompareNormalizationAcrossWithReference, CompareNormalizationTest, |
| 400 | armnn::NormalizationAlgorithmChannel::Across, |
| 401 | armnn::NormalizationAlgorithmMethod::LocalBrightness) |
| 402 | |
| 403 | ARMNN_COMPARE_REF_AUTO_TEST_CASE(CompareMaxPooling2dWithReference, ComparePooling2dTest, armnn::PoolingAlgorithm::Max) |
| 404 | ARMNN_COMPARE_REF_AUTO_TEST_CASE(CompareMaxPooling2dWithReferenceUint8, ComparePooling2dUint8Test, |
| 405 | armnn::PoolingAlgorithm::Max) |
| 406 | ARMNN_COMPARE_REF_AUTO_TEST_CASE(CompareAveragePooling2dWithReference, ComparePooling2dTest, |
| 407 | armnn::PoolingAlgorithm::Average) |
| 408 | ARMNN_COMPARE_REF_AUTO_TEST_CASE(CompareAveragePooling2dWithReferenceUint8, ComparePooling2dUint8Test, |
| 409 | armnn::PoolingAlgorithm::Average) |
| 410 | ARMNN_COMPARE_REF_AUTO_TEST_CASE(CompareL2Pooling2dWithReference, ComparePooling2dTest, armnn::PoolingAlgorithm::L2) |
| 411 | ARMNN_COMPARE_REF_AUTO_TEST_CASE(UNSUPPORTED_CompareL2Pooling2dWithReferenceUint8, ComparePooling2dUint8Test, |
| 412 | armnn::PoolingAlgorithm::L2) |
| 413 | |
| 414 | ARMNN_COMPARE_REF_AUTO_TEST_CASE(CompareSoftmaxBeta1WithReference, CompareSoftmaxTest, 1.0f) |
| 415 | ARMNN_COMPARE_REF_AUTO_TEST_CASE(CompareSoftmaxBeta2WithReference, CompareSoftmaxTest, 2.0f) |
| 416 | |
| 417 | ARMNN_COMPARE_REF_AUTO_TEST_CASE(CompareSoftmaxUint8Beta1WithReference, CompareSoftmaxUint8Test, 1.0f) |
| 418 | ARMNN_COMPARE_REF_AUTO_TEST_CASE(CompareSoftmaxUint8Beta2WithReference, CompareSoftmaxUint8Test, 2.0f) |
| 419 | |
| 420 | ARMNN_COMPARE_REF_AUTO_TEST_CASE(CompareAddition, CompareAdditionTest) |
| 421 | |
| 422 | ARMNN_COMPARE_REF_AUTO_TEST_CASE(CompareMultiplicationWithReference, CompareMultiplicationTest) |
| 423 | |
| 424 | ARMNN_COMPARE_REF_AUTO_TEST_CASE(CompareBatchNorm, CompareBatchNormTest) |
| 425 | |
| 426 | ARMNN_COMPARE_REF_AUTO_TEST_CASE(ReLu1, CompareBoundedReLuTest, 1.0f, -1.0f) |
| 427 | ARMNN_COMPARE_REF_AUTO_TEST_CASE(ReLu6, CompareBoundedReLuTest, 6.0f, 0.0f) |
| 428 | |
| 429 | // ============================================================================ |
| 430 | // FIXTURE tests |
| 431 | |
| 432 | ARMNN_COMPARE_REF_FIXTURE_TEST_CASE(CompareSigmoidActivationWithReference, ActivationFixture, |
| 433 | CompareActivationTest, armnn::ActivationFunction::Sigmoid, 5u) |
| 434 | |
| 435 | ARMNN_COMPARE_REF_FIXTURE_TEST_CASE(CompareTanhActivationWithReference, ActivationFixture, |
| 436 | CompareActivationTest, armnn::ActivationFunction::TanH, 5u) |
| 437 | |
| 438 | ARMNN_COMPARE_REF_FIXTURE_TEST_CASE(CompareLinearActivationWithReference, ActivationFixture, |
| 439 | CompareActivationTest, armnn::ActivationFunction::Linear, 5u) |
| 440 | |
| 441 | ARMNN_COMPARE_REF_FIXTURE_TEST_CASE(CompareReLuActivationWithReference, ActivationFixture, |
| 442 | CompareActivationTest, armnn::ActivationFunction::ReLu, 5u) |
| 443 | |
| 444 | ARMNN_COMPARE_REF_FIXTURE_TEST_CASE(CompareBoundedReLuActivationWithReference, ActivationFixture, |
| 445 | CompareActivationTest, armnn::ActivationFunction::BoundedReLu, 5u) |
| 446 | ARMNN_COMPARE_REF_FIXTURE_TEST_CASE(CompareBoundedReLuActivationWithReferenceUint8, ActivationFixture, |
| 447 | CompareActivationUint8Test, armnn::ActivationFunction::BoundedReLu) |
| 448 | |
| 449 | ARMNN_COMPARE_REF_FIXTURE_TEST_CASE(CompareSoftReLuActivationWithReference, ActivationFixture, |
| 450 | CompareActivationTest, armnn::ActivationFunction::SoftReLu, 1u) |
| 451 | |
| 452 | ARMNN_COMPARE_REF_FIXTURE_TEST_CASE(CompareLeakyReLuActivationWithReference, ActivationFixture, |
| 453 | CompareActivationTest, armnn::ActivationFunction::LeakyReLu, 5u) |
| 454 | |
| 455 | ARMNN_COMPARE_REF_FIXTURE_TEST_CASE(CompareAbsActivationWithReference, ActivationFixture, |
| 456 | CompareActivationTest, armnn::ActivationFunction::Abs, 5u) |
| 457 | |
| 458 | ARMNN_COMPARE_REF_FIXTURE_TEST_CASE(CompareSqrtActivationWithReference, PositiveActivationFixture, |
| 459 | CompareActivationTest, armnn::ActivationFunction::Sqrt, 5u) |
| 460 | |
| 461 | ARMNN_COMPARE_REF_FIXTURE_TEST_CASE(CompareSquareActivationWithReference, ActivationFixture, |
| 462 | CompareActivationTest, armnn::ActivationFunction::Square, 5u) |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 463 | BOOST_AUTO_TEST_SUITE_END() |