Teresa Charlin | 50de4fa | 2021-05-31 18:47:33 +0100 | [diff] [blame] | 1 | // |
| 2 | // Copyright © 2021 Arm Ltd and Contributors. All rights reserved. |
| 3 | // SPDX-License-Identifier: MIT |
| 4 | // |
| 5 | |
| 6 | #include "ClLogWorkload.hpp" |
| 7 | |
| 8 | #include "ClWorkloadUtils.hpp" |
| 9 | |
| 10 | #include <aclCommon/ArmComputeTensorUtils.hpp> |
| 11 | #include <armnn/utility/PolymorphicDowncast.hpp> |
| 12 | |
| 13 | #include <cl/ClTensorHandle.hpp> |
| 14 | |
| 15 | namespace armnn |
| 16 | { |
| 17 | |
| 18 | arm_compute::Status ClLogWorkloadValidate(const TensorInfo& input, const TensorInfo& output) |
| 19 | { |
| 20 | const arm_compute::TensorInfo aclInput = armcomputetensorutils::BuildArmComputeTensorInfo(input); |
| 21 | const arm_compute::TensorInfo aclOutput = armcomputetensorutils::BuildArmComputeTensorInfo(output); |
| 22 | |
| 23 | return arm_compute::CLLogLayer::validate(&aclInput, &aclOutput); |
| 24 | } |
| 25 | |
| 26 | ClLogWorkload::ClLogWorkload(const ElementwiseUnaryQueueDescriptor& descriptor, |
| 27 | const WorkloadInfo& info, |
| 28 | const arm_compute::CLCompileContext& clCompileContext) |
| 29 | : BaseWorkload<ElementwiseUnaryQueueDescriptor>(descriptor, info) |
| 30 | { |
| 31 | m_Data.ValidateInputsOutputs("ClLogWorkload", 1, 1); |
| 32 | |
| 33 | arm_compute::ICLTensor& input = PolymorphicDowncast<ClTensorHandle*>(m_Data.m_Inputs[0])->GetTensor(); |
| 34 | arm_compute::ICLTensor& output = PolymorphicDowncast<ClTensorHandle*>(m_Data.m_Outputs[0])->GetTensor(); |
| 35 | |
| 36 | m_LogLayer.configure(clCompileContext, &input, &output); |
| 37 | } |
| 38 | |
| 39 | void ClLogWorkload::Execute() const |
| 40 | { |
Keith Davis | bcd860a | 2021-08-05 14:20:33 +0100 | [diff] [blame] | 41 | ARMNN_SCOPED_PROFILING_EVENT_CL_GUID("ClLogWorkload_Execute", this->GetGuid()); |
Teresa Charlin | 50de4fa | 2021-05-31 18:47:33 +0100 | [diff] [blame] | 42 | RunClFunction(m_LogLayer, CHECK_LOCATION()); |
| 43 | } |
| 44 | |
| 45 | } // namespace armnn |