telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 1 | // |
| 2 | // Copyright © 2017 Arm Ltd. All rights reserved. |
David Beck | ecb56cd | 2018-09-05 12:52:57 +0100 | [diff] [blame] | 3 | // SPDX-License-Identifier: MIT |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 4 | // |
| 5 | |
| 6 | #include "RefDepthwiseConvolution2dFloat32Workload.hpp" |
| 7 | |
| 8 | #include "ConvImpl.hpp" |
| 9 | #include "RefWorkloadUtils.hpp" |
| 10 | |
| 11 | #include "Profiling.hpp" |
| 12 | |
| 13 | namespace armnn |
| 14 | { |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 15 | RefDepthwiseConvolution2dFloat32Workload::RefDepthwiseConvolution2dFloat32Workload( |
| 16 | const DepthwiseConvolution2dQueueDescriptor& descriptor, const WorkloadInfo& info) |
| 17 | : Float32Workload<DepthwiseConvolution2dQueueDescriptor>(descriptor, info), |
| 18 | m_Weight(std::make_unique<ScopedCpuTensorHandle>(*(descriptor.m_Weight))), |
| 19 | m_Bias(descriptor.m_Parameters.m_BiasEnabled |
| 20 | ? std::make_unique<ScopedCpuTensorHandle>(*(descriptor.m_Bias)) : nullptr) {} |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 21 | |
| 22 | void RefDepthwiseConvolution2dFloat32Workload::Execute() const |
| 23 | { |
| 24 | ARMNN_SCOPED_PROFILING_EVENT(Compute::CpuRef, "RefDepthwiseConvolution2dFloat32Workload_Execute"); |
| 25 | |
| 26 | float* outputData = GetOutputTensorDataFloat(0, m_Data); |
| 27 | const float* inputData = GetInputTensorDataFloat(0, m_Data); |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 28 | const float* weightData = m_Weight->template GetConstTensor<float>(); |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 29 | const float* biasData = m_Data.m_Parameters.m_BiasEnabled ? |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 30 | m_Bias->template GetConstTensor<float>() : nullptr; |
| 31 | const TensorInfo& filterInfo = m_Weight->GetTensorInfo(); |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 32 | |
| 33 | ConvImpl<armnn::DepthwiseConvolution2dQueueDescriptor, float, float, float> |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 34 | (m_Data, inputData, 0.0f, 0, weightData, 0.0f, 0, biasData, outputData, 0.0f, 0, filterInfo, true); |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 35 | } |
| 36 | |
| 37 | } //namespace armnn |