Narumol Prangnawarat | 0b51d5a | 2021-01-20 15:58:29 +0000 | [diff] [blame] | 1 | // |
| 2 | // Copyright © 2021 Arm Ltd and Contributors. All rights reserved. |
| 3 | // SPDX-License-Identifier: MIT |
| 4 | // |
| 5 | |
| 6 | #include "DelegateOptionsTestHelper.hpp" |
Nikhil Raj | 7dcc697 | 2021-04-30 15:44:24 +0100 | [diff] [blame] | 7 | #include <common/include/ProfilingGuid.hpp> |
Narumol Prangnawarat | 0b51d5a | 2021-01-20 15:58:29 +0000 | [diff] [blame] | 8 | |
| 9 | namespace armnnDelegate |
| 10 | { |
| 11 | |
| 12 | TEST_SUITE("DelegateOptions") |
| 13 | { |
| 14 | |
| 15 | TEST_CASE ("ArmnnDelegateOptimizerOptionsReduceFp32ToFp16") |
| 16 | { |
| 17 | std::stringstream ss; |
| 18 | { |
| 19 | StreamRedirector redirect(std::cout, ss.rdbuf()); |
| 20 | |
| 21 | std::vector<armnn::BackendId> backends = { armnn::Compute::CpuRef }; |
| 22 | std::vector<int32_t> tensorShape { 1, 2, 2, 1 }; |
| 23 | std::vector<float> inputData = { 1, 2, 3, 4 }; |
| 24 | std::vector<float> divData = { 2, 2, 3, 4 }; |
| 25 | std::vector<float> expectedResult = { 1, 2, 2, 2 }; |
| 26 | |
| 27 | // Enable ReduceFp32ToFp16 |
| 28 | armnn::OptimizerOptions optimizerOptions(true, true, false, false); |
Narumol Prangnawarat | 74a3cf5 | 2021-01-29 15:38:54 +0000 | [diff] [blame] | 29 | armnnDelegate::DelegateOptions delegateOptions(backends, optimizerOptions); |
Narumol Prangnawarat | 0b51d5a | 2021-01-20 15:58:29 +0000 | [diff] [blame] | 30 | |
| 31 | DelegateOptionTest<float>(::tflite::TensorType_FLOAT32, |
| 32 | backends, |
| 33 | tensorShape, |
| 34 | inputData, |
| 35 | inputData, |
| 36 | divData, |
| 37 | expectedResult, |
| 38 | delegateOptions); |
| 39 | } |
| 40 | // ReduceFp32ToFp16 option is enabled |
| 41 | CHECK(ss.str().find("convert_fp32_to_fp16") != std::string::npos); |
| 42 | CHECK(ss.str().find("convert_fp16_to_fp32") != std::string::npos); |
| 43 | } |
| 44 | |
| 45 | TEST_CASE ("ArmnnDelegateOptimizerOptionsDebug") |
| 46 | { |
| 47 | std::stringstream ss; |
| 48 | { |
| 49 | StreamRedirector redirect(std::cout, ss.rdbuf()); |
| 50 | |
| 51 | std::vector<armnn::BackendId> backends = { armnn::Compute::CpuRef }; |
| 52 | std::vector<int32_t> tensorShape { 1, 2, 2, 1 }; |
| 53 | std::vector<float> inputData = { 1, 2, 3, 4 }; |
| 54 | std::vector<float> divData = { 2, 2, 3, 4 }; |
| 55 | std::vector<float> expectedResult = { 1, 2, 2, 2 }; |
| 56 | |
| 57 | // Enable Debug |
| 58 | armnn::OptimizerOptions optimizerOptions(false, true, false, false); |
Narumol Prangnawarat | 74a3cf5 | 2021-01-29 15:38:54 +0000 | [diff] [blame] | 59 | armnnDelegate::DelegateOptions delegateOptions(backends, optimizerOptions); |
Narumol Prangnawarat | 0b51d5a | 2021-01-20 15:58:29 +0000 | [diff] [blame] | 60 | |
| 61 | DelegateOptionTest<float>(::tflite::TensorType_FLOAT32, |
| 62 | backends, |
| 63 | tensorShape, |
| 64 | inputData, |
| 65 | inputData, |
| 66 | divData, |
| 67 | expectedResult, |
| 68 | delegateOptions); |
| 69 | } |
| 70 | // Debug option triggered. |
| 71 | CHECK(ss.str().find("layerGuid") != std::string::npos); |
| 72 | CHECK(ss.str().find("layerName") != std::string::npos); |
| 73 | CHECK(ss.str().find("outputSlot") != std::string::npos); |
| 74 | CHECK(ss.str().find("shape") != std::string::npos); |
| 75 | CHECK(ss.str().find("data") != std::string::npos); |
| 76 | } |
| 77 | |
| 78 | TEST_CASE ("ArmnnDelegateOptimizerOptionsDebugFunction") |
| 79 | { |
| 80 | std::vector<armnn::BackendId> backends = { armnn::Compute::CpuRef }; |
| 81 | std::vector<int32_t> tensorShape { 1, 2, 2, 1 }; |
| 82 | std::vector<float> inputData = { 1, 2, 3, 4 }; |
| 83 | std::vector<float> divData = { 2, 2, 3, 4 }; |
| 84 | std::vector<float> expectedResult = { 1, 2, 2, 2 }; |
| 85 | |
| 86 | // Enable debug with debug callback function |
| 87 | armnn::OptimizerOptions optimizerOptions(false, true, false, false); |
| 88 | bool callback = false; |
| 89 | auto mockCallback = [&](armnn::LayerGuid guid, unsigned int slotIndex, armnn::ITensorHandle* tensor) |
| 90 | { |
| 91 | armnn::IgnoreUnused(guid); |
| 92 | armnn::IgnoreUnused(slotIndex); |
| 93 | armnn::IgnoreUnused(tensor); |
| 94 | callback = true; |
| 95 | }; |
| 96 | |
Francis Murtagh | 73d3e2e | 2021-04-29 14:23:04 +0100 | [diff] [blame] | 97 | armnn::INetworkProperties networkProperties(false, armnn::MemorySource::Undefined, armnn::MemorySource::Undefined); |
Narumol Prangnawarat | 0b51d5a | 2021-01-20 15:58:29 +0000 | [diff] [blame] | 98 | armnnDelegate::DelegateOptions delegateOptions(backends, |
| 99 | optimizerOptions, |
Narumol Prangnawarat | 0b51d5a | 2021-01-20 15:58:29 +0000 | [diff] [blame] | 100 | armnn::EmptyOptional(), |
| 101 | armnn::Optional<armnn::DebugCallbackFunction>(mockCallback)); |
| 102 | |
| 103 | CHECK(!callback); |
| 104 | |
| 105 | DelegateOptionTest<float>(::tflite::TensorType_FLOAT32, |
| 106 | backends, |
| 107 | tensorShape, |
| 108 | inputData, |
| 109 | inputData, |
| 110 | divData, |
| 111 | expectedResult, |
| 112 | delegateOptions); |
| 113 | |
| 114 | // Check that the debug callback function was called. |
| 115 | CHECK(callback); |
| 116 | } |
| 117 | |
| 118 | TEST_CASE ("ArmnnDelegateOptimizerOptionsReduceFp32ToBf16") |
| 119 | { |
| 120 | std::stringstream ss; |
| 121 | { |
| 122 | StreamRedirector redirect(std::cout, ss.rdbuf()); |
| 123 | |
| 124 | ReduceFp32ToBf16TestImpl(); |
| 125 | } |
| 126 | |
| 127 | // ReduceFp32ToBf16 option is enabled |
| 128 | CHECK(ss.str().find("convert_fp32_to_bf16") != std::string::npos); |
| 129 | } |
| 130 | |
| 131 | TEST_CASE ("ArmnnDelegateOptimizerOptionsImport") |
| 132 | { |
| 133 | std::vector<armnn::BackendId> backends = { armnn::Compute::CpuAcc, armnn::Compute::CpuRef }; |
| 134 | std::vector<int32_t> tensorShape { 1, 2, 2, 1 }; |
| 135 | std::vector<uint8_t> inputData = { 1, 2, 3, 4 }; |
| 136 | std::vector<uint8_t> divData = { 2, 2, 3, 4 }; |
Narumol Prangnawarat | 74a3cf5 | 2021-01-29 15:38:54 +0000 | [diff] [blame] | 137 | std::vector<uint8_t> expectedResult = { 1, 2, 2, 2 }; |
Narumol Prangnawarat | 0b51d5a | 2021-01-20 15:58:29 +0000 | [diff] [blame] | 138 | |
| 139 | armnn::OptimizerOptions optimizerOptions(false, false, false, true); |
Narumol Prangnawarat | 74a3cf5 | 2021-01-29 15:38:54 +0000 | [diff] [blame] | 140 | armnnDelegate::DelegateOptions delegateOptions(backends, optimizerOptions); |
Narumol Prangnawarat | 0b51d5a | 2021-01-20 15:58:29 +0000 | [diff] [blame] | 141 | |
| 142 | DelegateOptionTest<uint8_t>(::tflite::TensorType_UINT8, |
| 143 | backends, |
| 144 | tensorShape, |
| 145 | inputData, |
| 146 | inputData, |
| 147 | divData, |
| 148 | expectedResult, |
| 149 | delegateOptions); |
| 150 | } |
| 151 | |
| 152 | } |
| 153 | |
Matthew Sloyan | 0a7dc6b | 2021-02-10 16:50:53 +0000 | [diff] [blame] | 154 | TEST_SUITE("DelegateOptions_CpuAccTests") |
| 155 | { |
| 156 | |
| 157 | TEST_CASE ("ArmnnDelegateModelOptions_CpuAcc_Test") |
| 158 | { |
| 159 | std::vector<armnn::BackendId> backends = { armnn::Compute::CpuAcc }; |
| 160 | std::vector<int32_t> tensorShape { 1, 2, 2, 1 }; |
| 161 | std::vector<float> inputData = { 1, 2, 3, 4 }; |
| 162 | std::vector<float> divData = { 2, 2, 3, 4 }; |
| 163 | std::vector<float> expectedResult = { 1, 2, 2, 2 }; |
| 164 | |
| 165 | unsigned int numberOfThreads = 2; |
| 166 | |
| 167 | armnn::ModelOptions modelOptions; |
| 168 | armnn::BackendOptions cpuAcc("CpuAcc", |
| 169 | { |
| 170 | { "FastMathEnabled", true }, |
| 171 | { "NumberOfThreads", numberOfThreads } |
| 172 | }); |
| 173 | modelOptions.push_back(cpuAcc); |
| 174 | |
| 175 | armnn::OptimizerOptions optimizerOptions(false, false, false, false, modelOptions); |
| 176 | armnnDelegate::DelegateOptions delegateOptions(backends, optimizerOptions); |
| 177 | |
| 178 | DelegateOptionTest<float>(::tflite::TensorType_FLOAT32, |
| 179 | backends, |
| 180 | tensorShape, |
| 181 | inputData, |
| 182 | inputData, |
| 183 | divData, |
| 184 | expectedResult, |
| 185 | delegateOptions); |
| 186 | } |
| 187 | |
| 188 | } |
| 189 | |
Narumol Prangnawarat | 0b51d5a | 2021-01-20 15:58:29 +0000 | [diff] [blame] | 190 | } // namespace armnnDelegate |