Sadik Armagan | 32ca144 | 2020-11-13 17:51:56 +0000 | [diff] [blame] | 1 | // |
| 2 | // Copyright © 2020 Arm Ltd and Contributors. All rights reserved. |
| 3 | // SPDX-License-Identifier: MIT |
| 4 | // |
| 5 | |
| 6 | #include "ConvolutionTestHelper.hpp" |
| 7 | |
| 8 | #include <armnn_delegate.hpp> |
| 9 | |
| 10 | #include <flatbuffers/flatbuffers.h> |
| 11 | #include <tensorflow/lite/interpreter.h> |
| 12 | #include <tensorflow/lite/kernels/register.h> |
| 13 | #include <tensorflow/lite/model.h> |
| 14 | #include <tensorflow/lite/schema/schema_generated.h> |
| 15 | #include <tensorflow/lite/version.h> |
| 16 | |
| 17 | #include <doctest/doctest.h> |
| 18 | |
| 19 | namespace armnnDelegate |
| 20 | { |
| 21 | |
| 22 | void DepthwiseConv2dValidReluFp32Test(std::vector<armnn::BackendId>& backends) |
| 23 | { |
| 24 | // Set input data |
| 25 | std::vector<int32_t> inputShape { 1, 3, 2, 2 }; |
| 26 | std::vector<int32_t> filterShape { 1, 2, 2, 4 }; |
| 27 | std::vector<int32_t> biasShape { 4 }; |
| 28 | std::vector<int32_t> outputShape { 1, 3, 3, 1 }; |
| 29 | |
| 30 | static std::vector<float> inputValues = |
| 31 | { |
| 32 | 1, 2, 7, 8, |
| 33 | 3, 4, 9, 10, |
| 34 | 5, 6, 11, 12 |
| 35 | }; |
| 36 | |
| 37 | std::vector<float> filterValues = |
| 38 | { |
| 39 | 1, 2, 3, 4, |
| 40 | -9, 10, -11, 12, |
| 41 | 5, 6, 7, 8, |
| 42 | 13, -14, 15, -16 |
| 43 | }; |
| 44 | |
| 45 | std::vector<float> biasValues = { 1, 2, 3, 4 }; |
| 46 | |
| 47 | std::vector<float> expectedOutputValues = |
| 48 | { |
| 49 | 71, 0, 99, 0, |
| 50 | 91, 0, 127, 0 |
| 51 | }; |
| 52 | |
| 53 | tflite::Padding padding = tflite::Padding_VALID; |
| 54 | int32_t depth_multiplier = 2; |
| 55 | |
| 56 | ConvolutionTest<float>(tflite::BuiltinOperator_DEPTHWISE_CONV_2D, |
| 57 | ::tflite::TensorType_FLOAT32, |
| 58 | 1, // strideX |
| 59 | 1, // strideY |
| 60 | 1, // dilationX |
| 61 | 1, // dilationY |
| 62 | padding, |
| 63 | tflite::ActivationFunctionType_RELU, |
| 64 | backends, |
| 65 | inputShape, |
| 66 | filterShape, |
| 67 | outputShape, |
| 68 | inputValues, |
| 69 | filterValues, |
| 70 | expectedOutputValues, |
| 71 | biasShape, |
| 72 | biasValues, |
| 73 | 1.0f, // filterScale |
| 74 | 0, // filterOffset |
| 75 | 2.0f, // outputQuantScale |
| 76 | 0, // outputQuantOffset |
| 77 | 1.0f, // quantScale |
| 78 | 0, // quantOffset |
| 79 | depth_multiplier); |
| 80 | } |
| 81 | |
| 82 | void DepthwiseConv2dSameUint8Test(std::vector<armnn::BackendId>& backends) |
| 83 | { |
| 84 | // Set input data |
| 85 | std::vector<int32_t> inputShape { 1, 3, 3, 1 }; |
| 86 | std::vector<int32_t> filterShape { 1, 3, 3, 1 }; |
| 87 | std::vector<int32_t> biasShape { 1 } ; |
| 88 | std::vector<int32_t> outputShape { 1, 3, 3, 1 }; |
| 89 | |
| 90 | static std::vector<uint8_t> inputValues = |
| 91 | { |
| 92 | 0, 1, 2, |
| 93 | 3, 4, 5, |
| 94 | 6, 7, 8 |
| 95 | }; |
| 96 | |
| 97 | std::vector<uint8_t> filterValues = { 9, 8, 7, 6, 5, 4, 3, 2, 1 }; |
| 98 | |
| 99 | std::vector<int32_t> biasValues = { 10 }; |
| 100 | |
| 101 | std::vector<uint8_t> expectedOutputValues = |
| 102 | { |
| 103 | 12, 23, 24, // ( 14+10)/2, ( 35+10)/2, ( 38+10)/2, |
| 104 | 34, 65, 61, // ( 57+10)/2, (120+10)/2, (111+10)/2, |
| 105 | 60, 104, 84 // (110+10)/2, (197+10)/2, (158+10)/2 |
| 106 | }; |
| 107 | |
| 108 | tflite::Padding padding = tflite::Padding_SAME; |
| 109 | |
| 110 | ConvolutionTest<uint8_t, int32_t>(tflite::BuiltinOperator_DEPTHWISE_CONV_2D, |
| 111 | ::tflite::TensorType_UINT8, |
| 112 | 1, // strideX |
| 113 | 1, // strideY |
| 114 | 1, // dilationX |
| 115 | 1, // dilationY |
| 116 | padding, |
| 117 | tflite::ActivationFunctionType_NONE, |
| 118 | backends, |
| 119 | inputShape, |
| 120 | filterShape, |
| 121 | outputShape, |
| 122 | inputValues, |
| 123 | filterValues, |
| 124 | expectedOutputValues, |
| 125 | biasShape, |
| 126 | biasValues); |
| 127 | } |
| 128 | |
| 129 | TEST_SUITE("DepthwiseConv2d_CpuRef_Tests") |
| 130 | { |
| 131 | |
| 132 | TEST_CASE ("DepthwiseConv2d_Valid_Relu_Fp32_CpuRef_Test") |
| 133 | { |
| 134 | std::vector<armnn::BackendId> backends = {armnn::Compute::CpuRef}; |
| 135 | DepthwiseConv2dValidReluFp32Test(backends); |
| 136 | } |
| 137 | |
| 138 | TEST_CASE ("DepthwiseConv2d_Same_Uint8_CpuRef_Test") |
| 139 | { |
| 140 | std::vector<armnn::BackendId> backends = {armnn::Compute::CpuRef}; |
| 141 | DepthwiseConv2dSameUint8Test(backends); |
| 142 | } |
| 143 | |
| 144 | }//End of TEST_SUITE("DepthwiseConv2d_CpuRef_Tests") |
| 145 | |
| 146 | TEST_SUITE("DepthwiseConv2d_CpuAcc_Tests") |
| 147 | { |
| 148 | |
| 149 | TEST_CASE ("DepthwiseConv2d_Valid_Relu_Fp32_CpuAcc_Test") |
| 150 | { |
| 151 | std::vector<armnn::BackendId> backends = {armnn::Compute::CpuAcc}; |
| 152 | DepthwiseConv2dValidReluFp32Test(backends); |
| 153 | } |
| 154 | |
| 155 | TEST_CASE ("DepthwiseConv2d_Same_Uint8_CpuAcc_Test") |
| 156 | { |
| 157 | std::vector<armnn::BackendId> backends = {armnn::Compute::CpuAcc}; |
| 158 | DepthwiseConv2dSameUint8Test(backends); |
| 159 | } |
| 160 | |
| 161 | }//End of TEST_SUITE("DepthwiseConv2d_CpuAcc_Tests") |
| 162 | |
| 163 | TEST_SUITE("DepthwiseConv2d_GpuAcc_Tests") |
| 164 | { |
| 165 | |
| 166 | TEST_CASE ("DepthwiseConv2d_Valid_Relu_Fp32_GpuAcc_Test") |
| 167 | { |
| 168 | std::vector<armnn::BackendId> backends = {armnn::Compute::GpuAcc}; |
| 169 | DepthwiseConv2dValidReluFp32Test(backends); |
| 170 | } |
| 171 | |
| 172 | TEST_CASE ("DepthwiseConv2d_Same_Uint8_GpuAcc_Test") |
| 173 | { |
| 174 | std::vector<armnn::BackendId> backends = {armnn::Compute::GpuAcc}; |
| 175 | DepthwiseConv2dSameUint8Test(backends); |
| 176 | } |
| 177 | |
| 178 | }//End of TEST_SUITE("DepthwiseConv2d_GpuAcc_Tests") |
| 179 | |
| 180 | } // namespace armnnDelegate |