telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 1 | // |
| 2 | // Copyright © 2017 Arm Ltd. All rights reserved. |
David Beck | ecb56cd | 2018-09-05 12:52:57 +0100 | [diff] [blame] | 3 | // SPDX-License-Identifier: MIT |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 4 | // |
| 5 | #pragma once |
| 6 | |
Matteo Martincigh | e5b8eb9 | 2019-11-28 15:45:42 +0000 | [diff] [blame] | 7 | #include <armnn/backends/CpuTensorHandleFwd.hpp> |
| 8 | #include <armnn/backends/ITensorHandle.hpp> |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 9 | |
Aron Virginas-Tar | c9cc804 | 2018-11-01 16:15:57 +0000 | [diff] [blame] | 10 | #include <InternalTypes.hpp> |
| 11 | |
Jim Flynn | e242f2d | 2019-05-22 14:24:13 +0100 | [diff] [blame] | 12 | #include <armnn/Deprecated.hpp> |
David Beck | 0dbe0ee | 2018-09-24 15:59:27 +0100 | [diff] [blame] | 13 | #include <armnn/Descriptors.hpp> |
| 14 | #include <armnn/Exceptions.hpp> |
Aron Virginas-Tar | c9cc804 | 2018-11-01 16:15:57 +0000 | [diff] [blame] | 15 | #include <armnn/Types.hpp> |
| 16 | #include <armnn/Tensor.hpp> |
David Beck | 0dbe0ee | 2018-09-24 15:59:27 +0100 | [diff] [blame] | 17 | |
Aron Virginas-Tar | c9cc804 | 2018-11-01 16:15:57 +0000 | [diff] [blame] | 18 | #include <backendsCommon/WorkloadInfo.hpp> |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 19 | |
| 20 | namespace armnn |
| 21 | { |
| 22 | |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 23 | //A helper function that returns the bias data type required for given input data type. |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 24 | DataType GetBiasDataType(DataType inputDataType); |
| 25 | |
| 26 | struct WorkloadInfo; |
| 27 | |
| 28 | struct QueueDescriptor |
| 29 | { |
| 30 | std::vector<ITensorHandle*> m_Inputs; |
| 31 | std::vector<ITensorHandle*> m_Outputs; |
| 32 | |
| 33 | void ValidateInputsOutputs(const std::string& descName, |
Narumol Prangnawarat | 867eba5 | 2020-02-03 12:29:56 +0000 | [diff] [blame] | 34 | unsigned int numExpectedIn, |
| 35 | unsigned int numExpectedOut) const; |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 36 | |
| 37 | |
| 38 | protected: |
| 39 | ~QueueDescriptor() = default; |
| 40 | QueueDescriptor() = default; |
| 41 | QueueDescriptor(QueueDescriptor const&) = default; |
| 42 | QueueDescriptor& operator=(QueueDescriptor const&) = default; |
| 43 | }; |
| 44 | |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 45 | // Base class for queue descriptors which contain parameters. |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 46 | template <typename LayerDescriptor> |
| 47 | struct QueueDescriptorWithParameters : public QueueDescriptor |
| 48 | { |
| 49 | LayerDescriptor m_Parameters; |
| 50 | |
| 51 | protected: |
| 52 | ~QueueDescriptorWithParameters() = default; |
| 53 | QueueDescriptorWithParameters() = default; |
| 54 | QueueDescriptorWithParameters(QueueDescriptorWithParameters const&) = default; |
| 55 | QueueDescriptorWithParameters& operator=(QueueDescriptorWithParameters const&) = default; |
| 56 | }; |
| 57 | |
| 58 | struct MemCopyQueueDescriptor : QueueDescriptor |
| 59 | { |
| 60 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 61 | }; |
| 62 | |
| 63 | using InputQueueDescriptor = MemCopyQueueDescriptor; |
| 64 | using OutputQueueDescriptor = MemCopyQueueDescriptor; |
| 65 | |
Derek Lamberti | f674aa0 | 2019-08-01 15:56:25 +0100 | [diff] [blame] | 66 | struct MemImportQueueDescriptor : QueueDescriptor |
| 67 | { |
| 68 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 69 | }; |
| 70 | |
| 71 | struct MemSyncQueueDescriptor : QueueDescriptor |
| 72 | { |
| 73 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 74 | }; |
| 75 | |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 76 | // Softmax layer workload data. |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 77 | struct SoftmaxQueueDescriptor : QueueDescriptorWithParameters<SoftmaxDescriptor> |
| 78 | { |
| 79 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 80 | }; |
| 81 | |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 82 | // Splitter layer workload data. |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 83 | struct SplitterQueueDescriptor : QueueDescriptorWithParameters<ViewsDescriptor> |
| 84 | { |
| 85 | struct ViewOrigin |
| 86 | { |
| 87 | ViewOrigin() {} |
| 88 | ViewOrigin(std::vector<unsigned int> const& origin) : m_Origin(origin) {} |
| 89 | |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 90 | //View origin (size of the vector is the same as number of dimensions of the view). |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 91 | std::vector<unsigned int> m_Origin; |
| 92 | }; |
| 93 | |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 94 | //View defines a tensor that will be carved from the input tensor. |
| 95 | //View origins are stored here, the extents are defined by sizes of the output tensors. |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 96 | std::vector<ViewOrigin> m_ViewOrigins; |
| 97 | |
| 98 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 99 | }; |
| 100 | |
Jim Flynn | e242f2d | 2019-05-22 14:24:13 +0100 | [diff] [blame] | 101 | // Concat layer workload data. |
| 102 | struct ConcatQueueDescriptor : QueueDescriptorWithParameters<OriginsDescriptor> |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 103 | { |
| 104 | struct ViewOrigin |
| 105 | { |
| 106 | ViewOrigin() {} |
| 107 | ViewOrigin(const std::vector<unsigned int>& origin) : m_Origin(origin) {} |
| 108 | |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 109 | //View origin (size of the vector is the same as number of dimensions of the view). |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 110 | std::vector<unsigned int> m_Origin; |
| 111 | }; |
| 112 | |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 113 | //View defines a sub-area of the output tensor that will be filled with the corresponding input tensor. |
| 114 | //View origins are stored here, the extents are defined by sizes of the input tensors. |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 115 | std::vector<ViewOrigin> m_ViewOrigins; |
| 116 | |
| 117 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 118 | }; |
| 119 | |
Jim Flynn | e242f2d | 2019-05-22 14:24:13 +0100 | [diff] [blame] | 120 | // Deprecated. Use ConcatQueueDescriptor instead |
| 121 | using MergerQueueDescriptor = ConcatQueueDescriptor; |
| 122 | |
Matthew Jackson | 2b8c1da | 2019-07-04 14:59:16 +0100 | [diff] [blame] | 123 | // Stack layer workload data. |
| 124 | struct StackQueueDescriptor : QueueDescriptorWithParameters<StackDescriptor> |
| 125 | { |
| 126 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 127 | }; |
| 128 | |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 129 | // Activation layer workload data. |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 130 | struct ActivationQueueDescriptor : QueueDescriptorWithParameters<ActivationDescriptor> |
| 131 | { |
| 132 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 133 | }; |
| 134 | |
Nikhil Raj | ee391d5 | 2019-09-05 17:50:44 +0100 | [diff] [blame] | 135 | struct ArgMinMaxQueueDescriptor : QueueDescriptorWithParameters<ArgMinMaxDescriptor> |
| 136 | { |
| 137 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 138 | }; |
| 139 | |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 140 | // Fully connected layer workload data. |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 141 | struct FullyConnectedQueueDescriptor : QueueDescriptorWithParameters<FullyConnectedDescriptor> |
| 142 | { |
| 143 | FullyConnectedQueueDescriptor() |
| 144 | : m_Weight(nullptr) |
| 145 | , m_Bias(nullptr) |
| 146 | { |
| 147 | } |
| 148 | |
| 149 | const ConstCpuTensorHandle* m_Weight; |
| 150 | const ConstCpuTensorHandle* m_Bias; |
| 151 | |
| 152 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 153 | }; |
| 154 | |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 155 | // Permute layer workload data. |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 156 | struct PermuteQueueDescriptor : QueueDescriptorWithParameters<PermuteDescriptor> |
| 157 | { |
| 158 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 159 | }; |
| 160 | |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 161 | // Pooling 2D layer workload data. |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 162 | struct Pooling2dQueueDescriptor : QueueDescriptorWithParameters<Pooling2dDescriptor> |
| 163 | { |
| 164 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 165 | }; |
| 166 | |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 167 | // Convolution 2D layer workload data. |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 168 | struct Convolution2dQueueDescriptor : QueueDescriptorWithParameters<Convolution2dDescriptor> |
| 169 | { |
| 170 | Convolution2dQueueDescriptor() |
| 171 | : m_Weight(nullptr) |
| 172 | , m_Bias(nullptr) |
| 173 | { |
| 174 | } |
| 175 | |
| 176 | const ConstCpuTensorHandle* m_Weight; |
| 177 | const ConstCpuTensorHandle* m_Bias; |
| 178 | |
| 179 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 180 | }; |
| 181 | |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 182 | // Depthwise Convolution 2D layer workload data. |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 183 | struct DepthwiseConvolution2dQueueDescriptor : QueueDescriptorWithParameters<DepthwiseConvolution2dDescriptor> |
| 184 | { |
| 185 | DepthwiseConvolution2dQueueDescriptor() |
| 186 | : m_Weight(nullptr) |
| 187 | , m_Bias(nullptr) |
| 188 | { |
| 189 | } |
| 190 | |
| 191 | const ConstCpuTensorHandle* m_Weight; |
| 192 | const ConstCpuTensorHandle* m_Bias; |
| 193 | |
| 194 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 195 | }; |
| 196 | |
Narumol Prangnawarat | 94dd5d8 | 2019-01-23 18:06:26 +0000 | [diff] [blame] | 197 | struct DetectionPostProcessQueueDescriptor : QueueDescriptorWithParameters<DetectionPostProcessDescriptor> |
| 198 | { |
Narumol Prangnawarat | bc67cef | 2019-01-31 15:31:54 +0000 | [diff] [blame] | 199 | DetectionPostProcessQueueDescriptor() |
| 200 | : m_Anchors(nullptr) |
| 201 | { |
| 202 | } |
| 203 | |
| 204 | const ConstCpuTensorHandle* m_Anchors; |
| 205 | |
Narumol Prangnawarat | 94dd5d8 | 2019-01-23 18:06:26 +0000 | [diff] [blame] | 206 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 207 | }; |
| 208 | |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 209 | // Normalization layer workload data. |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 210 | struct NormalizationQueueDescriptor : QueueDescriptorWithParameters<NormalizationDescriptor> |
| 211 | { |
| 212 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 213 | }; |
| 214 | |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 215 | // Add layer workload data. |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 216 | struct AdditionQueueDescriptor : QueueDescriptor |
| 217 | { |
| 218 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 219 | }; |
| 220 | |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 221 | // Multiplication layer workload data. |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 222 | struct MultiplicationQueueDescriptor : QueueDescriptor |
| 223 | { |
| 224 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 225 | }; |
| 226 | |
Francis Murtagh | e7a86a4 | 2018-08-29 12:42:10 +0100 | [diff] [blame] | 227 | // Division layer workload data. |
| 228 | struct DivisionQueueDescriptor : QueueDescriptor |
| 229 | { |
| 230 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 231 | }; |
| 232 | |
David Beck | c2044fe | 2018-09-05 15:00:38 +0100 | [diff] [blame] | 233 | // Subtraction layer workload data. |
| 234 | struct SubtractionQueueDescriptor : QueueDescriptor |
| 235 | { |
| 236 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 237 | }; |
| 238 | |
Nattapat Chaimanowong | 5a4304a | 2018-11-28 10:44:37 +0000 | [diff] [blame] | 239 | // Maximum layer workload data. |
| 240 | struct MaximumQueueDescriptor : QueueDescriptor |
| 241 | { |
| 242 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 243 | }; |
| 244 | |
narpra01 | a6bf912 | 2018-09-10 09:50:09 +0100 | [diff] [blame] | 245 | // Mean layer workload data. |
narpra01 | 32b9046 | 2018-09-13 11:07:48 +0100 | [diff] [blame] | 246 | struct MeanQueueDescriptor : QueueDescriptorWithParameters<MeanDescriptor> |
narpra01 | a6bf912 | 2018-09-10 09:50:09 +0100 | [diff] [blame] | 247 | { |
| 248 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 249 | }; |
| 250 | |
jimfly01 | 2c9322a | 2018-09-19 10:59:49 +0100 | [diff] [blame] | 251 | // Pad layer workload data |
| 252 | struct PadQueueDescriptor : QueueDescriptorWithParameters<PadDescriptor> |
| 253 | { |
| 254 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 255 | }; |
| 256 | |
Derek Lamberti | a9cca6a | 2019-03-25 15:41:58 +0000 | [diff] [blame] | 257 | struct QuantizeQueueDescriptor : QueueDescriptor |
| 258 | { |
| 259 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 260 | }; |
| 261 | |
FrancisMurtagh | 2099595 | 2018-12-17 12:11:36 +0000 | [diff] [blame] | 262 | // Equal layer workload data |
| 263 | struct EqualQueueDescriptor : QueueDescriptor |
| 264 | { |
| 265 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 266 | }; |
| 267 | |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 268 | // Batch norm layer workload data. |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 269 | struct BatchNormalizationQueueDescriptor : QueueDescriptorWithParameters<BatchNormalizationDescriptor> |
| 270 | { |
| 271 | BatchNormalizationQueueDescriptor() |
| 272 | : m_Mean(nullptr) |
| 273 | , m_Variance(nullptr) |
| 274 | , m_Beta(nullptr) |
| 275 | , m_Gamma(nullptr) |
| 276 | { |
| 277 | } |
| 278 | |
| 279 | const ConstCpuTensorHandle* m_Mean; |
| 280 | const ConstCpuTensorHandle* m_Variance; |
| 281 | const ConstCpuTensorHandle* m_Beta; |
| 282 | const ConstCpuTensorHandle* m_Gamma; |
| 283 | |
| 284 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 285 | }; |
| 286 | |
| 287 | struct ResizeBilinearQueueDescriptor : QueueDescriptorWithParameters<ResizeBilinearDescriptor> |
| 288 | { |
| 289 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 290 | }; |
| 291 | |
Teresa Charlin | a9075df | 2019-06-27 15:41:57 +0100 | [diff] [blame] | 292 | struct ResizeQueueDescriptor : QueueDescriptorWithParameters<ResizeDescriptor> |
| 293 | { |
| 294 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 295 | }; |
| 296 | |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 297 | struct FakeQuantizationQueueDescriptor : QueueDescriptorWithParameters<FakeQuantizationDescriptor> |
| 298 | { |
| 299 | FakeQuantizationQueueDescriptor() |
| 300 | : m_Min(nullptr) |
| 301 | , m_Max(nullptr) |
| 302 | { |
| 303 | } |
| 304 | |
| 305 | const ConstCpuTensorHandle* m_Min; |
| 306 | const ConstCpuTensorHandle* m_Max; |
| 307 | |
| 308 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 309 | }; |
| 310 | |
Kevin May | ce5045a | 2019-10-02 14:07:47 +0100 | [diff] [blame] | 311 | struct InstanceNormalizationQueueDescriptor : QueueDescriptorWithParameters<InstanceNormalizationDescriptor> |
| 312 | { |
Kevin May | ce5045a | 2019-10-02 14:07:47 +0100 | [diff] [blame] | 313 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 314 | }; |
| 315 | |
Matteo Martincigh | bcd3c85 | 2018-09-28 14:14:12 +0100 | [diff] [blame] | 316 | struct L2NormalizationQueueDescriptor : QueueDescriptorWithParameters<L2NormalizationDescriptor> |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 317 | { |
| 318 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 319 | }; |
| 320 | |
Aron Virginas-Tar | f982dea | 2019-10-11 14:07:53 +0100 | [diff] [blame] | 321 | struct LogSoftmaxQueueDescriptor : QueueDescriptorWithParameters<LogSoftmaxDescriptor> |
| 322 | { |
| 323 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 324 | }; |
| 325 | |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 326 | struct ConstantQueueDescriptor : QueueDescriptor |
| 327 | { |
| 328 | ConstantQueueDescriptor() |
| 329 | : m_LayerOutput(nullptr) |
| 330 | { |
| 331 | } |
| 332 | |
| 333 | const ConstCpuTensorHandle* m_LayerOutput; |
| 334 | |
| 335 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 336 | }; |
| 337 | |
| 338 | struct ReshapeQueueDescriptor : QueueDescriptorWithParameters<ReshapeDescriptor> |
| 339 | { |
| 340 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 341 | }; |
| 342 | |
Nattapat Chaimanowong | 207ef9a | 2018-11-02 10:57:25 +0000 | [diff] [blame] | 343 | struct SpaceToBatchNdQueueDescriptor : QueueDescriptorWithParameters<SpaceToBatchNdDescriptor> |
| 344 | { |
| 345 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 346 | }; |
| 347 | |
Aron Virginas-Tar | 972af15 | 2019-06-11 14:14:03 +0100 | [diff] [blame] | 348 | struct SpaceToDepthQueueDescriptor : QueueDescriptorWithParameters<SpaceToDepthDescriptor> |
| 349 | { |
| 350 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 351 | }; |
| 352 | |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 353 | struct FloorQueueDescriptor : QueueDescriptor |
| 354 | { |
| 355 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 356 | }; |
| 357 | |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 358 | struct LstmQueueDescriptor : QueueDescriptorWithParameters<LstmDescriptor> |
| 359 | { |
| 360 | LstmQueueDescriptor() |
| 361 | : m_InputToInputWeights(nullptr) |
| 362 | , m_InputToForgetWeights(nullptr) |
| 363 | , m_InputToCellWeights(nullptr) |
| 364 | , m_InputToOutputWeights(nullptr) |
| 365 | , m_RecurrentToInputWeights(nullptr) |
| 366 | , m_RecurrentToForgetWeights(nullptr) |
| 367 | , m_RecurrentToCellWeights(nullptr) |
| 368 | , m_RecurrentToOutputWeights(nullptr) |
| 369 | , m_CellToInputWeights(nullptr) |
| 370 | , m_CellToForgetWeights(nullptr) |
| 371 | , m_CellToOutputWeights(nullptr) |
| 372 | , m_InputGateBias(nullptr) |
| 373 | , m_ForgetGateBias(nullptr) |
| 374 | , m_CellBias(nullptr) |
| 375 | , m_OutputGateBias(nullptr) |
| 376 | , m_ProjectionWeights(nullptr) |
| 377 | , m_ProjectionBias(nullptr) |
Jan Eilers | 38e05bd | 2019-06-26 13:10:09 +0100 | [diff] [blame] | 378 | , m_InputLayerNormWeights(nullptr) |
| 379 | , m_ForgetLayerNormWeights(nullptr) |
| 380 | , m_CellLayerNormWeights(nullptr) |
| 381 | , m_OutputLayerNormWeights(nullptr) |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 382 | { |
| 383 | } |
| 384 | |
| 385 | const ConstCpuTensorHandle* m_InputToInputWeights; |
| 386 | const ConstCpuTensorHandle* m_InputToForgetWeights; |
| 387 | const ConstCpuTensorHandle* m_InputToCellWeights; |
| 388 | const ConstCpuTensorHandle* m_InputToOutputWeights; |
| 389 | const ConstCpuTensorHandle* m_RecurrentToInputWeights; |
| 390 | const ConstCpuTensorHandle* m_RecurrentToForgetWeights; |
| 391 | const ConstCpuTensorHandle* m_RecurrentToCellWeights; |
| 392 | const ConstCpuTensorHandle* m_RecurrentToOutputWeights; |
| 393 | const ConstCpuTensorHandle* m_CellToInputWeights; |
| 394 | const ConstCpuTensorHandle* m_CellToForgetWeights; |
| 395 | const ConstCpuTensorHandle* m_CellToOutputWeights; |
| 396 | const ConstCpuTensorHandle* m_InputGateBias; |
| 397 | const ConstCpuTensorHandle* m_ForgetGateBias; |
| 398 | const ConstCpuTensorHandle* m_CellBias; |
| 399 | const ConstCpuTensorHandle* m_OutputGateBias; |
| 400 | const ConstCpuTensorHandle* m_ProjectionWeights; |
| 401 | const ConstCpuTensorHandle* m_ProjectionBias; |
Jan Eilers | 38e05bd | 2019-06-26 13:10:09 +0100 | [diff] [blame] | 402 | const ConstCpuTensorHandle* m_InputLayerNormWeights; |
| 403 | const ConstCpuTensorHandle* m_ForgetLayerNormWeights; |
| 404 | const ConstCpuTensorHandle* m_CellLayerNormWeights; |
| 405 | const ConstCpuTensorHandle* m_OutputLayerNormWeights; |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 406 | |
| 407 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 408 | }; |
| 409 | |
| 410 | struct ConvertFp16ToFp32QueueDescriptor : QueueDescriptor |
| 411 | { |
| 412 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 413 | }; |
| 414 | |
| 415 | struct ConvertFp32ToFp16QueueDescriptor : QueueDescriptor |
| 416 | { |
| 417 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 418 | }; |
| 419 | |
Éanna Ó Catháin | 4e1e136 | 2018-11-12 11:36:34 +0000 | [diff] [blame] | 420 | struct BatchToSpaceNdQueueDescriptor : QueueDescriptorWithParameters<BatchToSpaceNdDescriptor> |
| 421 | { |
| 422 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 423 | }; |
Conor Kennedy | 430b5d8 | 2018-11-14 15:28:28 +0000 | [diff] [blame] | 424 | |
| 425 | struct StridedSliceQueueDescriptor : QueueDescriptorWithParameters<StridedSliceDescriptor> |
| 426 | { |
| 427 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 428 | }; |
| 429 | |
Éanna Ó Catháin | 20e5880 | 2018-12-04 10:29:06 +0000 | [diff] [blame] | 430 | // Minimum layer workload data. |
kevmay01 | 9053969 | 2018-11-29 08:40:19 +0000 | [diff] [blame] | 431 | struct MinimumQueueDescriptor : QueueDescriptor |
| 432 | { |
| 433 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 434 | }; |
| 435 | |
Matteo Martincigh | 59a950c | 2018-12-13 12:48:25 +0000 | [diff] [blame] | 436 | struct GreaterQueueDescriptor : QueueDescriptor |
| 437 | { |
| 438 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 439 | }; |
| 440 | |
Nattapat Chaimanowong | 964e955 | 2019-03-26 11:03:26 +0000 | [diff] [blame] | 441 | struct DebugQueueDescriptor : QueueDescriptor |
Nattapat Chaimanowong | a9a1cf1 | 2018-12-03 16:06:49 +0000 | [diff] [blame] | 442 | { |
janeil01 | 3fec1ea | 2019-11-07 09:47:20 +0000 | [diff] [blame] | 443 | DebugQueueDescriptor() : m_Guid(0) {} |
| 444 | |
Nattapat Chaimanowong | a9a1cf1 | 2018-12-03 16:06:49 +0000 | [diff] [blame] | 445 | void Validate(const WorkloadInfo& workloadInfo) const; |
Nattapat Chaimanowong | 964e955 | 2019-03-26 11:03:26 +0000 | [diff] [blame] | 446 | |
| 447 | LayerGuid m_Guid; |
| 448 | std::string m_LayerName; |
| 449 | unsigned int m_SlotIndex; |
Nattapat Chaimanowong | a9a1cf1 | 2018-12-03 16:06:49 +0000 | [diff] [blame] | 450 | }; |
| 451 | |
Mohamed Nour Abouelseoud | a1d3c6a | 2018-12-27 12:39:16 +0000 | [diff] [blame] | 452 | struct RsqrtQueueDescriptor : QueueDescriptor |
| 453 | { |
| 454 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 455 | }; |
| 456 | |
narpra01 | b89b05f | 2019-01-16 09:53:09 +0000 | [diff] [blame] | 457 | struct GatherQueueDescriptor : QueueDescriptor |
| 458 | { |
| 459 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 460 | }; |
| 461 | |
Matteo Martincigh | 4912402 | 2019-01-11 13:25:59 +0000 | [diff] [blame] | 462 | struct PreCompiledQueueDescriptor : QueueDescriptorWithParameters<PreCompiledDescriptor> |
| 463 | { |
| 464 | PreCompiledQueueDescriptor() |
| 465 | : m_PreCompiledObject(nullptr) |
| 466 | { |
| 467 | } |
| 468 | |
Matteo Martincigh | 7997a35 | 2019-04-17 15:37:30 +0100 | [diff] [blame] | 469 | void* m_PreCompiledObject; |
Matteo Martincigh | 4912402 | 2019-01-11 13:25:59 +0000 | [diff] [blame] | 470 | |
| 471 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 472 | }; |
| 473 | |
Nattapat Chaimanowong | e4294fd | 2019-03-28 09:56:53 +0000 | [diff] [blame] | 474 | struct DequantizeQueueDescriptor : QueueDescriptor |
| 475 | { |
| 476 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 477 | }; |
| 478 | |
Nattapat Chaimanowong | 1f88630 | 2019-04-05 13:37:19 +0100 | [diff] [blame] | 479 | struct MergeQueueDescriptor : QueueDescriptor |
| 480 | { |
| 481 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 482 | }; |
| 483 | |
Sadik Armagan | eff363d | 2019-04-05 15:25:46 +0100 | [diff] [blame] | 484 | struct SwitchQueueDescriptor : QueueDescriptor |
| 485 | { |
| 486 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 487 | }; |
| 488 | |
Matteo Martincigh | 0e406ee | 2019-06-12 15:42:18 +0100 | [diff] [blame] | 489 | struct PreluQueueDescriptor : QueueDescriptor |
| 490 | { |
| 491 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 492 | }; |
| 493 | |
Aron Virginas-Tar | 639fb04 | 2019-06-20 14:28:19 +0100 | [diff] [blame] | 494 | struct TransposeConvolution2dQueueDescriptor : QueueDescriptorWithParameters<TransposeConvolution2dDescriptor> |
| 495 | { |
| 496 | TransposeConvolution2dQueueDescriptor() : |
| 497 | m_Weight(nullptr), |
| 498 | m_Bias(nullptr) |
| 499 | {} |
| 500 | |
| 501 | const ConstCpuTensorHandle* m_Weight; |
| 502 | const ConstCpuTensorHandle* m_Bias; |
| 503 | |
| 504 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 505 | }; |
| 506 | |
Mike Kelly | c9ea45a | 2020-02-28 18:11:58 +0000 | [diff] [blame] | 507 | struct TransposeQueueDescriptor : QueueDescriptorWithParameters<TransposeDescriptor> |
| 508 | { |
| 509 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 510 | }; |
| 511 | |
James Conroy | ee18dc8 | 2019-07-17 11:27:46 +0100 | [diff] [blame] | 512 | struct QuantizedLstmQueueDescriptor : QueueDescriptor |
| 513 | { |
| 514 | QuantizedLstmQueueDescriptor() |
| 515 | : m_InputToInputWeights(nullptr) |
| 516 | , m_InputToForgetWeights(nullptr) |
| 517 | , m_InputToCellWeights(nullptr) |
| 518 | , m_InputToOutputWeights(nullptr) |
| 519 | |
| 520 | , m_RecurrentToInputWeights(nullptr) |
| 521 | , m_RecurrentToForgetWeights(nullptr) |
| 522 | , m_RecurrentToCellWeights(nullptr) |
| 523 | , m_RecurrentToOutputWeights(nullptr) |
| 524 | |
| 525 | , m_InputGateBias(nullptr) |
| 526 | , m_ForgetGateBias(nullptr) |
| 527 | , m_CellBias(nullptr) |
| 528 | , m_OutputGateBias(nullptr) |
| 529 | {} |
| 530 | |
| 531 | const ConstCpuTensorHandle* m_InputToInputWeights; |
| 532 | const ConstCpuTensorHandle* m_InputToForgetWeights; |
| 533 | const ConstCpuTensorHandle* m_InputToCellWeights; |
| 534 | const ConstCpuTensorHandle* m_InputToOutputWeights; |
| 535 | |
| 536 | const ConstCpuTensorHandle* m_RecurrentToInputWeights; |
| 537 | const ConstCpuTensorHandle* m_RecurrentToForgetWeights; |
| 538 | const ConstCpuTensorHandle* m_RecurrentToCellWeights; |
| 539 | const ConstCpuTensorHandle* m_RecurrentToOutputWeights; |
| 540 | |
| 541 | const ConstCpuTensorHandle* m_InputGateBias; |
| 542 | const ConstCpuTensorHandle* m_ForgetGateBias; |
| 543 | const ConstCpuTensorHandle* m_CellBias; |
| 544 | const ConstCpuTensorHandle* m_OutputGateBias; |
| 545 | |
| 546 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 547 | }; |
| 548 | |
Kevin May | 868eb14 | 2019-09-04 17:29:31 +0100 | [diff] [blame] | 549 | struct AbsQueueDescriptor : QueueDescriptor |
| 550 | { |
| 551 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 552 | }; |
| 553 | |
Aron Virginas-Tar | 636ab40 | 2019-09-16 14:27:45 +0100 | [diff] [blame] | 554 | struct SliceQueueDescriptor : QueueDescriptorWithParameters<SliceDescriptor> |
| 555 | { |
| 556 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 557 | }; |
| 558 | |
Aron Virginas-Tar | dd6247f | 2019-09-19 14:31:17 +0100 | [diff] [blame] | 559 | struct DepthToSpaceQueueDescriptor : QueueDescriptorWithParameters<DepthToSpaceDescriptor> |
| 560 | { |
| 561 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 562 | }; |
| 563 | |
Aron Virginas-Tar | 77bfb5e | 2019-10-16 17:45:38 +0100 | [diff] [blame] | 564 | struct ComparisonQueueDescriptor : QueueDescriptorWithParameters<ComparisonDescriptor> |
| 565 | { |
| 566 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 567 | }; |
| 568 | |
josh minor | 4a3c610 | 2020-01-06 16:40:46 -0600 | [diff] [blame] | 569 | struct ElementwiseUnaryQueueDescriptor : QueueDescriptorWithParameters<ElementwiseUnaryDescriptor> |
| 570 | { |
| 571 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 572 | }; |
| 573 | |
Aron Virginas-Tar | 636ab40 | 2019-09-16 14:27:45 +0100 | [diff] [blame] | 574 | } // namespace armnn |