| telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 1 | // |
| 2 | // Copyright © 2017 Arm Ltd. All rights reserved. |
| David Beck | ecb56cd | 2018-09-05 12:52:57 +0100 | [diff] [blame] | 3 | // SPDX-License-Identifier: MIT |
| telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 4 | // |
| 5 | #pragma once |
| 6 | |
| 7 | #include <armnn/Tensor.hpp> |
| telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 8 | |
| Aron Virginas-Tar | 5caf907 | 2018-11-14 18:35:18 +0000 | [diff] [blame^] | 9 | #include <backendsCommon/IBackendInternal.hpp> |
| 10 | #include <backendsCommon/IMemoryManager.hpp> |
| 11 | #include <backendsCommon/Workload.hpp> |
| Aron Virginas-Tar | c9cc804 | 2018-11-01 16:15:57 +0000 | [diff] [blame] | 12 | #include <backendsCommon/WorkloadInfo.hpp> |
| 13 | |
| telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 14 | namespace armnn |
| 15 | { |
| 16 | class ITensorHandle; |
| Aron Virginas-Tar | 5caf907 | 2018-11-14 18:35:18 +0000 | [diff] [blame^] | 17 | } // namespace armnn |
| 18 | |
| 19 | namespace |
| 20 | { |
| telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 21 | |
| 22 | template <typename QueueDescriptor> |
| 23 | void AddInputToWorkload(QueueDescriptor& descriptor, |
| 24 | armnn::WorkloadInfo& info, |
| 25 | const armnn::TensorInfo& tensorInfo, |
| 26 | armnn::ITensorHandle* tensorHandle) |
| 27 | { |
| 28 | descriptor.m_Inputs.push_back(tensorHandle); |
| 29 | info.m_InputTensorInfos.push_back(tensorInfo); |
| 30 | } |
| 31 | |
| 32 | template <typename QueueDescriptor> |
| 33 | void AddOutputToWorkload(QueueDescriptor& descriptor, |
| 34 | armnn::WorkloadInfo& info, |
| 35 | const armnn::TensorInfo& tensorInfo, |
| 36 | armnn::ITensorHandle* tensorHandle) |
| 37 | { |
| 38 | descriptor.m_Outputs.push_back(tensorHandle); |
| 39 | info.m_OutputTensorInfos.push_back(tensorInfo); |
| 40 | } |
| 41 | |
| 42 | template <typename QueueDescriptor> |
| 43 | void SetWorkloadInput(QueueDescriptor& descriptor, |
| 44 | armnn::WorkloadInfo& info, |
| 45 | unsigned int index, |
| 46 | const armnn::TensorInfo& tensorInfo, |
| 47 | armnn::ITensorHandle* tensorHandle) |
| 48 | { |
| 49 | descriptor.m_Inputs[index] = tensorHandle; |
| 50 | info.m_InputTensorInfos[index] = tensorInfo; |
| 51 | } |
| 52 | |
| 53 | template <typename QueueDescriptor> |
| 54 | void SetWorkloadOutput(QueueDescriptor& descriptor, |
| 55 | armnn::WorkloadInfo& info, |
| 56 | unsigned int index, |
| 57 | const armnn::TensorInfo& tensorInfo, |
| 58 | armnn::ITensorHandle* tensorHandle) |
| 59 | { |
| 60 | descriptor.m_Outputs[index] = tensorHandle; |
| 61 | info.m_OutputTensorInfos[index] = tensorInfo; |
| Aron Virginas-Tar | 5caf907 | 2018-11-14 18:35:18 +0000 | [diff] [blame^] | 62 | } |
| 63 | |
| 64 | inline void ExecuteWorkload(armnn::IWorkload& workload, |
| 65 | const armnn::IBackendInternal::IMemoryManagerSharedPtr& memoryManager, |
| 66 | bool memoryManagementRequested = true) |
| 67 | { |
| 68 | const bool manageMemory = memoryManager && memoryManagementRequested; |
| 69 | |
| 70 | // Acquire working memory (if needed) |
| 71 | if (manageMemory) |
| 72 | { |
| 73 | memoryManager->Acquire(); |
| 74 | } |
| 75 | |
| 76 | // Execute the workload |
| 77 | workload.Execute(); |
| 78 | |
| 79 | // Release working memory (if needed) |
| 80 | if (manageMemory) |
| 81 | { |
| 82 | memoryManager->Release(); |
| 83 | } |
| 84 | } |
| 85 | |
| 86 | } // anonymous namespace |