telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 1 | // |
| 2 | // Copyright © 2017 Arm Ltd. All rights reserved. |
David Beck | ecb56cd | 2018-09-05 12:52:57 +0100 | [diff] [blame] | 3 | // SPDX-License-Identifier: MIT |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 4 | // |
| 5 | #pragma once |
| 6 | |
Aron Virginas-Tar | c9cc804 | 2018-11-01 16:15:57 +0000 | [diff] [blame] | 7 | #include "CpuTensorHandleFwd.hpp" |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 8 | #include "WorkloadDataFwd.hpp" |
| 9 | |
Aron Virginas-Tar | c9cc804 | 2018-11-01 16:15:57 +0000 | [diff] [blame] | 10 | #include <InternalTypes.hpp> |
| 11 | |
Jim Flynn | e242f2d | 2019-05-22 14:24:13 +0100 | [diff] [blame] | 12 | #include <armnn/Deprecated.hpp> |
David Beck | 0dbe0ee | 2018-09-24 15:59:27 +0100 | [diff] [blame] | 13 | #include <armnn/Descriptors.hpp> |
| 14 | #include <armnn/Exceptions.hpp> |
Aron Virginas-Tar | c9cc804 | 2018-11-01 16:15:57 +0000 | [diff] [blame] | 15 | #include <armnn/Types.hpp> |
| 16 | #include <armnn/Tensor.hpp> |
David Beck | 0dbe0ee | 2018-09-24 15:59:27 +0100 | [diff] [blame] | 17 | |
Aron Virginas-Tar | c9cc804 | 2018-11-01 16:15:57 +0000 | [diff] [blame] | 18 | #include <backendsCommon/OutputHandler.hpp> |
| 19 | #include <backendsCommon/WorkloadInfo.hpp> |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 20 | |
| 21 | namespace armnn |
| 22 | { |
| 23 | |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 24 | //A helper function that returns the bias data type required for given input data type. |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 25 | DataType GetBiasDataType(DataType inputDataType); |
| 26 | |
| 27 | struct WorkloadInfo; |
| 28 | |
| 29 | struct QueueDescriptor |
| 30 | { |
| 31 | std::vector<ITensorHandle*> m_Inputs; |
| 32 | std::vector<ITensorHandle*> m_Outputs; |
| 33 | |
| 34 | void ValidateInputsOutputs(const std::string& descName, |
| 35 | unsigned int numExpectedIn, unsigned int numExpectedOut) const; |
| 36 | |
| 37 | |
| 38 | protected: |
| 39 | ~QueueDescriptor() = default; |
| 40 | QueueDescriptor() = default; |
| 41 | QueueDescriptor(QueueDescriptor const&) = default; |
| 42 | QueueDescriptor& operator=(QueueDescriptor const&) = default; |
| 43 | }; |
| 44 | |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 45 | // Base class for queue descriptors which contain parameters. |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 46 | template <typename LayerDescriptor> |
| 47 | struct QueueDescriptorWithParameters : public QueueDescriptor |
| 48 | { |
| 49 | LayerDescriptor m_Parameters; |
| 50 | |
| 51 | protected: |
| 52 | ~QueueDescriptorWithParameters() = default; |
| 53 | QueueDescriptorWithParameters() = default; |
| 54 | QueueDescriptorWithParameters(QueueDescriptorWithParameters const&) = default; |
| 55 | QueueDescriptorWithParameters& operator=(QueueDescriptorWithParameters const&) = default; |
| 56 | }; |
| 57 | |
| 58 | struct MemCopyQueueDescriptor : QueueDescriptor |
| 59 | { |
| 60 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 61 | }; |
| 62 | |
| 63 | using InputQueueDescriptor = MemCopyQueueDescriptor; |
| 64 | using OutputQueueDescriptor = MemCopyQueueDescriptor; |
| 65 | |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 66 | // Softmax layer workload data. |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 67 | struct SoftmaxQueueDescriptor : QueueDescriptorWithParameters<SoftmaxDescriptor> |
| 68 | { |
| 69 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 70 | }; |
| 71 | |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 72 | // Splitter layer workload data. |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 73 | struct SplitterQueueDescriptor : QueueDescriptorWithParameters<ViewsDescriptor> |
| 74 | { |
| 75 | struct ViewOrigin |
| 76 | { |
| 77 | ViewOrigin() {} |
| 78 | ViewOrigin(std::vector<unsigned int> const& origin) : m_Origin(origin) {} |
| 79 | |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 80 | //View origin (size of the vector is the same as number of dimensions of the view). |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 81 | std::vector<unsigned int> m_Origin; |
| 82 | }; |
| 83 | |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 84 | //View defines a tensor that will be carved from the input tensor. |
| 85 | //View origins are stored here, the extents are defined by sizes of the output tensors. |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 86 | std::vector<ViewOrigin> m_ViewOrigins; |
| 87 | |
| 88 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 89 | }; |
| 90 | |
Jim Flynn | e242f2d | 2019-05-22 14:24:13 +0100 | [diff] [blame] | 91 | // Concat layer workload data. |
| 92 | struct ConcatQueueDescriptor : QueueDescriptorWithParameters<OriginsDescriptor> |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 93 | { |
| 94 | struct ViewOrigin |
| 95 | { |
| 96 | ViewOrigin() {} |
| 97 | ViewOrigin(const std::vector<unsigned int>& origin) : m_Origin(origin) {} |
| 98 | |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 99 | //View origin (size of the vector is the same as number of dimensions of the view). |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 100 | std::vector<unsigned int> m_Origin; |
| 101 | }; |
| 102 | |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 103 | //View defines a sub-area of the output tensor that will be filled with the corresponding input tensor. |
| 104 | //View origins are stored here, the extents are defined by sizes of the input tensors. |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 105 | std::vector<ViewOrigin> m_ViewOrigins; |
| 106 | |
| 107 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 108 | }; |
| 109 | |
Jim Flynn | e242f2d | 2019-05-22 14:24:13 +0100 | [diff] [blame] | 110 | // Deprecated. Use ConcatQueueDescriptor instead |
| 111 | using MergerQueueDescriptor = ConcatQueueDescriptor; |
| 112 | |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 113 | // Activation layer workload data. |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 114 | struct ActivationQueueDescriptor : QueueDescriptorWithParameters<ActivationDescriptor> |
| 115 | { |
| 116 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 117 | }; |
| 118 | |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 119 | // Fully connected layer workload data. |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 120 | struct FullyConnectedQueueDescriptor : QueueDescriptorWithParameters<FullyConnectedDescriptor> |
| 121 | { |
| 122 | FullyConnectedQueueDescriptor() |
| 123 | : m_Weight(nullptr) |
| 124 | , m_Bias(nullptr) |
| 125 | { |
| 126 | } |
| 127 | |
| 128 | const ConstCpuTensorHandle* m_Weight; |
| 129 | const ConstCpuTensorHandle* m_Bias; |
| 130 | |
| 131 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 132 | }; |
| 133 | |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 134 | // Permute layer workload data. |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 135 | struct PermuteQueueDescriptor : QueueDescriptorWithParameters<PermuteDescriptor> |
| 136 | { |
| 137 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 138 | }; |
| 139 | |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 140 | // Pooling 2D layer workload data. |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 141 | struct Pooling2dQueueDescriptor : QueueDescriptorWithParameters<Pooling2dDescriptor> |
| 142 | { |
| 143 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 144 | }; |
| 145 | |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 146 | // Convolution 2D layer workload data. |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 147 | struct Convolution2dQueueDescriptor : QueueDescriptorWithParameters<Convolution2dDescriptor> |
| 148 | { |
| 149 | Convolution2dQueueDescriptor() |
| 150 | : m_Weight(nullptr) |
| 151 | , m_Bias(nullptr) |
| 152 | { |
| 153 | } |
| 154 | |
| 155 | const ConstCpuTensorHandle* m_Weight; |
| 156 | const ConstCpuTensorHandle* m_Bias; |
| 157 | |
| 158 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 159 | }; |
| 160 | |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 161 | // Depthwise Convolution 2D layer workload data. |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 162 | struct DepthwiseConvolution2dQueueDescriptor : QueueDescriptorWithParameters<DepthwiseConvolution2dDescriptor> |
| 163 | { |
| 164 | DepthwiseConvolution2dQueueDescriptor() |
| 165 | : m_Weight(nullptr) |
| 166 | , m_Bias(nullptr) |
| 167 | { |
| 168 | } |
| 169 | |
| 170 | const ConstCpuTensorHandle* m_Weight; |
| 171 | const ConstCpuTensorHandle* m_Bias; |
| 172 | |
| 173 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 174 | }; |
| 175 | |
Narumol Prangnawarat | 94dd5d8 | 2019-01-23 18:06:26 +0000 | [diff] [blame] | 176 | struct DetectionPostProcessQueueDescriptor : QueueDescriptorWithParameters<DetectionPostProcessDescriptor> |
| 177 | { |
Narumol Prangnawarat | bc67cef | 2019-01-31 15:31:54 +0000 | [diff] [blame] | 178 | DetectionPostProcessQueueDescriptor() |
| 179 | : m_Anchors(nullptr) |
| 180 | { |
| 181 | } |
| 182 | |
| 183 | const ConstCpuTensorHandle* m_Anchors; |
| 184 | |
Narumol Prangnawarat | 94dd5d8 | 2019-01-23 18:06:26 +0000 | [diff] [blame] | 185 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 186 | }; |
| 187 | |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 188 | // Normalization layer workload data. |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 189 | struct NormalizationQueueDescriptor : QueueDescriptorWithParameters<NormalizationDescriptor> |
| 190 | { |
| 191 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 192 | }; |
| 193 | |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 194 | // Add layer workload data. |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 195 | struct AdditionQueueDescriptor : QueueDescriptor |
| 196 | { |
| 197 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 198 | }; |
| 199 | |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 200 | // Multiplication layer workload data. |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 201 | struct MultiplicationQueueDescriptor : QueueDescriptor |
| 202 | { |
| 203 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 204 | }; |
| 205 | |
Francis Murtagh | e7a86a4 | 2018-08-29 12:42:10 +0100 | [diff] [blame] | 206 | // Division layer workload data. |
| 207 | struct DivisionQueueDescriptor : QueueDescriptor |
| 208 | { |
| 209 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 210 | }; |
| 211 | |
David Beck | c2044fe | 2018-09-05 15:00:38 +0100 | [diff] [blame] | 212 | // Subtraction layer workload data. |
| 213 | struct SubtractionQueueDescriptor : QueueDescriptor |
| 214 | { |
| 215 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 216 | }; |
| 217 | |
Nattapat Chaimanowong | 5a4304a | 2018-11-28 10:44:37 +0000 | [diff] [blame] | 218 | // Maximum layer workload data. |
| 219 | struct MaximumQueueDescriptor : QueueDescriptor |
| 220 | { |
| 221 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 222 | }; |
| 223 | |
narpra01 | a6bf912 | 2018-09-10 09:50:09 +0100 | [diff] [blame] | 224 | // Mean layer workload data. |
narpra01 | 32b9046 | 2018-09-13 11:07:48 +0100 | [diff] [blame] | 225 | struct MeanQueueDescriptor : QueueDescriptorWithParameters<MeanDescriptor> |
narpra01 | a6bf912 | 2018-09-10 09:50:09 +0100 | [diff] [blame] | 226 | { |
| 227 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 228 | }; |
| 229 | |
jimfly01 | 2c9322a | 2018-09-19 10:59:49 +0100 | [diff] [blame] | 230 | // Pad layer workload data |
| 231 | struct PadQueueDescriptor : QueueDescriptorWithParameters<PadDescriptor> |
| 232 | { |
| 233 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 234 | }; |
| 235 | |
Derek Lamberti | a9cca6a | 2019-03-25 15:41:58 +0000 | [diff] [blame] | 236 | struct QuantizeQueueDescriptor : QueueDescriptor |
| 237 | { |
| 238 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 239 | }; |
| 240 | |
FrancisMurtagh | 2099595 | 2018-12-17 12:11:36 +0000 | [diff] [blame] | 241 | // Equal layer workload data |
| 242 | struct EqualQueueDescriptor : QueueDescriptor |
| 243 | { |
| 244 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 245 | }; |
| 246 | |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 247 | // Batch norm layer workload data. |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 248 | struct BatchNormalizationQueueDescriptor : QueueDescriptorWithParameters<BatchNormalizationDescriptor> |
| 249 | { |
| 250 | BatchNormalizationQueueDescriptor() |
| 251 | : m_Mean(nullptr) |
| 252 | , m_Variance(nullptr) |
| 253 | , m_Beta(nullptr) |
| 254 | , m_Gamma(nullptr) |
| 255 | { |
| 256 | } |
| 257 | |
| 258 | const ConstCpuTensorHandle* m_Mean; |
| 259 | const ConstCpuTensorHandle* m_Variance; |
| 260 | const ConstCpuTensorHandle* m_Beta; |
| 261 | const ConstCpuTensorHandle* m_Gamma; |
| 262 | |
| 263 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 264 | }; |
| 265 | |
| 266 | struct ResizeBilinearQueueDescriptor : QueueDescriptorWithParameters<ResizeBilinearDescriptor> |
| 267 | { |
| 268 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 269 | }; |
| 270 | |
Teresa Charlin | a9075df | 2019-06-27 15:41:57 +0100 | [diff] [blame] | 271 | struct ResizeQueueDescriptor : QueueDescriptorWithParameters<ResizeDescriptor> |
| 272 | { |
| 273 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 274 | }; |
| 275 | |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 276 | struct FakeQuantizationQueueDescriptor : QueueDescriptorWithParameters<FakeQuantizationDescriptor> |
| 277 | { |
| 278 | FakeQuantizationQueueDescriptor() |
| 279 | : m_Min(nullptr) |
| 280 | , m_Max(nullptr) |
| 281 | { |
| 282 | } |
| 283 | |
| 284 | const ConstCpuTensorHandle* m_Min; |
| 285 | const ConstCpuTensorHandle* m_Max; |
| 286 | |
| 287 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 288 | }; |
| 289 | |
Matteo Martincigh | bcd3c85 | 2018-09-28 14:14:12 +0100 | [diff] [blame] | 290 | struct L2NormalizationQueueDescriptor : QueueDescriptorWithParameters<L2NormalizationDescriptor> |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 291 | { |
| 292 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 293 | }; |
| 294 | |
| 295 | struct ConstantQueueDescriptor : QueueDescriptor |
| 296 | { |
| 297 | ConstantQueueDescriptor() |
| 298 | : m_LayerOutput(nullptr) |
| 299 | { |
| 300 | } |
| 301 | |
| 302 | const ConstCpuTensorHandle* m_LayerOutput; |
| 303 | |
| 304 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 305 | }; |
| 306 | |
| 307 | struct ReshapeQueueDescriptor : QueueDescriptorWithParameters<ReshapeDescriptor> |
| 308 | { |
| 309 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 310 | }; |
| 311 | |
Nattapat Chaimanowong | 207ef9a | 2018-11-02 10:57:25 +0000 | [diff] [blame] | 312 | struct SpaceToBatchNdQueueDescriptor : QueueDescriptorWithParameters<SpaceToBatchNdDescriptor> |
| 313 | { |
| 314 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 315 | }; |
| 316 | |
Aron Virginas-Tar | 972af15 | 2019-06-11 14:14:03 +0100 | [diff] [blame] | 317 | struct SpaceToDepthQueueDescriptor : QueueDescriptorWithParameters<SpaceToDepthDescriptor> |
| 318 | { |
| 319 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 320 | }; |
| 321 | |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 322 | struct FloorQueueDescriptor : QueueDescriptor |
| 323 | { |
| 324 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 325 | }; |
| 326 | |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 327 | struct LstmQueueDescriptor : QueueDescriptorWithParameters<LstmDescriptor> |
| 328 | { |
| 329 | LstmQueueDescriptor() |
| 330 | : m_InputToInputWeights(nullptr) |
| 331 | , m_InputToForgetWeights(nullptr) |
| 332 | , m_InputToCellWeights(nullptr) |
| 333 | , m_InputToOutputWeights(nullptr) |
| 334 | , m_RecurrentToInputWeights(nullptr) |
| 335 | , m_RecurrentToForgetWeights(nullptr) |
| 336 | , m_RecurrentToCellWeights(nullptr) |
| 337 | , m_RecurrentToOutputWeights(nullptr) |
| 338 | , m_CellToInputWeights(nullptr) |
| 339 | , m_CellToForgetWeights(nullptr) |
| 340 | , m_CellToOutputWeights(nullptr) |
| 341 | , m_InputGateBias(nullptr) |
| 342 | , m_ForgetGateBias(nullptr) |
| 343 | , m_CellBias(nullptr) |
| 344 | , m_OutputGateBias(nullptr) |
| 345 | , m_ProjectionWeights(nullptr) |
| 346 | , m_ProjectionBias(nullptr) |
Jan Eilers | 38e05bd | 2019-06-26 13:10:09 +0100 | [diff] [blame] | 347 | , m_InputLayerNormWeights(nullptr) |
| 348 | , m_ForgetLayerNormWeights(nullptr) |
| 349 | , m_CellLayerNormWeights(nullptr) |
| 350 | , m_OutputLayerNormWeights(nullptr) |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 351 | { |
| 352 | } |
| 353 | |
| 354 | const ConstCpuTensorHandle* m_InputToInputWeights; |
| 355 | const ConstCpuTensorHandle* m_InputToForgetWeights; |
| 356 | const ConstCpuTensorHandle* m_InputToCellWeights; |
| 357 | const ConstCpuTensorHandle* m_InputToOutputWeights; |
| 358 | const ConstCpuTensorHandle* m_RecurrentToInputWeights; |
| 359 | const ConstCpuTensorHandle* m_RecurrentToForgetWeights; |
| 360 | const ConstCpuTensorHandle* m_RecurrentToCellWeights; |
| 361 | const ConstCpuTensorHandle* m_RecurrentToOutputWeights; |
| 362 | const ConstCpuTensorHandle* m_CellToInputWeights; |
| 363 | const ConstCpuTensorHandle* m_CellToForgetWeights; |
| 364 | const ConstCpuTensorHandle* m_CellToOutputWeights; |
| 365 | const ConstCpuTensorHandle* m_InputGateBias; |
| 366 | const ConstCpuTensorHandle* m_ForgetGateBias; |
| 367 | const ConstCpuTensorHandle* m_CellBias; |
| 368 | const ConstCpuTensorHandle* m_OutputGateBias; |
| 369 | const ConstCpuTensorHandle* m_ProjectionWeights; |
| 370 | const ConstCpuTensorHandle* m_ProjectionBias; |
Jan Eilers | 38e05bd | 2019-06-26 13:10:09 +0100 | [diff] [blame] | 371 | const ConstCpuTensorHandle* m_InputLayerNormWeights; |
| 372 | const ConstCpuTensorHandle* m_ForgetLayerNormWeights; |
| 373 | const ConstCpuTensorHandle* m_CellLayerNormWeights; |
| 374 | const ConstCpuTensorHandle* m_OutputLayerNormWeights; |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 375 | |
| 376 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 377 | }; |
| 378 | |
| 379 | struct ConvertFp16ToFp32QueueDescriptor : QueueDescriptor |
| 380 | { |
| 381 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 382 | }; |
| 383 | |
| 384 | struct ConvertFp32ToFp16QueueDescriptor : QueueDescriptor |
| 385 | { |
| 386 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 387 | }; |
| 388 | |
Éanna Ó Catháin | 4e1e136 | 2018-11-12 11:36:34 +0000 | [diff] [blame] | 389 | struct BatchToSpaceNdQueueDescriptor : QueueDescriptorWithParameters<BatchToSpaceNdDescriptor> |
| 390 | { |
| 391 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 392 | }; |
Conor Kennedy | 430b5d8 | 2018-11-14 15:28:28 +0000 | [diff] [blame] | 393 | |
| 394 | struct StridedSliceQueueDescriptor : QueueDescriptorWithParameters<StridedSliceDescriptor> |
| 395 | { |
| 396 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 397 | }; |
| 398 | |
Éanna Ó Catháin | 20e5880 | 2018-12-04 10:29:06 +0000 | [diff] [blame] | 399 | // Minimum layer workload data. |
kevmay01 | 9053969 | 2018-11-29 08:40:19 +0000 | [diff] [blame] | 400 | struct MinimumQueueDescriptor : QueueDescriptor |
| 401 | { |
| 402 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 403 | }; |
| 404 | |
Matteo Martincigh | 59a950c | 2018-12-13 12:48:25 +0000 | [diff] [blame] | 405 | struct GreaterQueueDescriptor : QueueDescriptor |
| 406 | { |
| 407 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 408 | }; |
| 409 | |
Nattapat Chaimanowong | 964e955 | 2019-03-26 11:03:26 +0000 | [diff] [blame] | 410 | struct DebugQueueDescriptor : QueueDescriptor |
Nattapat Chaimanowong | a9a1cf1 | 2018-12-03 16:06:49 +0000 | [diff] [blame] | 411 | { |
| 412 | void Validate(const WorkloadInfo& workloadInfo) const; |
Nattapat Chaimanowong | 964e955 | 2019-03-26 11:03:26 +0000 | [diff] [blame] | 413 | |
| 414 | LayerGuid m_Guid; |
| 415 | std::string m_LayerName; |
| 416 | unsigned int m_SlotIndex; |
Nattapat Chaimanowong | a9a1cf1 | 2018-12-03 16:06:49 +0000 | [diff] [blame] | 417 | }; |
| 418 | |
Mohamed Nour Abouelseoud | a1d3c6a | 2018-12-27 12:39:16 +0000 | [diff] [blame] | 419 | struct RsqrtQueueDescriptor : QueueDescriptor |
| 420 | { |
| 421 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 422 | }; |
| 423 | |
narpra01 | b89b05f | 2019-01-16 09:53:09 +0000 | [diff] [blame] | 424 | struct GatherQueueDescriptor : QueueDescriptor |
| 425 | { |
| 426 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 427 | }; |
| 428 | |
Matteo Martincigh | 4912402 | 2019-01-11 13:25:59 +0000 | [diff] [blame] | 429 | struct PreCompiledQueueDescriptor : QueueDescriptorWithParameters<PreCompiledDescriptor> |
| 430 | { |
| 431 | PreCompiledQueueDescriptor() |
| 432 | : m_PreCompiledObject(nullptr) |
| 433 | { |
| 434 | } |
| 435 | |
Matteo Martincigh | 7997a35 | 2019-04-17 15:37:30 +0100 | [diff] [blame] | 436 | void* m_PreCompiledObject; |
Matteo Martincigh | 4912402 | 2019-01-11 13:25:59 +0000 | [diff] [blame] | 437 | |
| 438 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 439 | }; |
| 440 | |
Nattapat Chaimanowong | e4294fd | 2019-03-28 09:56:53 +0000 | [diff] [blame] | 441 | struct DequantizeQueueDescriptor : QueueDescriptor |
| 442 | { |
| 443 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 444 | }; |
| 445 | |
Nattapat Chaimanowong | 1f88630 | 2019-04-05 13:37:19 +0100 | [diff] [blame] | 446 | struct MergeQueueDescriptor : QueueDescriptor |
| 447 | { |
| 448 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 449 | }; |
| 450 | |
Sadik Armagan | eff363d | 2019-04-05 15:25:46 +0100 | [diff] [blame] | 451 | struct SwitchQueueDescriptor : QueueDescriptor |
| 452 | { |
| 453 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 454 | }; |
| 455 | |
Matteo Martincigh | 0e406ee | 2019-06-12 15:42:18 +0100 | [diff] [blame] | 456 | struct PreluQueueDescriptor : QueueDescriptor |
| 457 | { |
| 458 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 459 | }; |
| 460 | |
Aron Virginas-Tar | 639fb04 | 2019-06-20 14:28:19 +0100 | [diff] [blame] | 461 | struct TransposeConvolution2dQueueDescriptor : QueueDescriptorWithParameters<TransposeConvolution2dDescriptor> |
| 462 | { |
| 463 | TransposeConvolution2dQueueDescriptor() : |
| 464 | m_Weight(nullptr), |
| 465 | m_Bias(nullptr) |
| 466 | {} |
| 467 | |
| 468 | const ConstCpuTensorHandle* m_Weight; |
| 469 | const ConstCpuTensorHandle* m_Bias; |
| 470 | |
| 471 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 472 | }; |
| 473 | |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 474 | } //namespace armnn |