| Sadik Armagan | f446432 | 2018-12-20 16:19:12 +0000 | [diff] [blame] | 1 | // |
| 2 | // Copyright © 2017 Arm Ltd. All rights reserved. |
| 3 | // SPDX-License-Identifier: MIT |
| 4 | // |
| 5 | |
| 6 | #include "ClSpaceToBatchNdWorkload.hpp" |
| 7 | |
| 8 | #include "ClWorkloadUtils.hpp" |
| 9 | |
| 10 | #include <aclCommon/ArmComputeUtils.hpp> |
| 11 | #include <aclCommon/ArmComputeTensorUtils.hpp> |
| 12 | #include <backendsCommon/CpuTensorHandle.hpp> |
| 13 | #include <cl/ClLayerSupport.hpp> |
| 14 | #include <cl/ClTensorHandle.hpp> |
| 15 | #include <cl/ClLayerSupport.hpp> |
| 16 | |
| 17 | #include <boost/polymorphic_pointer_cast.hpp> |
| 18 | |
| 19 | namespace armnn |
| 20 | { |
| 21 | using namespace armcomputetensorutils; |
| 22 | |
| 23 | arm_compute::Status ClSpaceToBatchNdWorkloadValidate(const TensorInfo& input, |
| 24 | const TensorInfo& output, |
| 25 | const SpaceToBatchNdDescriptor& descriptor) |
| 26 | { |
| 27 | const arm_compute::TensorInfo aclInputInfo = BuildArmComputeTensorInfo(input, descriptor.m_DataLayout); |
| 28 | const arm_compute::TensorInfo aclOutputInfo = BuildArmComputeTensorInfo(output, descriptor.m_DataLayout); |
| 29 | |
| 30 | // ArmNN blockShape is [H, W] Cl asks for W, H |
| 31 | int32_t blockHeight = boost::numeric_cast<int32_t>(descriptor.m_BlockShape[0]); |
| 32 | int32_t blockWidth = boost::numeric_cast<int32_t>(descriptor.m_BlockShape[1]); |
| 33 | |
| 34 | // ACL expects paddingTopBottom [pad_top, pad_bottom] and paddingLeftRight [pad_left, pad_right] |
| 35 | arm_compute::Size2D paddingLeftRight = BuildArmComputeSize2D( |
| 36 | descriptor.m_PadList[0].first, descriptor.m_PadList[0].second); |
| 37 | arm_compute::Size2D paddingTopBottom = BuildArmComputeSize2D( |
| 38 | descriptor.m_PadList[1].first, descriptor.m_PadList[1].second); |
| 39 | |
| 40 | return arm_compute::CLSpaceToBatchLayer::validate(&aclInputInfo, |
| 41 | blockWidth, |
| 42 | blockHeight, |
| 43 | paddingTopBottom, |
| 44 | paddingLeftRight, |
| 45 | &aclOutputInfo); |
| 46 | } |
| 47 | |
| 48 | ClSpaceToBatchNdWorkload::ClSpaceToBatchNdWorkload( |
| 49 | const SpaceToBatchNdQueueDescriptor& descriptor, const WorkloadInfo& info) |
| 50 | : BaseWorkload<SpaceToBatchNdQueueDescriptor>(descriptor, info) |
| 51 | { |
| 52 | m_Data.ValidateInputsOutputs("ClSpaceToBatchNdWorkload", 1, 1); |
| 53 | |
| 54 | arm_compute::ICLTensor& input = |
| 55 | boost::polymorphic_pointer_downcast<IClTensorHandle>(m_Data.m_Inputs[0])->GetTensor(); |
| 56 | arm_compute::ICLTensor& output = |
| 57 | boost::polymorphic_pointer_downcast<IClTensorHandle>(m_Data.m_Outputs[0])->GetTensor(); |
| 58 | |
| 59 | // ArmNN blockShape is [H, W] Cl asks for W, H |
| 60 | int32_t blockHeight = boost::numeric_cast<int32_t>(m_Data.m_Parameters.m_BlockShape[0]); |
| 61 | int32_t blockWidth = boost::numeric_cast<int32_t>(m_Data.m_Parameters.m_BlockShape[1]); |
| 62 | |
| 63 | // ACL expects paddingTopBottom [pad_top, pad_bottom] and paddingLeftRight [pad_left, pad_right] |
| 64 | arm_compute::Size2D paddingLeftRight = BuildArmComputeSize2D( |
| 65 | m_Data.m_Parameters.m_PadList[0].first, m_Data.m_Parameters.m_PadList[0].second); |
| 66 | arm_compute::Size2D paddingTopBottom = BuildArmComputeSize2D( |
| 67 | m_Data.m_Parameters.m_PadList[1].first, m_Data.m_Parameters.m_PadList[1].second); |
| 68 | |
| 69 | arm_compute::DataLayout aclDataLayout = ConvertDataLayout(m_Data.m_Parameters.m_DataLayout); |
| 70 | input.info()->set_data_layout(aclDataLayout); |
| 71 | output.info()->set_data_layout(aclDataLayout); |
| 72 | |
| 73 | m_SpaceToBatchLayer.configure(&input, |
| 74 | blockWidth, |
| 75 | blockHeight, |
| 76 | paddingTopBottom, |
| 77 | paddingLeftRight, |
| 78 | &output); |
| 79 | } |
| 80 | |
| 81 | void ClSpaceToBatchNdWorkload::Execute() const |
| 82 | { |
| 83 | ARMNN_SCOPED_PROFILING_EVENT_CL("ClSpaceToBatchNdWorkload_Execute"); |
| 84 | RunClFunction(m_SpaceToBatchLayer, CHECK_LOCATION()); |
| 85 | } |
| 86 | |
| 87 | } //namespace armnn |