Nikhil Raj | 68c2c90 | 2019-09-19 11:21:11 +0100 | [diff] [blame] | 1 | // |
Mike Kelly | 1f140f7 | 2021-04-06 12:25:55 +0100 | [diff] [blame] | 2 | // Copyright © 2019 Arm Ltd and Contributors. All rights reserved. |
Nikhil Raj | 68c2c90 | 2019-09-19 11:21:11 +0100 | [diff] [blame] | 3 | // SPDX-License-Identifier: MIT |
| 4 | // |
| 5 | |
| 6 | #include "RefArgMinMaxWorkload.hpp" |
| 7 | |
| 8 | #include "ArgMinMax.hpp" |
| 9 | #include "RefWorkloadUtils.hpp" |
| 10 | #include "Decoders.hpp" |
| 11 | #include "Encoders.hpp" |
| 12 | #include "Profiling.hpp" |
| 13 | |
| 14 | namespace armnn |
| 15 | { |
| 16 | RefArgMinMaxWorkload::RefArgMinMaxWorkload( |
| 17 | const ArgMinMaxQueueDescriptor& descriptor, |
| 18 | const WorkloadInfo& info) |
| 19 | : BaseWorkload<ArgMinMaxQueueDescriptor>(descriptor, info) {} |
| 20 | |
Finn Williams | b8181f7 | 2021-04-07 10:23:21 +0100 | [diff] [blame] | 21 | |
Nikhil Raj | 68c2c90 | 2019-09-19 11:21:11 +0100 | [diff] [blame] | 22 | void RefArgMinMaxWorkload::Execute() const |
| 23 | { |
Finn Williams | b8181f7 | 2021-04-07 10:23:21 +0100 | [diff] [blame] | 24 | Execute(m_Data.m_Inputs, m_Data.m_Outputs); |
| 25 | } |
| 26 | |
| 27 | void RefArgMinMaxWorkload::ExecuteAsync(WorkingMemDescriptor &workingMemDescriptor) |
| 28 | { |
| 29 | Execute(workingMemDescriptor.m_Inputs, workingMemDescriptor.m_Outputs); |
| 30 | } |
| 31 | |
| 32 | void RefArgMinMaxWorkload::Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const |
| 33 | { |
Nikhil Raj | 68c2c90 | 2019-09-19 11:21:11 +0100 | [diff] [blame] | 34 | ARMNN_SCOPED_PROFILING_EVENT(Compute::CpuRef, "RefArgMinMaxWorkload_Execute"); |
| 35 | |
Finn Williams | b8181f7 | 2021-04-07 10:23:21 +0100 | [diff] [blame] | 36 | const TensorInfo &inputTensorInfo = GetTensorInfo(inputs[0]); |
Nikhil Raj | 68c2c90 | 2019-09-19 11:21:11 +0100 | [diff] [blame] | 37 | |
Finn Williams | b8181f7 | 2021-04-07 10:23:21 +0100 | [diff] [blame] | 38 | std::unique_ptr<Decoder<float>> decoderPtr = MakeDecoder<float>(inputTensorInfo, inputs[0]->Map()); |
Nikhil Raj | 68c2c90 | 2019-09-19 11:21:11 +0100 | [diff] [blame] | 39 | Decoder<float> &decoder = *decoderPtr; |
| 40 | |
Finn Williams | b8181f7 | 2021-04-07 10:23:21 +0100 | [diff] [blame] | 41 | const TensorInfo &outputTensorInfo = GetTensorInfo(outputs[0]); |
Nikhil Raj | 68c2c90 | 2019-09-19 11:21:11 +0100 | [diff] [blame] | 42 | |
Mike Kelly | 1f140f7 | 2021-04-06 12:25:55 +0100 | [diff] [blame] | 43 | if (outputTensorInfo.GetDataType() == armnn::DataType::Signed32) { |
Finn Williams | 0109794 | 2021-04-26 12:06:34 +0100 | [diff] [blame] | 44 | int32_t *output = GetOutputTensorData<int32_t>(outputs[0]); |
Inki Dae | d4619e2 | 2020-09-10 15:33:54 +0900 | [diff] [blame] | 45 | ArgMinMax(decoder, output, inputTensorInfo, outputTensorInfo, m_Data.m_Parameters.m_Function, |
| 46 | m_Data.m_Parameters.m_Axis); |
| 47 | } else { |
Finn Williams | 0109794 | 2021-04-26 12:06:34 +0100 | [diff] [blame] | 48 | int64_t *output = GetOutputTensorData<int64_t>(outputs[0]); |
Inki Dae | d4619e2 | 2020-09-10 15:33:54 +0900 | [diff] [blame] | 49 | ArgMinMax(decoder, output, inputTensorInfo, outputTensorInfo, m_Data.m_Parameters.m_Function, |
| 50 | m_Data.m_Parameters.m_Axis); |
| 51 | } |
Nikhil Raj | 68c2c90 | 2019-09-19 11:21:11 +0100 | [diff] [blame] | 52 | } |
| 53 | |
| 54 | } //namespace armnn |