telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 1 | // |
| 2 | // Copyright © 2017 Arm Ltd. All rights reserved. |
David Beck | ecb56cd | 2018-09-05 12:52:57 +0100 | [diff] [blame] | 3 | // SPDX-License-Identifier: MIT |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 4 | // |
| 5 | |
Nattapat Chaimanowong | 7714088 | 2018-10-17 11:12:19 +0100 | [diff] [blame] | 6 | #include "NeonDepthwiseConvolutionWorkload.hpp" |
| 7 | |
Aron Virginas-Tar | c9cc804 | 2018-11-01 16:15:57 +0000 | [diff] [blame] | 8 | #include <aclCommon/ArmComputeTensorUtils.hpp> |
| 9 | #include <neon/NeonLayerSupport.hpp> |
| 10 | #include <backendsCommon/CpuTensorHandle.hpp> |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 11 | |
| 12 | namespace armnn |
| 13 | { |
Nattapat Chaimanowong | 7714088 | 2018-10-17 11:12:19 +0100 | [diff] [blame] | 14 | |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 15 | using namespace armcomputetensorutils; |
| 16 | |
Nattapat Chaimanowong | 7714088 | 2018-10-17 11:12:19 +0100 | [diff] [blame] | 17 | arm_compute::Status NeonDepthwiseConvolutionWorkloadValidate(const TensorInfo& input, |
| 18 | const TensorInfo& output, |
| 19 | const DepthwiseConvolution2dDescriptor& descriptor, |
| 20 | const TensorInfo& weights, |
| 21 | const Optional<TensorInfo>& biases) |
| 22 | { |
| 23 | const arm_compute::TensorInfo aclInputInfo = |
| 24 | BuildArmComputeTensorInfo(input, descriptor.m_DataLayout); |
| 25 | const arm_compute::TensorInfo aclOutputInfo = |
| 26 | BuildArmComputeTensorInfo(output, descriptor.m_DataLayout); |
| 27 | const arm_compute::TensorInfo aclWeightsInfo = |
| 28 | BuildArmComputeTensorInfo(weights, descriptor.m_DataLayout); |
| 29 | |
| 30 | arm_compute::TensorInfo aclBiasesInfo; |
| 31 | arm_compute::TensorInfo *optionalAclBiasesInfo = nullptr; |
| 32 | |
| 33 | if (descriptor.m_BiasEnabled) |
| 34 | { |
| 35 | BOOST_ASSERT(biases.has_value()); |
| 36 | |
| 37 | aclBiasesInfo = BuildArmComputeTensorInfo(biases.value(), descriptor.m_DataLayout); |
| 38 | optionalAclBiasesInfo = &aclBiasesInfo; |
| 39 | } |
| 40 | |
| 41 | const arm_compute::PadStrideInfo aclPadStrideInfo = |
| 42 | BuildArmComputePadStrideInfo(descriptor); |
| 43 | const unsigned int aclDepthMultiplier = weights.GetShape()[0]; |
| 44 | |
| 45 | return arm_compute::NEDepthwiseConvolutionLayer::validate(&aclInputInfo, |
| 46 | &aclWeightsInfo, |
| 47 | optionalAclBiasesInfo, |
| 48 | &aclOutputInfo, |
| 49 | aclPadStrideInfo, |
| 50 | aclDepthMultiplier); |
| 51 | } |
| 52 | |
| 53 | NeonDepthwiseConvolutionWorkload::NeonDepthwiseConvolutionWorkload( |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 54 | const DepthwiseConvolution2dQueueDescriptor& descriptor, |
| 55 | const WorkloadInfo& info) |
Nattapat Chaimanowong | 7714088 | 2018-10-17 11:12:19 +0100 | [diff] [blame] | 56 | : BaseWorkload<DepthwiseConvolution2dQueueDescriptor>(descriptor, info) |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 57 | { |
| 58 | const TensorInfo& weightInfo = m_Data.m_Weight->GetTensorInfo(); |
| 59 | |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 60 | m_KernelTensor = std::make_unique<arm_compute::Tensor>(); |
Nikhil Raj | cec6b65 | 2018-10-12 13:51:57 +0100 | [diff] [blame] | 61 | BuildArmComputeTensor(*m_KernelTensor, weightInfo, m_Data.m_Parameters.m_DataLayout); |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 62 | |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 63 | if (m_Data.m_Parameters.m_BiasEnabled) |
| 64 | { |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 65 | m_BiasTensor = std::make_unique<arm_compute::Tensor>(); |
Nikhil Raj | cec6b65 | 2018-10-12 13:51:57 +0100 | [diff] [blame] | 66 | BuildArmComputeTensor(*m_BiasTensor, m_Data.m_Bias->GetTensorInfo(), m_Data.m_Parameters.m_DataLayout); |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 67 | } |
| 68 | |
| 69 | arm_compute::PadStrideInfo padStrideInfo(m_Data.m_Parameters.m_StrideX, |
| 70 | m_Data.m_Parameters.m_StrideY, |
| 71 | m_Data.m_Parameters.m_PadLeft, |
| 72 | m_Data.m_Parameters.m_PadRight, |
| 73 | m_Data.m_Parameters.m_PadTop, |
| 74 | m_Data.m_Parameters.m_PadBottom, |
| 75 | arm_compute::DimensionRoundingType::FLOOR); |
| 76 | |
Nattapat Chaimanowong | 7714088 | 2018-10-17 11:12:19 +0100 | [diff] [blame] | 77 | m_Data.ValidateInputsOutputs("NeonDepthwiseConvolutionWorkload", 1, 1); |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 78 | |
| 79 | arm_compute::ITensor& input = static_cast<INeonTensorHandle*>(m_Data.m_Inputs[0])->GetTensor(); |
| 80 | arm_compute::ITensor& output = static_cast<INeonTensorHandle*>(m_Data.m_Outputs[0])->GetTensor(); |
| 81 | |
Nikhil Raj | cec6b65 | 2018-10-12 13:51:57 +0100 | [diff] [blame] | 82 | arm_compute::DataLayout aclDataLayout = ConvertDataLayout(m_Data.m_Parameters.m_DataLayout); |
| 83 | input.info()->set_data_layout(aclDataLayout); |
| 84 | output.info()->set_data_layout(aclDataLayout); |
| 85 | |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 86 | bool use3x3Optimisation = weightInfo.GetShape()[3] == 3 && weightInfo.GetShape()[2] == 3; |
| 87 | if (use3x3Optimisation) |
| 88 | { |
| 89 | m_pDepthwiseConvolutionLayer = std::make_unique<arm_compute::NEDepthwiseConvolutionLayer3x3>(); |
| 90 | static_cast<arm_compute::NEDepthwiseConvolutionLayer3x3*>( |
| 91 | m_pDepthwiseConvolutionLayer.get())->configure(&input, |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 92 | m_KernelTensor.get(), |
| 93 | m_BiasTensor.get(), |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 94 | &output, |
| 95 | padStrideInfo); |
| 96 | } |
| 97 | else |
| 98 | { |
| 99 | m_pDepthwiseConvolutionLayer = std::make_unique<arm_compute::NEDepthwiseConvolutionLayer>(); |
| 100 | static_cast<arm_compute::NEDepthwiseConvolutionLayer*>( |
| 101 | m_pDepthwiseConvolutionLayer.get())->configure(&input, |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 102 | m_KernelTensor.get(), |
| 103 | m_BiasTensor.get(), |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 104 | &output, |
| 105 | padStrideInfo); |
| 106 | } |
| 107 | |
| 108 | BOOST_ASSERT(m_pDepthwiseConvolutionLayer); |
| 109 | |
Nattapat Chaimanowong | 177d8d2 | 2018-10-16 13:21:27 +0100 | [diff] [blame] | 110 | InitializeArmComputeTensorData(*m_KernelTensor, m_Data.m_Weight); |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 111 | |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 112 | if (m_BiasTensor) |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 113 | { |
Nattapat Chaimanowong | 177d8d2 | 2018-10-16 13:21:27 +0100 | [diff] [blame] | 114 | InitializeArmComputeTensorData(*m_BiasTensor, m_Data.m_Bias); |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 115 | } |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 116 | |
| 117 | m_pDepthwiseConvolutionLayer->prepare(); |
| 118 | FreeUnusedTensors(); |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 119 | } |
| 120 | |
Nattapat Chaimanowong | 7714088 | 2018-10-17 11:12:19 +0100 | [diff] [blame] | 121 | void NeonDepthwiseConvolutionWorkload::Execute() const |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 122 | { |
Nattapat Chaimanowong | 7714088 | 2018-10-17 11:12:19 +0100 | [diff] [blame] | 123 | ARMNN_SCOPED_PROFILING_EVENT_NEON("NeonDepthwiseConvolutionWorkload_Execute"); |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 124 | BOOST_ASSERT(m_pDepthwiseConvolutionLayer); |
| 125 | |
| 126 | m_pDepthwiseConvolutionLayer->run(); |
| 127 | } |
| 128 | |
Nattapat Chaimanowong | 7714088 | 2018-10-17 11:12:19 +0100 | [diff] [blame] | 129 | void NeonDepthwiseConvolutionWorkload::FreeUnusedTensors() |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 130 | { |
| 131 | FreeTensorIfUnused(m_KernelTensor); |
| 132 | FreeTensorIfUnused(m_BiasTensor); |
| 133 | } |
| 134 | |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 135 | } //namespace armnn |