telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 1 | // |
| 2 | // Copyright © 2017 Arm Ltd. All rights reserved. |
David Beck | ecb56cd | 2018-09-05 12:52:57 +0100 | [diff] [blame] | 3 | // SPDX-License-Identifier: MIT |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 4 | // |
| 5 | |
| 6 | #include "ClDepthwiseConvolutionBaseWorkload.hpp" |
| 7 | |
| 8 | #include "TypeUtils.hpp" |
| 9 | |
David Beck | 711fa31 | 2018-09-24 10:46:38 +0100 | [diff] [blame] | 10 | #include <backends/aclCommon/ArmComputeUtils.hpp> |
| 11 | #include <backends/aclCommon/ArmComputeTensorUtils.hpp> |
| 12 | #include <backends/ClTensorHandle.hpp> |
| 13 | #include <backends/CpuTensorHandle.hpp> |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 14 | |
| 15 | namespace armnn |
| 16 | { |
| 17 | |
| 18 | using namespace armcomputetensorutils; |
| 19 | |
| 20 | arm_compute::Status ClDepthwiseConvolutionWorkloadValidate(const TensorInfo& input, |
| 21 | const TensorInfo& output, |
| 22 | const DepthwiseConvolution2dDescriptor& descriptor, |
| 23 | const TensorInfo& weights, |
arovir01 | a682410 | 2018-08-28 17:40:45 +0100 | [diff] [blame] | 24 | const boost::optional<TensorInfo>& biases) |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 25 | { |
Nikhil Raj | a05c210 | 2018-09-25 16:16:13 +0100 | [diff] [blame^] | 26 | const arm_compute::TensorInfo aclInputInfo = BuildArmComputeTensorInfo(input, descriptor.m_DataLayout); |
| 27 | const arm_compute::TensorInfo aclOutputInfo = BuildArmComputeTensorInfo(output, descriptor.m_DataLayout); |
| 28 | const arm_compute::TensorInfo aclWeightsInfo = BuildArmComputeTensorInfo(weights, descriptor.m_DataLayout); |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 29 | |
| 30 | arm_compute::TensorInfo aclBiasesInfo; |
| 31 | arm_compute::TensorInfo *optionalAclBiasesInfo = nullptr; |
arovir01 | a682410 | 2018-08-28 17:40:45 +0100 | [diff] [blame] | 32 | |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 33 | if (descriptor.m_BiasEnabled) |
| 34 | { |
arovir01 | a682410 | 2018-08-28 17:40:45 +0100 | [diff] [blame] | 35 | BOOST_ASSERT(biases.is_initialized()); |
| 36 | |
Nikhil Raj | a05c210 | 2018-09-25 16:16:13 +0100 | [diff] [blame^] | 37 | aclBiasesInfo = BuildArmComputeTensorInfo(biases.get(), descriptor.m_DataLayout); |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 38 | optionalAclBiasesInfo = &aclBiasesInfo; |
| 39 | } |
| 40 | |
| 41 | const arm_compute::PadStrideInfo aclPadStrideInfo = BuildArmComputePadStrideInfo(descriptor); |
| 42 | const unsigned int aclDepthMultiplier = weights.GetShape()[0]; |
| 43 | |
| 44 | return arm_compute::CLDepthwiseConvolutionLayer::validate(&aclInputInfo, |
| 45 | &aclWeightsInfo, |
| 46 | optionalAclBiasesInfo, |
| 47 | &aclOutputInfo, |
| 48 | aclPadStrideInfo, |
| 49 | aclDepthMultiplier); |
| 50 | } |
| 51 | |
| 52 | template<armnn::DataType... dataTypes> |
| 53 | ClDepthwiseConvolutionBaseWorkload<dataTypes...>::ClDepthwiseConvolutionBaseWorkload( |
| 54 | const DepthwiseConvolution2dQueueDescriptor& descriptor, |
| 55 | const WorkloadInfo& info) |
| 56 | : TypedWorkload<DepthwiseConvolution2dQueueDescriptor, dataTypes...>(descriptor, info) |
| 57 | { |
| 58 | auto& weightInfo = m_Data.m_Weight->GetTensorInfo(); |
| 59 | |
| 60 | m_KernelTensor = std::make_unique<arm_compute::CLTensor>(); |
| 61 | BuildArmComputeTensor(*m_KernelTensor, weightInfo); |
| 62 | |
| 63 | if (m_Data.m_Parameters.m_BiasEnabled) |
| 64 | { |
| 65 | m_BiasTensor = std::make_unique<arm_compute::CLTensor>(); |
| 66 | BuildArmComputeTensor(*m_BiasTensor, m_Data.m_Bias->GetTensorInfo()); |
| 67 | } |
| 68 | |
| 69 | arm_compute::PadStrideInfo padStrideInfo(m_Data.m_Parameters.m_StrideX, |
| 70 | m_Data.m_Parameters.m_StrideY, |
| 71 | m_Data.m_Parameters.m_PadLeft, |
| 72 | m_Data.m_Parameters.m_PadRight, |
| 73 | m_Data.m_Parameters.m_PadTop, |
| 74 | m_Data.m_Parameters.m_PadBottom, |
| 75 | arm_compute::DimensionRoundingType::FLOOR); |
| 76 | |
| 77 | std::string name = std::string("ClDepthwiseConvolution") + |
| 78 | GetDataTypeName(m_Data.m_Weight->GetTensorInfo().GetDataType()) + "Workload"; |
| 79 | m_Data.ValidateInputsOutputs(name, 1, 1); |
| 80 | |
| 81 | arm_compute::ICLTensor& input = static_cast<IClTensorHandle*>(m_Data.m_Inputs[0])->GetTensor(); |
| 82 | arm_compute::ICLTensor& output = static_cast<IClTensorHandle*>(m_Data.m_Outputs[0])->GetTensor(); |
| 83 | |
| 84 | const unsigned int depthMultiplier = weightInfo.GetShape()[0]; |
| 85 | |
| 86 | //Check for optimisation opportunities. |
| 87 | bool use3x3Optimisation = (weightInfo.GetShape()[3] == 3) && (weightInfo.GetShape()[2] == 3); |
| 88 | if (use3x3Optimisation) |
| 89 | { |
| 90 | m_DepthwiseConvolutionLayer = std::make_unique<arm_compute::CLDepthwiseConvolutionLayer3x3>(); |
| 91 | static_cast<arm_compute::CLDepthwiseConvolutionLayer3x3*>(m_DepthwiseConvolutionLayer.get())->configure( |
| 92 | &input, |
| 93 | m_KernelTensor.get(), |
| 94 | m_BiasTensor.get(), |
| 95 | &output, |
| 96 | padStrideInfo, |
| 97 | depthMultiplier); |
| 98 | } |
| 99 | else |
| 100 | { |
| 101 | m_DepthwiseConvolutionLayer = std::make_unique<arm_compute::CLDepthwiseConvolutionLayer>(); |
| 102 | static_cast<arm_compute::CLDepthwiseConvolutionLayer*>(m_DepthwiseConvolutionLayer.get())->configure( |
| 103 | &input, |
| 104 | m_KernelTensor.get(), |
| 105 | m_BiasTensor.get(), |
| 106 | &output, |
| 107 | padStrideInfo, |
| 108 | depthMultiplier); |
| 109 | } |
| 110 | |
| 111 | BOOST_ASSERT(m_DepthwiseConvolutionLayer); |
| 112 | } |
| 113 | |
| 114 | template<armnn::DataType... dataTypes> |
| 115 | void ClDepthwiseConvolutionBaseWorkload<dataTypes...>::FreeUnusedTensors() |
| 116 | { |
| 117 | FreeTensorIfUnused(m_KernelTensor); |
| 118 | FreeTensorIfUnused(m_BiasTensor); |
| 119 | } |
| 120 | |
| 121 | // Generate known implementations for linker |
| 122 | template class ClDepthwiseConvolutionBaseWorkload<DataType::Float16, DataType::Float32>; |
| 123 | template class ClDepthwiseConvolutionBaseWorkload<DataType::QuantisedAsymm8>; |
| 124 | |
| 125 | } // namespace armnn |