telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 1 | // |
| 2 | // Copyright © 2017 Arm Ltd. All rights reserved. |
David Beck | ecb56cd | 2018-09-05 12:52:57 +0100 | [diff] [blame] | 3 | // SPDX-License-Identifier: MIT |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 4 | // |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 5 | |
arovir01 | 43095f3 | 2018-10-09 18:04:24 +0100 | [diff] [blame] | 6 | #include <armnn/test/TensorHelpers.hpp> |
| 7 | #include <armnn/test/UnitTests.hpp> |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 8 | |
David Beck | b4540be | 2018-09-24 13:18:27 +0100 | [diff] [blame] | 9 | #include <backends/CpuTensorHandle.hpp> |
David Beck | 0dbe0ee | 2018-09-24 15:59:27 +0100 | [diff] [blame] | 10 | #include <backends/neon/NeonLayerSupport.hpp> |
| 11 | #include <backends/neon/NeonWorkloadFactory.hpp> |
David Beck | b4540be | 2018-09-24 13:18:27 +0100 | [diff] [blame] | 12 | #include <backends/reference/RefWorkloadFactory.hpp> |
arovir01 | 43095f3 | 2018-10-09 18:04:24 +0100 | [diff] [blame] | 13 | #include <backends/test/ActivationFixture.hpp> |
| 14 | #include <backends/test/LayerTests.hpp> |
David Beck | b4540be | 2018-09-24 13:18:27 +0100 | [diff] [blame] | 15 | #include <backends/test/TensorCopyUtils.hpp> |
arovir01 | 43095f3 | 2018-10-09 18:04:24 +0100 | [diff] [blame] | 16 | #include <backends/test/WorkloadTestUtils.hpp> |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 17 | |
arovir01 | 43095f3 | 2018-10-09 18:04:24 +0100 | [diff] [blame] | 18 | #include <boost/test/unit_test.hpp> |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 19 | |
| 20 | BOOST_AUTO_TEST_SUITE(Compute_ArmComputeNeon) |
| 21 | using FactoryType = armnn::NeonWorkloadFactory; |
| 22 | |
| 23 | // ============================================================================ |
| 24 | // UNIT tests |
| 25 | |
| 26 | // Convolution |
| 27 | ARMNN_AUTO_TEST_CASE(SimpleConvolution1d, Convolution1dTest, true) |
| 28 | |
| 29 | ARMNN_AUTO_TEST_CASE(SimpleConvolution2d, SimpleConvolution2d3x5Test, true) |
| 30 | ARMNN_AUTO_TEST_CASE(SimpleConvolution2dSquare, SimpleConvolution2d3x3Test, true) |
| 31 | ARMNN_AUTO_TEST_CASE(UnbiasedConvolution2d, SimpleConvolution2d3x5Test, false) |
| 32 | ARMNN_AUTO_TEST_CASE(UnbiasedConvolution2dSquare, SimpleConvolution2d3x3Test, false) |
| 33 | ARMNN_AUTO_TEST_CASE(SimpleConvolution2dAsymmetricPadding, Convolution2dAsymmetricPaddingTest) |
| 34 | |
Francis Murtagh | d59116e | 2018-10-04 16:03:07 +0100 | [diff] [blame] | 35 | ARMNN_AUTO_TEST_CASE(SimpleConvolution2dSquareNhwc, SimpleConvolution2d3x3NhwcTest, false) |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 36 | namespace |
| 37 | { |
| 38 | |
| 39 | armnn::Convolution2dDescriptor MakeConv2dDesc(uint32_t strideX, uint32_t strideY, |
| 40 | uint32_t padLeft = 0, uint32_t padRight = 0, uint32_t padTop = 0, uint32_t padBottom = 0) |
| 41 | { |
| 42 | armnn::Convolution2dDescriptor result; |
| 43 | result.m_StrideX = strideX; |
| 44 | result.m_StrideY = strideY; |
| 45 | result.m_PadLeft = padLeft; |
| 46 | result.m_PadRight = padRight; |
| 47 | result.m_PadTop = padTop; |
| 48 | result.m_PadBottom = padBottom; |
| 49 | result.m_BiasEnabled = true; |
| 50 | return result; |
| 51 | } |
| 52 | |
| 53 | } |
| 54 | |
| 55 | BOOST_AUTO_TEST_CASE(Conv2dUtils) |
| 56 | { |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 57 | // The only preferred Neon convolution is 1x1 with padding=0 and stride size {1,2,3}. |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 58 | armnn::TensorShape shape1x1({ 1,1,1,1 }); |
| 59 | armnn::TensorInfo info1x1(shape1x1, armnn::DataType::Float32); |
| 60 | BOOST_TEST(armnn::IsNeonDirectConvolutionPreferred(info1x1, MakeConv2dDesc(1, 1))); |
| 61 | BOOST_TEST(armnn::IsNeonDirectConvolutionPreferred(info1x1, MakeConv2dDesc(1, 2))); |
| 62 | BOOST_TEST(armnn::IsNeonDirectConvolutionPreferred(info1x1, MakeConv2dDesc(1, 3))); |
| 63 | BOOST_TEST(armnn::IsNeonDirectConvolutionPreferred(info1x1, MakeConv2dDesc(2, 1))); |
| 64 | BOOST_TEST(armnn::IsNeonDirectConvolutionPreferred(info1x1, MakeConv2dDesc(2, 2))); |
| 65 | BOOST_TEST(armnn::IsNeonDirectConvolutionPreferred(info1x1, MakeConv2dDesc(2, 3))); |
| 66 | BOOST_TEST(armnn::IsNeonDirectConvolutionPreferred(info1x1, MakeConv2dDesc(3, 1))); |
| 67 | BOOST_TEST(armnn::IsNeonDirectConvolutionPreferred(info1x1, MakeConv2dDesc(3, 2))); |
| 68 | BOOST_TEST(armnn::IsNeonDirectConvolutionPreferred(info1x1, MakeConv2dDesc(3, 3))); |
| 69 | |
| 70 | BOOST_TEST(!armnn::IsNeonDirectConvolutionPreferred(info1x1, MakeConv2dDesc(4, 1))); |
| 71 | BOOST_TEST(!armnn::IsNeonDirectConvolutionPreferred(info1x1, MakeConv2dDesc(4, 5))); |
| 72 | BOOST_TEST(!armnn::IsNeonDirectConvolutionPreferred(info1x1, MakeConv2dDesc(3, 6))); |
| 73 | |
| 74 | // non zero padding is not preferred for direct convolution |
| 75 | BOOST_TEST(!armnn::IsNeonDirectConvolutionPreferred(info1x1, MakeConv2dDesc(1, 1, 1, 0))); |
| 76 | BOOST_TEST(!armnn::IsNeonDirectConvolutionPreferred(info1x1, MakeConv2dDesc(1, 1, 0, 1))); |
| 77 | BOOST_TEST(!armnn::IsNeonDirectConvolutionPreferred(info1x1, MakeConv2dDesc(1, 1, 1, 1))); |
| 78 | |
| 79 | // 2x2 filter not preferred for direct convolution |
| 80 | armnn::TensorShape shape2x2({ 1,1,2,2 }); |
| 81 | armnn::TensorInfo info2x2(shape2x2, armnn::DataType::Float32); |
| 82 | BOOST_TEST(!armnn::IsNeonDirectConvolutionPreferred(info2x2, MakeConv2dDesc(1, 1))); |
| 83 | } |
| 84 | |
| 85 | // Depthwise Convolution |
| 86 | ARMNN_AUTO_TEST_CASE(DepthwiseConvolution2dDepthMul1, DepthwiseConvolution2dDepthMul1Test, true) |
Nikhil Raj | cec6b65 | 2018-10-12 13:51:57 +0100 | [diff] [blame^] | 87 | ARMNN_AUTO_TEST_CASE(DepthwiseConvolution2dDepthNhwc, DepthwiseConvolution2dDepthNhwcTest, false) |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 88 | ARMNN_AUTO_TEST_CASE(UnbiasedDepthwiseConvolution2dDepthMul1, DepthwiseConvolution2dDepthMul1Test, false) |
| 89 | ARMNN_AUTO_TEST_CASE(DepthwiseConvolution2dDepthMul1Uint8, DepthwiseConvolution2dDepthMul1Uint8Test, true) |
| 90 | ARMNN_AUTO_TEST_CASE(UnbiasedDepthwiseConvolution2dDepthMul1Uint8, DepthwiseConvolution2dDepthMul1Uint8Test, false) |
| 91 | |
surmeh01 | 3537c2c | 2018-05-18 16:31:43 +0100 | [diff] [blame] | 92 | ARMNN_AUTO_TEST_CASE(DepthwiseConvolution2dAsymmetric, DepthwiseConvolution2dAsymmetricTest, true) |
| 93 | ARMNN_AUTO_TEST_CASE(UnbiasedDepthwiseConvolution2dAsymmetric, DepthwiseConvolution2dAsymmetricTest, false) |
| 94 | |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 95 | namespace |
| 96 | { |
| 97 | |
| 98 | armnn::DepthwiseConvolution2dDescriptor MakeDepthwiseConv2dDesc(uint32_t strideX, uint32_t strideY, |
| 99 | uint32_t depthMultiplier = 1, uint32_t padLeft = 0, uint32_t padRight = 0, |
| 100 | uint32_t padTop = 0, uint32_t padBottom = 0) |
| 101 | { |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 102 | boost::ignore_unused(depthMultiplier); |
| 103 | |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 104 | armnn::DepthwiseConvolution2dDescriptor desc; |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 105 | |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 106 | desc.m_PadLeft = padLeft; |
| 107 | desc.m_PadRight = padRight; |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 108 | |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 109 | desc.m_PadTop = padTop; |
| 110 | desc.m_PadBottom = padBottom; |
| 111 | desc.m_StrideX = strideX; |
| 112 | desc.m_StrideY = strideY; |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 113 | desc.m_BiasEnabled = false; |
| 114 | |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 115 | return desc; |
| 116 | } |
| 117 | |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 118 | armnn::TensorInfo CreateOutputTensorInfo(const armnn::TensorInfo& inputInfo, |
| 119 | const armnn::TensorInfo& weightsInfo, |
| 120 | const armnn::DepthwiseConvolution2dDescriptor& descriptor, |
| 121 | armnn::DataType dataType) |
| 122 | { |
| 123 | const armnn::TensorShape& inputShape = inputInfo.GetShape(); |
| 124 | const armnn::TensorShape& filterShape = weightsInfo.GetShape(); |
| 125 | |
| 126 | unsigned int inWidth = inputShape[3]; |
| 127 | unsigned int inHeight = inputShape[2]; |
| 128 | unsigned int inBatchSize = inputShape[0]; |
| 129 | |
| 130 | unsigned int filterWidth = filterShape[3]; |
| 131 | unsigned int readWidth = (inWidth + descriptor.m_PadLeft + descriptor.m_PadRight) - (filterWidth); |
| 132 | unsigned int outWidth = 1u + (readWidth / descriptor.m_StrideX); |
| 133 | |
| 134 | unsigned int filterHeight = filterShape[2]; |
| 135 | unsigned int readHeight = (inHeight + descriptor.m_PadTop + descriptor.m_PadBottom) - (filterHeight); |
| 136 | unsigned int outHeight = 1u + (readHeight / descriptor.m_StrideY); |
| 137 | unsigned int depthMultiplier = filterShape[0]; |
| 138 | |
| 139 | unsigned int outChannels = filterShape[1] * depthMultiplier; |
| 140 | unsigned int outBatchSize = inBatchSize; |
| 141 | |
| 142 | armnn::TensorShape outputShape({outBatchSize, outChannels, outHeight, outWidth}); |
| 143 | return armnn::TensorInfo(outputShape, dataType); |
| 144 | } |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 145 | } |
| 146 | |
| 147 | BOOST_AUTO_TEST_CASE(DepthwiseConv2dUtils) |
| 148 | { |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 149 | const armnn::DataType dataType = armnn::DataType::Float32; |
| 150 | |
| 151 | armnn::TensorInfo inputInfo({1, 1, 10, 10 }, dataType); |
| 152 | armnn::TensorInfo outputInfo; |
| 153 | armnn::TensorInfo weightsInfo3x3({ 1, 1, 3, 3 }, dataType); |
| 154 | armnn::TensorInfo biasesInfo; |
| 155 | |
| 156 | armnn::DepthwiseConvolution2dDescriptor descriptor; |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 157 | |
| 158 | // Strides supported: 1,2,3 |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 159 | descriptor = MakeDepthwiseConv2dDesc(1, 1); |
| 160 | outputInfo = CreateOutputTensorInfo(inputInfo, weightsInfo3x3, descriptor, dataType); |
| 161 | BOOST_TEST(armnn::IsDepthwiseConvolutionSupportedNeon(inputInfo, outputInfo, descriptor, |
| 162 | weightsInfo3x3, biasesInfo)); |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 163 | |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 164 | descriptor = MakeDepthwiseConv2dDesc(1, 2); |
| 165 | outputInfo = CreateOutputTensorInfo(inputInfo, weightsInfo3x3, descriptor, dataType); |
| 166 | BOOST_TEST(armnn::IsDepthwiseConvolutionSupportedNeon(inputInfo, outputInfo, descriptor, |
| 167 | weightsInfo3x3, biasesInfo)); |
| 168 | |
| 169 | descriptor = MakeDepthwiseConv2dDesc(1, 3); |
| 170 | outputInfo = CreateOutputTensorInfo(inputInfo, weightsInfo3x3, descriptor, dataType); |
| 171 | BOOST_TEST(armnn::IsDepthwiseConvolutionSupportedNeon(inputInfo, outputInfo, descriptor, |
| 172 | weightsInfo3x3, biasesInfo)); |
| 173 | |
| 174 | descriptor = MakeDepthwiseConv2dDesc(2, 1); |
| 175 | outputInfo = CreateOutputTensorInfo(inputInfo, weightsInfo3x3, descriptor, dataType); |
| 176 | BOOST_TEST(armnn::IsDepthwiseConvolutionSupportedNeon(inputInfo, outputInfo, descriptor, |
| 177 | weightsInfo3x3, biasesInfo)); |
| 178 | |
| 179 | descriptor = MakeDepthwiseConv2dDesc(2, 2); |
| 180 | outputInfo = CreateOutputTensorInfo(inputInfo, weightsInfo3x3, descriptor, dataType); |
| 181 | BOOST_TEST(armnn::IsDepthwiseConvolutionSupportedNeon(inputInfo, outputInfo, descriptor, |
| 182 | weightsInfo3x3, biasesInfo)); |
| 183 | |
| 184 | descriptor = MakeDepthwiseConv2dDesc(2, 3); |
| 185 | outputInfo = CreateOutputTensorInfo(inputInfo, weightsInfo3x3, descriptor, dataType); |
| 186 | BOOST_TEST(armnn::IsDepthwiseConvolutionSupportedNeon(inputInfo, outputInfo, descriptor, |
| 187 | weightsInfo3x3, biasesInfo)); |
| 188 | |
| 189 | descriptor = MakeDepthwiseConv2dDesc(3, 1); |
| 190 | outputInfo = CreateOutputTensorInfo(inputInfo, weightsInfo3x3, descriptor, dataType); |
| 191 | BOOST_TEST(armnn::IsDepthwiseConvolutionSupportedNeon(inputInfo, outputInfo, descriptor, |
| 192 | weightsInfo3x3, biasesInfo)); |
| 193 | |
| 194 | descriptor = MakeDepthwiseConv2dDesc(3, 2); |
| 195 | outputInfo = CreateOutputTensorInfo(inputInfo, weightsInfo3x3, descriptor, dataType); |
| 196 | BOOST_TEST(armnn::IsDepthwiseConvolutionSupportedNeon(inputInfo, outputInfo, descriptor, |
| 197 | weightsInfo3x3, biasesInfo)); |
| 198 | |
| 199 | descriptor = MakeDepthwiseConv2dDesc(3, 3); |
| 200 | outputInfo = CreateOutputTensorInfo(inputInfo, weightsInfo3x3, descriptor, dataType); |
| 201 | BOOST_TEST(armnn::IsDepthwiseConvolutionSupportedNeon(inputInfo, outputInfo, descriptor, |
| 202 | weightsInfo3x3, biasesInfo)); |
| 203 | |
| 204 | // Supported stride 4 |
| 205 | descriptor = MakeDepthwiseConv2dDesc(4, 1); |
| 206 | outputInfo = CreateOutputTensorInfo(inputInfo, weightsInfo3x3, descriptor, dataType); |
| 207 | BOOST_TEST(armnn::IsDepthwiseConvolutionSupportedNeon(inputInfo, outputInfo, descriptor, |
| 208 | weightsInfo3x3, biasesInfo)); |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 209 | |
| 210 | // Supported weights shape 1x1 |
| 211 | armnn::TensorInfo weightsInfo1x1({ 1, 1, 1, 1 }, armnn::DataType::Float32); |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 212 | descriptor = MakeDepthwiseConv2dDesc(1, 1); |
| 213 | outputInfo = CreateOutputTensorInfo(inputInfo, weightsInfo1x1, descriptor, dataType); |
| 214 | BOOST_TEST(armnn::IsDepthwiseConvolutionSupportedNeon(inputInfo, outputInfo, descriptor, |
| 215 | weightsInfo1x1, biasesInfo)); |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 216 | |
| 217 | // Supported shape 2x2 |
| 218 | armnn::TensorInfo weightsInfo2x2({ 1, 1, 2, 2 }, armnn::DataType::Float32); |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 219 | descriptor = MakeDepthwiseConv2dDesc(1, 1); |
| 220 | outputInfo = CreateOutputTensorInfo(inputInfo, weightsInfo2x2, descriptor, dataType); |
| 221 | BOOST_TEST(armnn::IsDepthwiseConvolutionSupportedNeon(inputInfo, outputInfo, descriptor, |
| 222 | weightsInfo2x2, biasesInfo)); |
surmeh01 | 3537c2c | 2018-05-18 16:31:43 +0100 | [diff] [blame] | 223 | |
| 224 | // Asymmetric padding |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 225 | descriptor = MakeDepthwiseConv2dDesc(1, 1, 1, 1, 2, 1, 2); |
| 226 | outputInfo = CreateOutputTensorInfo(inputInfo, weightsInfo3x3, descriptor, dataType); |
| 227 | BOOST_TEST(armnn::IsDepthwiseConvolutionSupportedNeon(inputInfo, outputInfo, descriptor, |
| 228 | weightsInfo3x3, biasesInfo)); |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 229 | } |
| 230 | |
| 231 | // Pooling |
| 232 | ARMNN_AUTO_TEST_CASE(SimpleMaxPooling2dSize3x3Stride2x4, SimpleMaxPooling2dSize3x3Stride2x4Test, true) |
| 233 | ARMNN_AUTO_TEST_CASE(SimpleMaxPooling2dSize3x3Stride2x4Uint8, SimpleMaxPooling2dSize3x3Stride2x4Uint8Test, true) |
| 234 | ARMNN_AUTO_TEST_CASE(SimpleAveragePooling2d, SimpleAveragePooling2dTest) |
Francis Murtagh | 043d0d0 | 2018-10-05 14:08:48 +0100 | [diff] [blame] | 235 | ARMNN_AUTO_TEST_CASE(SimpleAveragePooling2dNhwc, SimpleAveragePooling2dNhwcTest) |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 236 | ARMNN_AUTO_TEST_CASE(SimpleAveragePooling2dUint8, SimpleAveragePooling2dUint8Test) |
surmeh01 | bceff2f | 2018-03-29 16:29:27 +0100 | [diff] [blame] | 237 | |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 238 | ARMNN_AUTO_TEST_CASE(LargeTensorsAveragePooling2d, LargeTensorsAveragePooling2dTest) |
| 239 | ARMNN_AUTO_TEST_CASE(LargeTensorsAveragePooling2dUint8, LargeTensorsAveragePooling2dUint8Test) |
| 240 | |
| 241 | ARMNN_AUTO_TEST_CASE(SimpleL2Pooling2d, SimpleL2Pooling2dTest) |
| 242 | ARMNN_AUTO_TEST_CASE(UNSUPPORTED_SimpleL2Pooling2dUint8, SimpleL2Pooling2dUint8Test) |
| 243 | ARMNN_AUTO_TEST_CASE(L2Pooling2dSize3Stride1, L2Pooling2dSize3Stride1Test) |
| 244 | ARMNN_AUTO_TEST_CASE(UNSUPPORTED_L2Pooling2dSize3Stride1Uint8, L2Pooling2dSize3Stride1Uint8Test) |
| 245 | ARMNN_AUTO_TEST_CASE(L2Pooling2dSize3Stride3, L2Pooling2dSize3Stride3Test) |
| 246 | ARMNN_AUTO_TEST_CASE(UNSUPPORTED_L2Pooling2dSize3Stride3Uint8, L2Pooling2dSize3Stride3Uint8Test) |
| 247 | ARMNN_AUTO_TEST_CASE(L2Pooling2dSize3Stride4, L2Pooling2dSize3Stride4Test) |
| 248 | ARMNN_AUTO_TEST_CASE(UNSUPPORTED_L2Pooling2dSize3Stride4Uint8, L2Pooling2dSize3Stride4Uint8Test) |
| 249 | ARMNN_AUTO_TEST_CASE(L2Pooling2dSize7, L2Pooling2dSize7Test) |
| 250 | ARMNN_AUTO_TEST_CASE(UNSUPPORTED_L2Pooling2dSize7Uint8, L2Pooling2dSize7Uint8Test) |
| 251 | ARMNN_AUTO_TEST_CASE(L2Pooling2dSize9, L2Pooling2dSize9Test) |
| 252 | ARMNN_AUTO_TEST_CASE(UNSUPPORTED_L2Pooling2dSize9Uint8, L2Pooling2dSize9Uint8Test) |
| 253 | |
| 254 | // Ignore padding values for pooling but count padding fields into the divisor |
| 255 | ARMNN_AUTO_TEST_CASE(IgnorePaddingSimpleMaxPooling2d, IgnorePaddingSimpleMaxPooling2dTest) |
| 256 | ARMNN_AUTO_TEST_CASE(IgnorePaddingSimpleMaxPooling2dUint8, IgnorePaddingSimpleMaxPooling2dUint8Test) |
| 257 | ARMNN_AUTO_TEST_CASE(IgnorePaddingMaxPooling2dSize3, IgnorePaddingMaxPooling2dSize3Test) |
| 258 | ARMNN_AUTO_TEST_CASE(IgnorePaddingMaxPooling2dSize3Uint8, IgnorePaddingMaxPooling2dSize3Uint8Test) |
| 259 | |
| 260 | ARMNN_AUTO_TEST_CASE(IgnorePaddingSimpleAveragePooling2d, IgnorePaddingSimpleAveragePooling2dTest) |
| 261 | ARMNN_AUTO_TEST_CASE(IgnorePaddingSimpleAveragePooling2dUint8, IgnorePaddingSimpleAveragePooling2dUint8Test) |
| 262 | ARMNN_AUTO_TEST_CASE(IgnorePaddingSimpleAveragePooling2dNoPadding, IgnorePaddingSimpleAveragePooling2dNoPaddingTest) |
| 263 | ARMNN_AUTO_TEST_CASE(IgnorePaddingSimpleAveragePooling2dNoPaddingUint8, |
| 264 | IgnorePaddingSimpleAveragePooling2dNoPaddingUint8Test) |
| 265 | ARMNN_AUTO_TEST_CASE(IgnorePaddingAveragePooling2dSize3, IgnorePaddingAveragePooling2dSize3Test) |
| 266 | ARMNN_AUTO_TEST_CASE(IgnorePaddingAveragePooling2dSize3Uint8, IgnorePaddingAveragePooling2dSize3Uint8Test) |
surmeh01 | bceff2f | 2018-03-29 16:29:27 +0100 | [diff] [blame] | 267 | ARMNN_AUTO_TEST_CASE(IgnorePaddingAveragePooling2dSize3x2Stride2x2, |
| 268 | IgnorePaddingAveragePooling2dSize3x2Stride2x2Test, false) |
| 269 | ARMNN_AUTO_TEST_CASE(IgnorePaddingAveragePooling2dSize3x2Stride2x2NoPadding, |
| 270 | IgnorePaddingAveragePooling2dSize3x2Stride2x2Test, |
| 271 | true) |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 272 | |
| 273 | ARMNN_AUTO_TEST_CASE(IgnorePaddingSimpleL2Pooling2d, IgnorePaddingSimpleL2Pooling2dTest) |
| 274 | ARMNN_AUTO_TEST_CASE(UNSUPPORTED_IgnorePaddingSimpleL2Pooling2dUint8, IgnorePaddingSimpleL2Pooling2dUint8Test) |
| 275 | ARMNN_AUTO_TEST_CASE(IgnorePaddingL2Pooling2dSize3, IgnorePaddingL2Pooling2dSize3Test) |
| 276 | ARMNN_AUTO_TEST_CASE(UNSUPPORTED_IgnorePaddingL2Pooling2dSize3Uint8, IgnorePaddingL2Pooling2dSize3Uint8Test) |
| 277 | |
| 278 | // Activation |
| 279 | ARMNN_AUTO_TEST_CASE(ConstantLinearActivation, ConstantLinearActivationTest) |
| 280 | |
| 281 | ARMNN_AUTO_TEST_CASE(SimpleSoftmaxBeta1, SimpleSoftmaxTest, 1.0f) |
| 282 | ARMNN_AUTO_TEST_CASE(SimpleSoftmaxBeta2, SimpleSoftmaxTest, 2.0f) |
| 283 | |
| 284 | ARMNN_AUTO_TEST_CASE(SimpleSoftmaxBeta1Uint8, SimpleSoftmaxUint8Test, 1.0f) |
| 285 | ARMNN_AUTO_TEST_CASE(SimpleSoftmaxBeta2Uint8, SimpleSoftmaxUint8Test, 2.0f) |
| 286 | |
| 287 | ARMNN_AUTO_TEST_CASE(ReLu1Uint8, BoundedReLuUint8UpperAndLowerBoundTest) |
| 288 | ARMNN_AUTO_TEST_CASE(ReLu6Uint8, BoundedReLuUint8UpperBoundOnlyTest) |
| 289 | |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 290 | // Softmax |
| 291 | BOOST_AUTO_TEST_CASE(Softmax4dSupport) |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 292 | { |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 293 | const unsigned int numDimensions = 4u; |
| 294 | std::array<unsigned int, numDimensions> dimensionSizes; |
| 295 | dimensionSizes.fill(1u); |
| 296 | |
| 297 | const armnn::TensorInfo inputInfo(numDimensions, &dimensionSizes.front(), armnn::DataType::Float32); |
| 298 | const armnn::TensorInfo outputInfo(numDimensions, &dimensionSizes.front(), armnn::DataType::Float32); |
| 299 | |
| 300 | // 4D Softmax should be reported as unsupported on the NEON backend |
| 301 | BOOST_TEST(!armnn::IsSoftmaxSupportedNeon(inputInfo, outputInfo, armnn::SoftmaxDescriptor())); |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 302 | } |
| 303 | |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 304 | // Splitter |
| 305 | ARMNN_AUTO_TEST_CASE(SimpleSplitter, SplitterTest) |
| 306 | ARMNN_AUTO_TEST_CASE(SimpleSplitterUint8, SplitterUint8Test) |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 307 | |
| 308 | ARMNN_AUTO_TEST_CASE(CopyViaSplitter, CopyViaSplitterTest) |
| 309 | ARMNN_AUTO_TEST_CASE(CopyViaSplitterUint8, CopyViaSplitterUint8Test) |
| 310 | |
| 311 | // Merger |
| 312 | ARMNN_AUTO_TEST_CASE(SimpleMerger, MergerTest) |
| 313 | ARMNN_AUTO_TEST_CASE(MergerUint8, MergerUint8Test) |
| 314 | |
| 315 | // Fully Connected |
| 316 | ARMNN_AUTO_TEST_CASE(SimpleFullyConnected, FullyConnectedFloat32Test, false, false) |
| 317 | ARMNN_AUTO_TEST_CASE(SimpleFullyConnectedWithBias, FullyConnectedFloat32Test, true, false) |
| 318 | ARMNN_AUTO_TEST_CASE(SimpleFullyConnectedWithTranspose, FullyConnectedFloat32Test, false, true) |
| 319 | ARMNN_AUTO_TEST_CASE(FullyConnectedLarge, FullyConnectedLargeTest, false) |
| 320 | ARMNN_AUTO_TEST_CASE(FullyConnectedLargeTransposed, FullyConnectedLargeTest, true) |
kevmay01 | e448be3 | 2018-09-26 10:21:55 +0100 | [diff] [blame] | 321 | ARMNN_AUTO_TEST_CASE(FullyConnectedUint8, FullyConnectedUint8Test, false) |
| 322 | ARMNN_AUTO_TEST_CASE(FullyConnectedBiasedUint8, FullyConnectedUint8Test, true) |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 323 | |
| 324 | // Add |
| 325 | ARMNN_AUTO_TEST_CASE(SimpleAdd, AdditionTest) |
David Beck | bc39245 | 2018-09-10 14:47:28 +0100 | [diff] [blame] | 326 | ARMNN_AUTO_TEST_CASE(AddBroadcast, AdditionBroadcastTest) |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 327 | ARMNN_AUTO_TEST_CASE(AddBroadcast1Element, AdditionBroadcast1ElementTest) |
| 328 | |
David Beck | bc39245 | 2018-09-10 14:47:28 +0100 | [diff] [blame] | 329 | // Sub |
| 330 | ARMNN_AUTO_TEST_CASE(SimpleSub, SubtractionTest) |
| 331 | |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 332 | // Mul |
| 333 | ARMNN_AUTO_TEST_CASE(SimpleMultiplication, MultiplicationTest) |
surmeh01 | 3537c2c | 2018-05-18 16:31:43 +0100 | [diff] [blame] | 334 | ARMNN_AUTO_TEST_CASE(MultiplicationBroadcast1Element, MultiplicationBroadcast1ElementTest) |
| 335 | ARMNN_AUTO_TEST_CASE(MultiplicationBroadcast1DVector, MultiplicationBroadcast1DVectorTest) |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 336 | |
| 337 | // Batch Norm |
| 338 | ARMNN_AUTO_TEST_CASE(BatchNorm, BatchNormTest) |
| 339 | |
| 340 | // Constant |
| 341 | ARMNN_AUTO_TEST_CASE(Constant, ConstantTest) |
| 342 | ARMNN_AUTO_TEST_CASE(ConstantUint8, ConstantTestUint8) |
| 343 | |
| 344 | // Concatenation |
| 345 | ARMNN_AUTO_TEST_CASE(Concatenation1d, Concatenation1dTest) |
| 346 | ARMNN_AUTO_TEST_CASE(Concatenation1dUint8, Concatenation1dUint8Test) |
| 347 | |
| 348 | ARMNN_AUTO_TEST_CASE(Concatenation2dDim0, Concatenation2dDim0Test) |
| 349 | ARMNN_AUTO_TEST_CASE(Concatenation2dDim0Uint8, Concatenation2dDim0Uint8Test) |
| 350 | ARMNN_AUTO_TEST_CASE(Concatenation2dDim1, Concatenation2dDim1Test) |
| 351 | ARMNN_AUTO_TEST_CASE(Concatenation2dDim1Uint8, Concatenation2dDim1Uint8Test) |
| 352 | |
| 353 | ARMNN_AUTO_TEST_CASE(Concatenation2dDim0DiffInputDims, Concatenation2dDim0DiffInputDimsTest) |
| 354 | ARMNN_AUTO_TEST_CASE(Concatenation2dDim0DiffInputDimsUint8, Concatenation2dDim0DiffInputDimsUint8Test) |
| 355 | ARMNN_AUTO_TEST_CASE(Concatenation2dDim1DiffInputDims, Concatenation2dDim1DiffInputDimsTest) |
| 356 | ARMNN_AUTO_TEST_CASE(Concatenation2dDim1DiffInputDimsUint8, Concatenation2dDim1DiffInputDimsUint8Test) |
| 357 | |
| 358 | ARMNN_AUTO_TEST_CASE(Concatenation3dDim0, Concatenation3dDim0Test) |
| 359 | ARMNN_AUTO_TEST_CASE(Concatenation3dDim0Uint8, Concatenation3dDim0Uint8Test) |
| 360 | ARMNN_AUTO_TEST_CASE(Concatenation3dDim1, Concatenation3dDim1Test) |
| 361 | ARMNN_AUTO_TEST_CASE(Concatenation3dDim1Uint8, Concatenation3dDim1Uint8Test) |
| 362 | ARMNN_AUTO_TEST_CASE(Concatenation3dDim2, Concatenation3dDim2Test) |
| 363 | ARMNN_AUTO_TEST_CASE(Concatenation3dDim2Uint8, Concatenation3dDim2Uint8Test) |
| 364 | |
| 365 | ARMNN_AUTO_TEST_CASE(Concatenation3dDim0DiffInputDims, Concatenation3dDim0DiffInputDimsTest) |
| 366 | ARMNN_AUTO_TEST_CASE(Concatenation3dDim0DiffInputDimsUint8, Concatenation3dDim0DiffInputDimsUint8Test) |
| 367 | ARMNN_AUTO_TEST_CASE(Concatenation3dDim1DiffInputDims, Concatenation3dDim1DiffInputDimsTest) |
| 368 | ARMNN_AUTO_TEST_CASE(Concatenation3dDim1DiffInputDimsUint8, Concatenation3dDim1DiffInputDimsUint8Test) |
| 369 | ARMNN_AUTO_TEST_CASE(Concatenation3dDim2DiffInputDims, Concatenation3dDim2DiffInputDimsTest) |
| 370 | ARMNN_AUTO_TEST_CASE(Concatenation3dDim2DiffInputDimsUint8, Concatenation3dDim2DiffInputDimsUint8Test) |
| 371 | |
| 372 | // L2 Normalization |
Matteo Martincigh | 539b44d | 2018-10-01 09:26:39 +0100 | [diff] [blame] | 373 | ARMNN_AUTO_TEST_CASE(L2Normalization1d, L2Normalization1dTest) |
| 374 | ARMNN_AUTO_TEST_CASE(L2Normalization2d, L2Normalization2dTest) |
| 375 | ARMNN_AUTO_TEST_CASE(L2Normalization3d, L2Normalization3dTest) |
| 376 | ARMNN_AUTO_TEST_CASE(L2Normalization4d, L2Normalization4dTest) |
| 377 | |
| 378 | ARMNN_AUTO_TEST_CASE(L2Normalization1dNhwc, L2Normalization1dNhwcTest) |
| 379 | ARMNN_AUTO_TEST_CASE(L2Normalization2dNhwc, L2Normalization2dNhwcTest) |
| 380 | ARMNN_AUTO_TEST_CASE(L2Normalization3dNhwc, L2Normalization3dNhwcTest) |
| 381 | ARMNN_AUTO_TEST_CASE(L2Normalization4dNhwc, L2Normalization4dNhwcTest) |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 382 | |
| 383 | // Floor |
| 384 | ARMNN_AUTO_TEST_CASE(SimpleFloor, SimpleFloorTest) |
| 385 | |
| 386 | // Reshape |
| 387 | ARMNN_AUTO_TEST_CASE(SimpleReshapeFloat32, SimpleReshapeFloat32Test) |
| 388 | ARMNN_AUTO_TEST_CASE(SimpleReshapeUint8, SimpleReshapeUint8Test) |
| 389 | |
| 390 | // Permute |
| 391 | ARMNN_AUTO_TEST_CASE(SimplePermuteFloat32, SimplePermuteFloat32Test) |
| 392 | ARMNN_AUTO_TEST_CASE(SimplePermuteUint8, SimplePermuteUint8Test) |
surmeh01 | bceff2f | 2018-03-29 16:29:27 +0100 | [diff] [blame] | 393 | ARMNN_AUTO_TEST_CASE(PermuteFloat32ValueSet1, PermuteFloat32ValueSet1Test) |
| 394 | ARMNN_AUTO_TEST_CASE(PermuteFloat32ValueSet2, PermuteFloat32ValueSet2Test) |
| 395 | ARMNN_AUTO_TEST_CASE(PermuteFloat32ValueSet3, PermuteFloat32ValueSet3Test) |
| 396 | |
Les Bell | de9011b | 2018-10-03 10:37:52 +0100 | [diff] [blame] | 397 | // Lstm |
| 398 | ARMNN_AUTO_TEST_CASE(LstmLayerFloat32WithCifgWithPeepholeNoProjection, |
| 399 | LstmLayerFloat32WithCifgWithPeepholeNoProjectionTest) |
| 400 | ARMNN_AUTO_TEST_CASE(LstmLayerFloat32NoCifgNoPeepholeNoProjection, |
| 401 | LstmLayerFloat32NoCifgNoPeepholeNoProjectionTest) |
| 402 | ARMNN_AUTO_TEST_CASE(LstmLayerFloat32NoCifgWithPeepholeWithProjection, |
| 403 | LstmLayerFloat32NoCifgWithPeepholeWithProjectionTest) |
| 404 | |
narpra01 | 55a97bc | 2018-10-02 14:35:53 +0100 | [diff] [blame] | 405 | // Normalization |
| 406 | ARMNN_AUTO_TEST_CASE(SimpleNormalizationAcross, SimpleNormalizationAcrossTest) |
| 407 | ARMNN_AUTO_TEST_CASE(SimpleNormalizationWithin, SimpleNormalizationWithinTest) |
| 408 | ARMNN_AUTO_TEST_CASE(SimpleNormalizationAcrossNhwc, SimpleNormalizationAcrossNhwcTest) |
| 409 | |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 410 | // ============================================================================ |
| 411 | // COMPARE tests |
| 412 | |
| 413 | ARMNN_COMPARE_REF_AUTO_TEST_CASE(CompareConv2dWithReference, CompareConvolution2dTest) |
| 414 | |
| 415 | ARMNN_COMPARE_REF_AUTO_TEST_CASE(CompareDepthwiseConv2dWithReferenceFloat32, CompareDepthwiseConvolution2dTest<float>) |
| 416 | ARMNN_COMPARE_REF_AUTO_TEST_CASE(CompareDepthwiseConv2dWithReferenceUint8, CompareDepthwiseConvolution2dTest<uint8_t>) |
| 417 | |
| 418 | ARMNN_COMPARE_REF_AUTO_TEST_CASE(CompareNormalizationWithinWithReference, CompareNormalizationTest, |
| 419 | armnn::NormalizationAlgorithmChannel::Within, |
| 420 | armnn::NormalizationAlgorithmMethod::LocalBrightness) |
| 421 | ARMNN_COMPARE_REF_AUTO_TEST_CASE(CompareNormalizationAcrossWithReference, CompareNormalizationTest, |
| 422 | armnn::NormalizationAlgorithmChannel::Across, |
| 423 | armnn::NormalizationAlgorithmMethod::LocalBrightness) |
| 424 | |
| 425 | ARMNN_COMPARE_REF_AUTO_TEST_CASE(CompareMaxPooling2dWithReference, ComparePooling2dTest, armnn::PoolingAlgorithm::Max) |
| 426 | ARMNN_COMPARE_REF_AUTO_TEST_CASE(CompareMaxPooling2dWithReferenceUint8, ComparePooling2dUint8Test, |
| 427 | armnn::PoolingAlgorithm::Max) |
| 428 | ARMNN_COMPARE_REF_AUTO_TEST_CASE(CompareAveragePooling2dWithReference, ComparePooling2dTest, |
| 429 | armnn::PoolingAlgorithm::Average) |
| 430 | ARMNN_COMPARE_REF_AUTO_TEST_CASE(CompareAveragePooling2dWithReferenceUint8, ComparePooling2dUint8Test, |
| 431 | armnn::PoolingAlgorithm::Average) |
| 432 | ARMNN_COMPARE_REF_AUTO_TEST_CASE(CompareL2Pooling2dWithReference, ComparePooling2dTest, armnn::PoolingAlgorithm::L2) |
| 433 | ARMNN_COMPARE_REF_AUTO_TEST_CASE(UNSUPPORTED_CompareL2Pooling2dWithReferenceUint8, ComparePooling2dUint8Test, |
| 434 | armnn::PoolingAlgorithm::L2) |
| 435 | |
| 436 | ARMNN_COMPARE_REF_AUTO_TEST_CASE(CompareSoftmaxBeta1WithReference, CompareSoftmaxTest, 1.0f) |
| 437 | ARMNN_COMPARE_REF_AUTO_TEST_CASE(CompareSoftmaxBeta2WithReference, CompareSoftmaxTest, 2.0f) |
| 438 | |
| 439 | ARMNN_COMPARE_REF_AUTO_TEST_CASE(CompareSoftmaxUint8Beta1WithReference, CompareSoftmaxUint8Test, 1.0f) |
| 440 | ARMNN_COMPARE_REF_AUTO_TEST_CASE(CompareSoftmaxUint8Beta2WithReference, CompareSoftmaxUint8Test, 2.0f) |
| 441 | |
| 442 | ARMNN_COMPARE_REF_AUTO_TEST_CASE(CompareAddition, CompareAdditionTest) |
| 443 | |
| 444 | ARMNN_COMPARE_REF_AUTO_TEST_CASE(CompareMultiplicationWithReference, CompareMultiplicationTest) |
| 445 | |
| 446 | ARMNN_COMPARE_REF_AUTO_TEST_CASE(CompareBatchNorm, CompareBatchNormTest) |
| 447 | |
| 448 | ARMNN_COMPARE_REF_AUTO_TEST_CASE(ReLu1, CompareBoundedReLuTest, 1.0f, -1.0f) |
| 449 | ARMNN_COMPARE_REF_AUTO_TEST_CASE(ReLu6, CompareBoundedReLuTest, 6.0f, 0.0f) |
| 450 | |
| 451 | // ============================================================================ |
| 452 | // FIXTURE tests |
| 453 | |
| 454 | ARMNN_COMPARE_REF_FIXTURE_TEST_CASE(CompareSigmoidActivationWithReference, ActivationFixture, |
| 455 | CompareActivationTest, armnn::ActivationFunction::Sigmoid, 5u) |
| 456 | |
| 457 | ARMNN_COMPARE_REF_FIXTURE_TEST_CASE(CompareTanhActivationWithReference, ActivationFixture, |
| 458 | CompareActivationTest, armnn::ActivationFunction::TanH, 5u) |
| 459 | |
| 460 | ARMNN_COMPARE_REF_FIXTURE_TEST_CASE(CompareLinearActivationWithReference, ActivationFixture, |
| 461 | CompareActivationTest, armnn::ActivationFunction::Linear, 5u) |
| 462 | |
| 463 | ARMNN_COMPARE_REF_FIXTURE_TEST_CASE(CompareReLuActivationWithReference, ActivationFixture, |
| 464 | CompareActivationTest, armnn::ActivationFunction::ReLu, 5u) |
| 465 | |
| 466 | ARMNN_COMPARE_REF_FIXTURE_TEST_CASE(CompareBoundedReLuActivationWithReference, ActivationFixture, |
| 467 | CompareActivationTest, armnn::ActivationFunction::BoundedReLu, 5u) |
| 468 | ARMNN_COMPARE_REF_FIXTURE_TEST_CASE(CompareBoundedReLuActivationWithReferenceUint8, ActivationFixture, |
| 469 | CompareActivationUint8Test, armnn::ActivationFunction::BoundedReLu) |
| 470 | |
| 471 | ARMNN_COMPARE_REF_FIXTURE_TEST_CASE(CompareSoftReLuActivationWithReference, ActivationFixture, |
| 472 | CompareActivationTest, armnn::ActivationFunction::SoftReLu, 1u) |
| 473 | |
| 474 | ARMNN_COMPARE_REF_FIXTURE_TEST_CASE(CompareLeakyReLuActivationWithReference, ActivationFixture, |
| 475 | CompareActivationTest, armnn::ActivationFunction::LeakyReLu, 5u) |
| 476 | |
| 477 | ARMNN_COMPARE_REF_FIXTURE_TEST_CASE(CompareAbsActivationWithReference, ActivationFixture, |
| 478 | CompareActivationTest, armnn::ActivationFunction::Abs, 5u) |
| 479 | |
| 480 | ARMNN_COMPARE_REF_FIXTURE_TEST_CASE(CompareSqrtActivationWithReference, PositiveActivationFixture, |
| 481 | CompareActivationTest, armnn::ActivationFunction::Sqrt, 5u) |
| 482 | |
| 483 | ARMNN_COMPARE_REF_FIXTURE_TEST_CASE(CompareSquareActivationWithReference, ActivationFixture, |
| 484 | CompareActivationTest, armnn::ActivationFunction::Square, 5u) |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 485 | BOOST_AUTO_TEST_SUITE_END() |