commit 1683665c5c3b782a872ce67fde38f814b3fae078
author Jonny Svärd <jonny.svaerd@arm.com> Thu Nov 18 12:14:21 2021 +0100
committer Kristofer Jonsson <kristofer.jonsson@arm.com> Thu Nov 18 12:01:44 2021 +0000
tree 5fb05b1667c8388bfbf1c9a9681baf44840040f0
parent 13cb089bf45f568a013f1e43c51c8a6ae28efbd5

Fix PMU event order to comply with interface files

Change-Id: I9e460e25e4c8ea4a86b460dbf4c634afb912b4de

include/pmu_ethosu.h

diff --git a/include/pmu_ethosu.h b/include/pmu_ethosu.h
index ceefda8..0c1475d 100644
--- a/include/pmu_ethosu.h
+++ b/include/pmu_ethosu.h
@@ -105,6 +105,15 @@
     ETHOSU_PMU_AXI0_ENABLED_CYCLES,
     ETHOSU_PMU_AXI0_RD_STALL_LIMIT,
     ETHOSU_PMU_AXI0_WR_STALL_LIMIT,
+    ETHOSU_PMU_AXI_LATENCY_ANY,
+    ETHOSU_PMU_AXI_LATENCY_32,
+    ETHOSU_PMU_AXI_LATENCY_64,
+    ETHOSU_PMU_AXI_LATENCY_128,
+    ETHOSU_PMU_AXI_LATENCY_256,
+    ETHOSU_PMU_AXI_LATENCY_512,
+    ETHOSU_PMU_AXI_LATENCY_1024,
+    ETHOSU_PMU_ECC_DMA,
+    ETHOSU_PMU_ECC_SB0,
     ETHOSU_PMU_AXI1_RD_TRANS_ACCEPTED,
     ETHOSU_PMU_AXI1_RD_TRANS_COMPLETED,
     ETHOSU_PMU_AXI1_RD_DATA_BEAT_RECEIVED,
@@ -118,15 +127,6 @@
     ETHOSU_PMU_AXI1_ENABLED_CYCLES,
     ETHOSU_PMU_AXI1_RD_STALL_LIMIT,
     ETHOSU_PMU_AXI1_WR_STALL_LIMIT,
-    ETHOSU_PMU_AXI_LATENCY_ANY,
-    ETHOSU_PMU_AXI_LATENCY_32,
-    ETHOSU_PMU_AXI_LATENCY_64,
-    ETHOSU_PMU_AXI_LATENCY_128,
-    ETHOSU_PMU_AXI_LATENCY_256,
-    ETHOSU_PMU_AXI_LATENCY_512,
-    ETHOSU_PMU_AXI_LATENCY_1024,
-    ETHOSU_PMU_ECC_DMA,
-    ETHOSU_PMU_ECC_SB0,
     ETHOSU_PMU_ECC_SB1,
 
     ETHOSU_PMU_SENTINEL // End-marker (not event)