diff --git a/src/ethosu_pmu.c b/src/ethosu_pmu.c
index 1d3b66c..62dc5da 100644
--- a/src/ethosu_pmu.c
+++ b/src/ethosu_pmu.c
@@ -22,9 +22,11 @@
 
 #include "ethosu55_interface.h"
 #include "ethosu_common.h"
+#include "ethosu_driver.h"
+#include "pmu_ethosu.h"
+
 #include <assert.h>
-#include <ethosu_driver.h>
-#include <pmu_ethosu.h>
+#include <stddef.h>
 #include <stdint.h>
 
 /*****************************************************************************
@@ -49,6 +51,13 @@
  * Variables
  *****************************************************************************/
 
+/**
+ *  NOTE: A pointer to ethosu_driver will be added to the PMU functions
+ * when multi-NPU functionality is implemented later. We shall use a
+ * shared ethosu_driver instance till then.
+ * */
+extern struct ethosu_driver ethosu_drv;
+
 static const enum pmu_event_type eventbyid[] = {EXPAND_PMU_EVENT_TYPE(EVID, COMMA)};
 
 /*****************************************************************************
@@ -78,21 +87,21 @@
 void ethosu_pmu_driver_init(void)
 {
 #ifdef PMU_AUTOINIT
-    write_reg(NPU_REG_PMCR, INIT_PMCR);
-    write_reg(NPU_REG_PMCNTENSET, INIT_PMCNTENSET);
-    write_reg(NPU_REG_PMCNTENCLR, INIT_PMCNTENCLR);
-    write_reg(NPU_REG_PMOVSSET, INIT_PMOVSSET);
-    write_reg(NPU_REG_PMOVSCLR, INIT_PMOVSCLR);
-    write_reg(NPU_REG_PMINTSET, INIT_PMINTSET);
-    write_reg(NPU_REG_PMINTCLR, INIT_PMINTCLR);
-    write_reg(NPU_REG_PMCCNTR_LO, INIT_PMCCNTR);
-    write_reg(NPU_REG_PMCCNTR_HI, INIT_PMCCNTR);
-    write_reg(NPU_REG_PMCCNTR_CFG, INIT_PMCCNTR_CFG);
+    ethosu_write_reg(&ethosu_drv.dev, NPU_REG_PMCR, INIT_PMCR);
+    ethosu_write_reg(&ethosu_drv.dev, NPU_REG_PMCNTENSET, INIT_PMCNTENSET);
+    ethosu_write_reg(&ethosu_drv.dev, NPU_REG_PMCNTENCLR, INIT_PMCNTENCLR);
+    ethosu_write_reg(&ethosu_drv.dev, NPU_REG_PMOVSSET, INIT_PMOVSSET);
+    ethosu_write_reg(&ethosu_drv.dev, NPU_REG_PMOVSCLR, INIT_PMOVSCLR);
+    ethosu_write_reg(&ethosu_drv.dev, NPU_REG_PMINTSET, INIT_PMINTSET);
+    ethosu_write_reg(&ethosu_drv.dev, NPU_REG_PMINTCLR, INIT_PMINTCLR);
+    ethosu_write_reg(&ethosu_drv.dev, NPU_REG_PMCCNTR_LO, INIT_PMCCNTR);
+    ethosu_write_reg(&ethosu_drv.dev, NPU_REG_PMCCNTR_HI, INIT_PMCCNTR);
+    ethosu_write_reg(&ethosu_drv.dev, NPU_REG_PMCCNTR_CFG, INIT_PMCCNTR_CFG);
 
     for (int i = 0; i < ETHOSU_PMU_NCOUNTERS; i++)
     {
-        write_reg(NPU_REG_PMEVCNTR(i), 0);
-        write_reg(NPU_REG_PMEVTYPER(i), 0);
+        ethosu_write_reg(&ethosu_drv.dev, NPU_REG_PMEVCNTR(i), 0);
+        ethosu_write_reg(&ethosu_drv.dev, NPU_REG_PMEVTYPER(i), 0);
     }
 #endif
 }
@@ -102,64 +111,66 @@
 void ETHOSU_PMU_Enable(void)
 {
     struct pmcr_r pmcr;
-    pmcr.word   = read_reg(NPU_REG_PMCR);
+    pmcr.word   = ethosu_read_reg(&ethosu_drv.dev, NPU_REG_PMCR);
     pmcr.cnt_en = 1;
-    write_reg(NPU_REG_PMCR, pmcr.word);
+    ethosu_write_reg(&ethosu_drv.dev, NPU_REG_PMCR, pmcr.word);
 }
 
 void ETHOSU_PMU_Disable(void)
 {
     struct pmcr_r pmcr;
-    pmcr.word   = read_reg(NPU_REG_PMCR);
+    pmcr.word   = ethosu_read_reg(&ethosu_drv.dev, NPU_REG_PMCR);
     pmcr.cnt_en = 0;
-    write_reg(NPU_REG_PMCR, pmcr.word);
+    ethosu_write_reg(&ethosu_drv.dev, NPU_REG_PMCR, pmcr.word);
 }
 
 void ETHOSU_PMU_Set_EVTYPER(uint32_t num, enum ethosu_pmu_event_type type)
 {
-    write_reg(NPU_REG_PMEVTYPER(num), pmu_event_value(type));
+    ethosu_write_reg(&ethosu_drv.dev, NPU_REG_PMEVTYPER(num), pmu_event_value(type));
 }
 
 enum ethosu_pmu_event_type ETHOSU_PMU_Get_EVTYPER(uint32_t num)
 {
-    return pmu_event_type(read_reg(NPU_REG_PMEVTYPER(num)));
+    return pmu_event_type(ethosu_read_reg(&ethosu_drv.dev, NPU_REG_PMEVTYPER(num)));
 }
 
 void ETHOSU_PMU_CYCCNT_Reset(void)
 {
     struct pmcr_r pmcr;
-    pmcr.word          = read_reg(NPU_REG_PMCR);
+    pmcr.word          = ethosu_read_reg(&ethosu_drv.dev, NPU_REG_PMCR);
     pmcr.cycle_cnt_rst = 1;
-    write_reg(NPU_REG_PMCR, pmcr.word);
+    ethosu_write_reg(&ethosu_drv.dev, NPU_REG_PMCR, pmcr.word);
 }
 
 void ETHOSU_PMU_EVCNTR_ALL_Reset(void)
 {
     struct pmcr_r pmcr;
-    pmcr.word          = read_reg(NPU_REG_PMCR);
+    pmcr.word          = ethosu_read_reg(&ethosu_drv.dev, NPU_REG_PMCR);
     pmcr.event_cnt_rst = 1;
-    write_reg(NPU_REG_PMCR, pmcr.word);
+    ethosu_write_reg(&ethosu_drv.dev, NPU_REG_PMCR, pmcr.word);
 }
 
 void ETHOSU_PMU_CNTR_Enable(uint32_t mask)
 {
-    write_reg(NPU_REG_PMCNTENSET, mask);
+    ethosu_write_reg(&ethosu_drv.dev, NPU_REG_PMCNTENSET, mask);
 }
 
 void ETHOSU_PMU_CNTR_Disable(uint32_t mask)
 {
-    write_reg(NPU_REG_PMCNTENCLR, mask);
+    ethosu_write_reg(&ethosu_drv.dev, NPU_REG_PMCNTENCLR, mask);
 }
 
-uint32_t ETHOSU_PMU_CNTR_Status()
+uint32_t ETHOSU_PMU_CNTR_Status(void)
 {
-    return read_reg(NPU_REG_PMCNTENSET);
+    return ethosu_read_reg(&ethosu_drv.dev, NPU_REG_PMCNTENSET);
 }
 
 uint64_t ETHOSU_PMU_Get_CCNTR(void)
 {
-    uint64_t val1 = (((uint64_t)read_reg(NPU_REG_PMCCNTR_HI)) << 32) | read_reg(NPU_REG_PMCCNTR_LO);
-    uint64_t val2 = (((uint64_t)read_reg(NPU_REG_PMCCNTR_HI)) << 32) | read_reg(NPU_REG_PMCCNTR_LO);
+    uint64_t val1 = (((uint64_t)ethosu_read_reg(&ethosu_drv.dev, NPU_REG_PMCCNTR_HI)) << 32) |
+                    ethosu_read_reg(&ethosu_drv.dev, NPU_REG_PMCCNTR_LO);
+    uint64_t val2 = (((uint64_t)ethosu_read_reg(&ethosu_drv.dev, NPU_REG_PMCCNTR_HI)) << 32) |
+                    ethosu_read_reg(&ethosu_drv.dev, NPU_REG_PMCCNTR_LO);
 
     if (val2 > val1)
     {
@@ -177,8 +188,8 @@
         ETHOSU_PMU_CNTR_Disable(ETHOSU_PMU_CCNT_Msk);
     }
 
-    write_reg(NPU_REG_PMCCNTR_LO, (val & MASK_0_31_BITS));
-    write_reg(NPU_REG_PMCCNTR_HI, (val & MASK_32_47_BITS) >> 32);
+    ethosu_write_reg(&ethosu_drv.dev, NPU_REG_PMCCNTR_LO, (val & MASK_0_31_BITS));
+    ethosu_write_reg(&ethosu_drv.dev, NPU_REG_PMCCNTR_HI, (val & MASK_32_47_BITS) >> 32);
 
     if (mask & ETHOSU_PMU_CCNT_Msk)
     {
@@ -188,39 +199,39 @@
 
 uint32_t ETHOSU_PMU_Get_EVCNTR(uint32_t num)
 {
-    return read_reg(NPU_REG_PMEVCNTR(num));
+    return ethosu_read_reg(&ethosu_drv.dev, NPU_REG_PMEVCNTR(num));
 }
 
 void ETHOSU_PMU_Set_EVCNTR(uint32_t num, uint32_t val)
 {
-    write_reg(NPU_REG_PMEVCNTR(num), val);
+    ethosu_write_reg(&ethosu_drv.dev, NPU_REG_PMEVCNTR(num), val);
 }
 
 uint32_t ETHOSU_PMU_Get_CNTR_OVS(void)
 {
-    return read_reg(NPU_REG_PMOVSSET);
+    return ethosu_read_reg(&ethosu_drv.dev, NPU_REG_PMOVSSET);
 }
 
 // TODO: check if this function name match with the description &
 // implementation.
 void ETHOSU_PMU_Set_CNTR_OVS(uint32_t mask)
 {
-    write_reg(NPU_REG_PMOVSCLR, mask);
+    ethosu_write_reg(&ethosu_drv.dev, NPU_REG_PMOVSCLR, mask);
 }
 
 void ETHOSU_PMU_Set_CNTR_IRQ_Enable(uint32_t mask)
 {
-    write_reg(NPU_REG_PMINTSET, mask);
+    ethosu_write_reg(&ethosu_drv.dev, NPU_REG_PMINTSET, mask);
 }
 
 void ETHOSU_PMU_Set_CNTR_IRQ_Disable(uint32_t mask)
 {
-    write_reg(NPU_REG_PMINTCLR, mask);
+    ethosu_write_reg(&ethosu_drv.dev, NPU_REG_PMINTCLR, mask);
 }
 
-uint32_t ETHOSU_PMU_Get_IRQ_Enable()
+uint32_t ETHOSU_PMU_Get_IRQ_Enable(void)
 {
-    return read_reg(NPU_REG_PMINTSET);
+    return ethosu_read_reg(&ethosu_drv.dev, NPU_REG_PMINTSET);
 }
 
 void ETHOSU_PMU_CNTR_Increment(uint32_t mask)
@@ -233,8 +244,8 @@
         {
             ETHOSU_PMU_CNTR_Disable(ETHOSU_PMU_CCNT_Msk);
             uint64_t val = ETHOSU_PMU_Get_CCNTR() + 1;
-            write_reg(NPU_REG_PMCCNTR_LO, (val & MASK_0_31_BITS));
-            write_reg(NPU_REG_PMCCNTR_HI, (val & MASK_32_47_BITS) >> 32);
+            ethosu_write_reg(&ethosu_drv.dev, NPU_REG_PMCCNTR_LO, (val & MASK_0_31_BITS));
+            ethosu_write_reg(&ethosu_drv.dev, NPU_REG_PMCCNTR_HI, (val & MASK_32_47_BITS) >> 32);
             if (cntrs_active & ETHOSU_PMU_CCNT_Msk)
             {
                 ETHOSU_PMU_CNTR_Enable(ETHOSU_PMU_CCNT_Msk);
@@ -248,8 +259,8 @@
         if (mask & cntr)
         {
             ETHOSU_PMU_CNTR_Disable(cntr);
-            uint32_t val = read_reg(NPU_REG_PMEVCNTR(i));
-            write_reg(NPU_REG_PMEVCNTR(i), val + 1);
+            uint32_t val = ethosu_read_reg(&ethosu_drv.dev, NPU_REG_PMEVCNTR(i));
+            ethosu_write_reg(&ethosu_drv.dev, NPU_REG_PMEVCNTR(i), val + 1);
             if (cntrs_active & cntr)
             {
                 ETHOSU_PMU_CNTR_Enable(cntr);
@@ -261,15 +272,15 @@
 void ETHOSU_PMU_PMCCNTR_CFG_Set_Start_Event(uint32_t start_event)
 {
     struct pmccntr_cfg_r cfg;
-    cfg.word                = read_reg(NPU_REG_PMCCNTR_CFG);
+    cfg.word                = ethosu_read_reg(&ethosu_drv.dev, NPU_REG_PMCCNTR_CFG);
     cfg.CYCLE_CNT_CFG_START = start_event & ETHOSU_PMCCNTR_CFG_START_STOP_EVENT_MASK;
-    write_reg(NPU_REG_PMCCNTR_CFG, cfg.word);
+    ethosu_write_reg(&ethosu_drv.dev, NPU_REG_PMCCNTR_CFG, cfg.word);
 }
 
 void ETHOSU_PMU_PMCCNTR_CFG_Set_Stop_Event(uint32_t stop_event)
 {
     struct pmccntr_cfg_r cfg;
-    cfg.word               = read_reg(NPU_REG_PMCCNTR_CFG);
+    cfg.word               = ethosu_read_reg(&ethosu_drv.dev, NPU_REG_PMCCNTR_CFG);
     cfg.CYCLE_CNT_CFG_STOP = stop_event & ETHOSU_PMCCNTR_CFG_START_STOP_EVENT_MASK;
-    write_reg(NPU_REG_PMCCNTR_CFG, cfg.word);
+    ethosu_write_reg(&ethosu_drv.dev, NPU_REG_PMCCNTR_CFG, cfg.word);
 }