diff --git a/include/ethosu_driver.h b/include/ethosu_driver.h
index e2d3f5b..d2f2f52 100644
--- a/include/ethosu_driver.h
+++ b/include/ethosu_driver.h
@@ -50,9 +50,6 @@
  * Types
  ******************************************************************************/
 
-// Forward declare
-struct ethosu_device;
-
 enum ethosu_job_state
 {
     ETHOSU_JOB_IDLE = 0,
@@ -81,7 +78,7 @@
 
 struct ethosu_driver
 {
-    struct ethosu_device *dev;
+    struct ethosu_device dev;
     struct ethosu_driver *next;
     struct ethosu_job job;
     void *semaphore;
diff --git a/include/ethosu_types.h b/include/ethosu_types.h
index a8062dd..9d14a60 100644
--- a/include/ethosu_types.h
+++ b/include/ethosu_types.h
@@ -1,6 +1,5 @@
 /*
- * Copyright (c) 2019-2021 Arm Limited. All rights reserved.
- *
+ * SPDX-FileCopyrightText: Copyright 2019-2021, 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
  * SPDX-License-Identifier: Apache-2.0
  *
  * Licensed under the Apache License, Version 2.0 (the License); you may
@@ -29,6 +28,15 @@
  * Types
  ******************************************************************************/
 
+struct NPU_REG; // Forward declare, to be implemented by each device
+
+struct ethosu_device
+{
+    volatile struct NPU_REG *reg; // Register map
+    uint32_t secure;
+    uint32_t privileged;
+};
+
 enum ethosu_error_codes
 {
     ETHOSU_SUCCESS         = 0,  ///< Success
diff --git a/src/ethosu_device.h b/src/ethosu_device.h
index 42d6d23..3567da4 100644
--- a/src/ethosu_device.h
+++ b/src/ethosu_device.h
@@ -31,30 +31,13 @@
 #endif
 
 /******************************************************************************
- * Types
- ******************************************************************************/
-struct NPU_REG; // Forward declare, to be implemented by each device
-
-struct ethosu_device
-{
-    volatile struct NPU_REG *reg; // Register map
-    uint32_t secure;
-    uint32_t privileged;
-};
-
-/******************************************************************************
  * Prototypes
  ******************************************************************************/
 
 /**
  * Initialize the device.
  */
-struct ethosu_device *ethosu_dev_init(void *const base_address, uint32_t secure_enable, uint32_t privilege_enable);
-
-/**
- * Deinitialize the device.
- */
-void ethosu_dev_deinit(struct ethosu_device *dev);
+bool ethosu_dev_init(struct ethosu_device *dev, void *base_address, uint32_t secure_enable, uint32_t privilege_enable);
 
 /**
  * Initialize AXI settings for device.
diff --git a/src/ethosu_device_u55_u65.c b/src/ethosu_device_u55_u65.c
index 50b78af..24e8949 100644
--- a/src/ethosu_device_u55_u65.c
+++ b/src/ethosu_device_u55_u65.c
@@ -1,6 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright 2019-2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
- *
+ * SPDX-FileCopyrightText: Copyright 2019-2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
  * SPDX-License-Identifier: Apache-2.0
  *
  * Licensed under the Apache License, Version 2.0 (the License); you may
@@ -67,15 +66,8 @@
     return address;
 }
 
-struct ethosu_device *ethosu_dev_init(void *const base_address, uint32_t secure_enable, uint32_t privilege_enable)
+bool ethosu_dev_init(struct ethosu_device *dev, void *base_address, uint32_t secure_enable, uint32_t privilege_enable)
 {
-    struct ethosu_device *dev = malloc(sizeof(struct ethosu_device));
-    if (!dev)
-    {
-        LOG_ERR("Failed to allocate memory for Ethos-U device");
-        return NULL;
-    }
-
     dev->reg        = (volatile struct NPU_REG *)base_address;
     dev->secure     = secure_enable;
     dev->privileged = privilege_enable;
@@ -87,25 +79,16 @@
 #endif
     {
         LOG_ERR("Failed to initialize device. Driver has not been compiled for this product");
-        goto err;
+        return false;
     }
 
     // Make sure the NPU is in a known state
     if (ethosu_dev_soft_reset(dev) != ETHOSU_SUCCESS)
     {
-        goto err;
+        return false;
     }
 
-    return dev;
-
-err:
-    free(dev);
-    return NULL;
-}
-
-void ethosu_dev_deinit(struct ethosu_device *dev)
-{
-    free(dev);
+    return true;
 }
 
 enum ethosu_error_codes ethosu_dev_axi_init(struct ethosu_device *dev)
diff --git a/src/ethosu_device_u85.c b/src/ethosu_device_u85.c
index 31f6a77..a5a70c7 100644
--- a/src/ethosu_device_u85.c
+++ b/src/ethosu_device_u85.c
@@ -55,15 +55,8 @@
     return address;
 }
 
-struct ethosu_device *ethosu_dev_init(void *const base_address, uint32_t secure_enable, uint32_t privilege_enable)
+bool ethosu_dev_init(struct ethosu_device *dev, void *base_address, uint32_t secure_enable, uint32_t privilege_enable)
 {
-    struct ethosu_device *dev = malloc(sizeof(struct ethosu_device));
-    if (!dev)
-    {
-        LOG_ERR("Failed to allocate memory for Ethos-U device");
-        return NULL;
-    }
-
     dev->reg        = (volatile struct NPU_REG *)base_address;
     dev->secure     = secure_enable;
     dev->privileged = privilege_enable;
@@ -71,25 +64,16 @@
     if (dev->reg->CONFIG.product != ETHOSU_PRODUCT_U85)
     {
         LOG_ERR("Failed to initialize device. Driver has not been compiled for this product");
-        goto err;
+        return false;
     }
 
     // Make sure the NPU is in a known state
     if (ethosu_dev_soft_reset(dev) != ETHOSU_SUCCESS)
     {
-        goto err;
+        return false;
     }
 
-    return dev;
-
-err:
-    free(dev);
-    return NULL;
-}
-
-void ethosu_dev_deinit(struct ethosu_device *dev)
-{
-    free(dev);
+    return true;
 }
 
 enum ethosu_error_codes ethosu_dev_axi_init(struct ethosu_device *dev)
diff --git a/src/ethosu_driver.c b/src/ethosu_driver.c
index 919fc11..4549458 100644
--- a/src/ethosu_driver.c
+++ b/src/ethosu_driver.c
@@ -258,7 +258,7 @@
 
     ethosu_semaphore_give(ethosu_semaphore);
 
-    LOG_INFO("New NPU driver registered (handle: 0x%p, NPU: 0x%p)", drv, drv->dev->reg);
+    LOG_INFO("New NPU driver registered (handle: 0x%p, NPU: 0x%p)", drv, drv->dev.reg);
 }
 
 static int ethosu_deregister_driver(struct ethosu_driver *drv)
@@ -304,7 +304,7 @@
 {
     LOG_INFO("Optimizer release nbr: %u patch: %u", opt_cfg_p->da_data.rel_nbr, opt_cfg_p->da_data.patch_nbr);
 
-    if (ethosu_dev_verify_optimizer_config(drv->dev, opt_cfg_p->cfg, opt_cfg_p->id) != true)
+    if (ethosu_dev_verify_optimizer_config(&drv->dev, opt_cfg_p->cfg, opt_cfg_p->id) != true)
     {
         return -1;
     }
@@ -366,7 +366,7 @@
     ethosu_inference_begin(drv, drv->job.user_arg);
 
     // Execute the command stream
-    ethosu_dev_run_command_stream(drv->dev, cmd_stream, cms_bytes, drv->job.base_addr, drv->job.num_base_addr);
+    ethosu_dev_run_command_stream(&drv->dev, cmd_stream, cms_bytes, drv->job.base_addr, drv->job.num_base_addr);
 
     return 0;
 }
@@ -386,7 +386,7 @@
     }
 
     drv->job.state  = ETHOSU_JOB_DONE;
-    drv->job.result = ethosu_dev_handle_interrupt(drv->dev) ? ETHOSU_JOB_RESULT_OK : ETHOSU_JOB_RESULT_ERROR;
+    drv->job.result = ethosu_dev_handle_interrupt(&drv->dev) ? ETHOSU_JOB_RESULT_OK : ETHOSU_JOB_RESULT_ERROR;
     ethosu_semaphore_give(drv->semaphore);
 }
 
@@ -434,9 +434,7 @@
     drv->power_request_counter = 0;
 
     // Initialize the device and set requested security state and privilege mode
-    drv->dev = ethosu_dev_init(base_address, secure_enable, privilege_enable);
-
-    if (drv->dev == NULL)
+    if (!ethosu_dev_init(&drv->dev, base_address, secure_enable, privilege_enable))
     {
         LOG_ERR("Failed to initialize Ethos-U device");
         return -1;
@@ -446,8 +444,6 @@
     if (!drv->semaphore)
     {
         LOG_ERR("Failed to create driver semaphore");
-        ethosu_dev_deinit(drv->dev);
-        drv->dev = NULL;
         return -1;
     }
 
@@ -461,21 +457,19 @@
 {
     ethosu_deregister_driver(drv);
     ethosu_semaphore_destroy(drv->semaphore);
-    ethosu_dev_deinit(drv->dev);
-    drv->dev = NULL;
 }
 
 int ethosu_soft_reset(struct ethosu_driver *drv)
 {
     // Soft reset the NPU
-    if (ethosu_dev_soft_reset(drv->dev) != ETHOSU_SUCCESS)
+    if (ethosu_dev_soft_reset(&drv->dev) != ETHOSU_SUCCESS)
     {
         LOG_ERR("Failed to soft-reset NPU");
         return -1;
     }
 
     // Update power and clock gating after the soft reset
-    ethosu_dev_set_clock_and_power(drv->dev,
+    ethosu_dev_set_clock_and_power(&drv->dev,
                                    drv->power_request_counter > 0 ? ETHOSU_CLOCK_Q_DISABLE : ETHOSU_CLOCK_Q_ENABLE,
                                    drv->power_request_counter > 0 ? ETHOSU_POWER_Q_DISABLE : ETHOSU_POWER_Q_ENABLE);
 
@@ -510,7 +504,7 @@
         // Decrement ref counter and enable power gating if no requests remain
         if (--drv->power_request_counter == 0)
         {
-            ethosu_dev_set_clock_and_power(drv->dev, ETHOSU_CLOCK_Q_ENABLE, ETHOSU_POWER_Q_ENABLE);
+            ethosu_dev_set_clock_and_power(&drv->dev, ETHOSU_CLOCK_Q_ENABLE, ETHOSU_POWER_Q_ENABLE);
         }
     }
 }
@@ -526,7 +520,7 @@
 void ethosu_get_hw_info(struct ethosu_driver *drv, struct ethosu_hw_info *hw)
 {
     assert(hw != NULL);
-    ethosu_dev_get_hw_info(drv->dev, hw);
+    ethosu_dev_get_hw_info(&drv->dev, hw);
 }
 
 int ethosu_wait(struct ethosu_driver *drv, bool block)
@@ -579,7 +573,7 @@
             if (drv->job.result == ETHOSU_JOB_RESULT_ERROR)
             {
                 LOG_ERR("NPU error(s) occured during inference.");
-                ethosu_dev_print_err_status(drv->dev);
+                ethosu_dev_print_err_status(&drv->dev);
             }
             else
             {
diff --git a/src/ethosu_pmu.c b/src/ethosu_pmu.c
index 0b58c6f..2681c0e 100644
--- a/src/ethosu_pmu.c
+++ b/src/ethosu_pmu.c
@@ -88,13 +88,13 @@
     struct pmcr_r pmcr = {0};
     pmcr.cnt_en        = 1;
     ethosu_request_power(drv);
-    drv->dev->reg->PMCR.word = pmcr.word;
+    drv->dev.reg->PMCR.word = pmcr.word;
 }
 
 void ETHOSU_PMU_Disable(struct ethosu_driver *drv)
 {
     LOG_DEBUG("Disable PMU");
-    drv->dev->reg->PMCR.word = 0;
+    drv->dev.reg->PMCR.word = 0;
     ethosu_release_power(drv);
 }
 
@@ -114,13 +114,13 @@
     }
 
     LOG_DEBUG("num=%" PRIu32 ", type=%d, val=%" PRIu32, num, type, val);
-    drv->dev->reg->PMEVTYPER[num].word = val;
+    drv->dev.reg->PMEVTYPER[num].word = val;
 }
 
 enum ethosu_pmu_event_type ETHOSU_PMU_Get_EVTYPER(struct ethosu_driver *drv, uint32_t num)
 {
     assert(num < ETHOSU_PMU_NCOUNTERS);
-    uint32_t val                    = drv->dev->reg->PMEVTYPER[num].word;
+    uint32_t val                    = drv->dev.reg->PMEVTYPER[num].word;
     enum ethosu_pmu_event_type type = pmu_event_type(val);
     LOG_DEBUG("num=%" PRIu32 ", type=%d, val=%" PRIu32, num, type, val);
     return type;
@@ -130,43 +130,43 @@
 {
     LOG_DEBUG("Reset PMU cycle counter");
     struct pmcr_r pmcr;
-    pmcr.word                = drv->dev->reg->PMCR.word;
-    pmcr.cycle_cnt_rst       = 1;
-    drv->dev->reg->PMCR.word = pmcr.word;
+    pmcr.word               = drv->dev.reg->PMCR.word;
+    pmcr.cycle_cnt_rst      = 1;
+    drv->dev.reg->PMCR.word = pmcr.word;
 }
 
 void ETHOSU_PMU_EVCNTR_ALL_Reset(struct ethosu_driver *drv)
 {
     LOG_DEBUG("Reset all events");
     struct pmcr_r pmcr;
-    pmcr.word                = drv->dev->reg->PMCR.word;
-    pmcr.event_cnt_rst       = 1;
-    drv->dev->reg->PMCR.word = pmcr.word;
+    pmcr.word               = drv->dev.reg->PMCR.word;
+    pmcr.event_cnt_rst      = 1;
+    drv->dev.reg->PMCR.word = pmcr.word;
 }
 
 void ETHOSU_PMU_CNTR_Enable(struct ethosu_driver *drv, uint32_t mask)
 {
     LOG_DEBUG("mask=0x%08" PRIx32, mask);
-    drv->dev->reg->PMCNTENSET.word = mask;
+    drv->dev.reg->PMCNTENSET.word = mask;
 }
 
 void ETHOSU_PMU_CNTR_Disable(struct ethosu_driver *drv, uint32_t mask)
 {
     LOG_DEBUG("mask=0x%08" PRIx32, mask);
-    drv->dev->reg->PMCNTENCLR.word = mask;
+    drv->dev.reg->PMCNTENCLR.word = mask;
 }
 
 uint32_t ETHOSU_PMU_CNTR_Status(struct ethosu_driver *drv)
 {
-    uint32_t pmcntenset = drv->dev->reg->PMCNTENSET.word;
+    uint32_t pmcntenset = drv->dev.reg->PMCNTENSET.word;
     LOG_DEBUG("mask=0x%08" PRIx32, pmcntenset);
     return pmcntenset;
 }
 
 uint64_t ETHOSU_PMU_Get_CCNTR(struct ethosu_driver *drv)
 {
-    uint32_t val_lo = drv->dev->reg->PMCCNTR.CYCLE_CNT_LO;
-    uint32_t val_hi = drv->dev->reg->PMCCNTR.CYCLE_CNT_HI;
+    uint32_t val_lo = drv->dev.reg->PMCCNTR.CYCLE_CNT_LO;
+    uint32_t val_hi = drv->dev.reg->PMCCNTR.CYCLE_CNT_HI;
     uint64_t val    = ((uint64_t)val_hi << 32) | val_lo;
 
     LOG_DEBUG("val=%" PRIu64, val);
@@ -184,8 +184,8 @@
         ETHOSU_PMU_CNTR_Disable(drv, ETHOSU_PMU_CCNT_Msk);
     }
 
-    drv->dev->reg->PMCCNTR.CYCLE_CNT_LO = val & MASK_0_31_BITS;
-    drv->dev->reg->PMCCNTR.CYCLE_CNT_HI = (val & MASK_32_47_BITS) >> 32;
+    drv->dev.reg->PMCCNTR.CYCLE_CNT_LO = val & MASK_0_31_BITS;
+    drv->dev.reg->PMCCNTR.CYCLE_CNT_HI = (val & MASK_32_47_BITS) >> 32;
 
     if (active)
     {
@@ -196,7 +196,7 @@
 uint32_t ETHOSU_PMU_Get_EVCNTR(struct ethosu_driver *drv, uint32_t num)
 {
     assert(num < ETHOSU_PMU_NCOUNTERS);
-    uint32_t val = drv->dev->reg->PMEVCNTR[num].word;
+    uint32_t val = drv->dev.reg->PMEVCNTR[num].word;
     LOG_DEBUG("num=%" PRIu32 ", val=%" PRIu32, num, val);
 
     return val;
@@ -206,36 +206,36 @@
 {
     assert(num < ETHOSU_PMU_NCOUNTERS);
     LOG_DEBUG("num=%" PRIu32 ", val=%" PRIu32, num, val);
-    drv->dev->reg->PMEVCNTR[num].word = val;
+    drv->dev.reg->PMEVCNTR[num].word = val;
 }
 
 uint32_t ETHOSU_PMU_Get_CNTR_OVS(struct ethosu_driver *drv)
 {
     LOG_DEBUG("");
-    return drv->dev->reg->PMOVSSET.word;
+    return drv->dev.reg->PMOVSSET.word;
 }
 
 void ETHOSU_PMU_Set_CNTR_OVS(struct ethosu_driver *drv, uint32_t mask)
 {
     LOG_DEBUG("");
-    drv->dev->reg->PMOVSCLR.word = mask;
+    drv->dev.reg->PMOVSCLR.word = mask;
 }
 
 void ETHOSU_PMU_Set_CNTR_IRQ_Enable(struct ethosu_driver *drv, uint32_t mask)
 {
     LOG_DEBUG("mask=0x%08" PRIx32, mask);
-    drv->dev->reg->PMINTSET.word = mask;
+    drv->dev.reg->PMINTSET.word = mask;
 }
 
 void ETHOSU_PMU_Set_CNTR_IRQ_Disable(struct ethosu_driver *drv, uint32_t mask)
 {
     LOG_DEBUG("mask=0x%08" PRIx32, mask);
-    drv->dev->reg->PMINTCLR.word = mask;
+    drv->dev.reg->PMINTCLR.word = mask;
 }
 
 uint32_t ETHOSU_PMU_Get_IRQ_Enable(struct ethosu_driver *drv)
 {
-    uint32_t pmint = drv->dev->reg->PMINTSET.word;
+    uint32_t pmint = drv->dev.reg->PMINTSET.word;
     LOG_DEBUG("mask=0x%08" PRIx32, pmint);
     return pmint;
 }
@@ -251,17 +251,17 @@
     // Increment cycle counter
     if (mask & ETHOSU_PMU_CCNT_Msk)
     {
-        uint64_t val                        = ETHOSU_PMU_Get_CCNTR(drv) + 1;
-        drv->dev->reg->PMCCNTR.CYCLE_CNT_LO = val & MASK_0_31_BITS;
-        drv->dev->reg->PMCCNTR.CYCLE_CNT_HI = (val & MASK_32_47_BITS) >> 32;
+        uint64_t val                       = ETHOSU_PMU_Get_CCNTR(drv) + 1;
+        drv->dev.reg->PMCCNTR.CYCLE_CNT_LO = val & MASK_0_31_BITS;
+        drv->dev.reg->PMCCNTR.CYCLE_CNT_HI = (val & MASK_32_47_BITS) >> 32;
     }
 
     for (int i = 0; i < ETHOSU_PMU_NCOUNTERS; i++)
     {
         if (mask & (1u << i))
         {
-            uint32_t val                    = ETHOSU_PMU_Get_EVCNTR(drv, i);
-            drv->dev->reg->PMEVCNTR[i].word = val + 1;
+            uint32_t val                   = ETHOSU_PMU_Get_EVCNTR(drv, i);
+            drv->dev.reg->PMEVCNTR[i].word = val + 1;
         }
     }
 
@@ -280,9 +280,9 @@
         return;
     }
 
-    cfg.word                        = drv->dev->reg->PMCCNTR_CFG.word;
-    cfg.CYCLE_CNT_CFG_START         = val;
-    drv->dev->reg->PMCCNTR_CFG.word = cfg.word;
+    cfg.word                       = drv->dev.reg->PMCCNTR_CFG.word;
+    cfg.CYCLE_CNT_CFG_START        = val;
+    drv->dev.reg->PMCCNTR_CFG.word = cfg.word;
 }
 
 void ETHOSU_PMU_PMCCNTR_CFG_Set_Stop_Event(struct ethosu_driver *drv, enum ethosu_pmu_event_type stop_event)
@@ -296,21 +296,21 @@
         return;
     }
 
-    cfg.word                        = drv->dev->reg->PMCCNTR_CFG.word;
-    cfg.CYCLE_CNT_CFG_STOP          = val;
-    drv->dev->reg->PMCCNTR_CFG.word = cfg.word;
+    cfg.word                       = drv->dev.reg->PMCCNTR_CFG.word;
+    cfg.CYCLE_CNT_CFG_STOP         = val;
+    drv->dev.reg->PMCCNTR_CFG.word = cfg.word;
 }
 
 uint32_t ETHOSU_PMU_Get_QREAD(struct ethosu_driver *drv)
 {
-    uint32_t val = drv->dev->reg->QREAD.word;
+    uint32_t val = drv->dev.reg->QREAD.word;
     LOG_DEBUG("qread=%" PRIu32, val);
     return val;
 }
 
 uint32_t ETHOSU_PMU_Get_STATUS(struct ethosu_driver *drv)
 {
-    uint32_t val = drv->dev->reg->STATUS.word;
+    uint32_t val = drv->dev.reg->STATUS.word;
     LOG_DEBUG("status=0x%" PRIx32, val);
     return val;
 }