Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2019-2020 Arm Limited. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: Apache-2.0 |
| 5 | * |
| 6 | * Licensed under the Apache License, Version 2.0 (the License); you may |
| 7 | * not use this file except in compliance with the License. |
| 8 | * You may obtain a copy of the License at |
| 9 | * |
| 10 | * www.apache.org/licenses/LICENSE-2.0 |
| 11 | * |
| 12 | * Unless required by applicable law or agreed to in writing, software |
| 13 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT |
| 14 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 15 | * See the License for the specific language governing permissions and |
| 16 | * limitations under the License. |
| 17 | */ |
| 18 | |
| 19 | #if defined(__ICCARM__) |
| 20 | #pragma system_include /* treat file as system include file for MISRA check */ |
| 21 | #elif defined(__clang__) |
| 22 | #pragma clang system_header /* treat file as system include file */ |
| 23 | #endif |
| 24 | |
| 25 | #ifndef PMU_ETHOSU_H |
| 26 | #define PMU_ETHOSU_H |
| 27 | |
| 28 | #define ETHOSU_PMU_NCOUNTERS 4 |
| 29 | |
| 30 | #include <cmsis_compiler.h> |
| 31 | |
| 32 | #ifdef NOTNOW |
| 33 | #if defined(CPU_CORTEX_M55) |
| 34 | #include <core_cm55.h> |
| 35 | #elif defined(CPU_CORTEX_M33) |
| 36 | #include <core_cm33.h> |
| 37 | #else |
| 38 | #error npu-pmu not supported for CPU |
| 39 | #endif |
| 40 | #else |
| 41 | /* IO definitions (access restrictions to peripheral registers) */ |
| 42 | /** |
| 43 | \defgroup CMSIS_glob_defs CMSIS Global Defines |
| 44 | |
| 45 | <strong>IO Type Qualifiers</strong> are used |
| 46 | \li to specify the access to peripheral variables. |
| 47 | \li for automatic generation of peripheral register debug information. |
| 48 | */ |
| 49 | #ifdef __cplusplus |
| 50 | #define __I volatile /*!< Defines 'read only' permissions */ |
| 51 | #else |
| 52 | #define __I volatile const /*!< Defines 'read only' permissions */ |
| 53 | #endif |
| 54 | #define __O volatile /*!< Defines 'write only' permissions */ |
| 55 | #define __IO volatile /*!< Defines 'read / write' permissions */ |
| 56 | |
| 57 | /* following defines should be used for structure members */ |
| 58 | #define __IM volatile const /*! Defines 'read only' structure member permissions */ |
| 59 | #define __OM volatile /*! Defines 'write only' structure member permissions */ |
| 60 | #define __IOM volatile /*! Defines 'read / write' structure member permissions */ |
| 61 | #endif |
| 62 | |
| 63 | typedef struct |
| 64 | { |
| 65 | __IOM uint32_t PMCR; |
| 66 | __IOM uint32_t PMCNTENSET; |
| 67 | __IOM uint32_t PMCNTENCLR; |
| 68 | __IOM uint32_t PMOVSSET; |
| 69 | __IOM uint32_t PMOVSCLR; |
| 70 | __IOM uint32_t PMINTSET; |
| 71 | __IOM uint32_t PMINTCLR; |
| 72 | __IOM uint64_t PMCCNTR; |
| 73 | __IOM uint32_t PMCCNTR_CFG; |
| 74 | } PMU_Ethosu_ctrl_Type; |
| 75 | |
| 76 | typedef uint32_t PMU_Ethosu_cntr_Type[ETHOSU_PMU_NCOUNTERS]; |
| 77 | typedef uint32_t PMU_Ethosu_evnt_Type[ETHOSU_PMU_NCOUNTERS]; |
| 78 | |
| 79 | /** \brief HW Supported ETHOSU PMU Events |
| 80 | * |
| 81 | * Note: These values are symbolic. Actual HW-values may change. I.e. always use API |
| 82 | * to set/get actual event-type value. |
| 83 | * */ |
| 84 | enum ethosu_pmu_event_type |
| 85 | { |
| 86 | ETHOSU_PMU_CYCLE = 0, |
| 87 | ETHOSU_PMU_NPU_IDLE, |
| 88 | ETHOSU_PMU_MAC_ACTIVE, |
| 89 | ETHOSU_PMU_MAC_ACTIVE_8BIT, |
| 90 | ETHOSU_PMU_MAC_ACTIVE_16BIT, |
| 91 | ETHOSU_PMU_MAC_DPU_ACTIVE, |
| 92 | ETHOSU_PMU_MAC_STALLED_BY_WD_ACC, |
| 93 | ETHOSU_PMU_MAC_STALLED_BY_WD, |
| 94 | ETHOSU_PMU_MAC_STALLED_BY_ACC, |
| 95 | ETHOSU_PMU_MAC_STALLED_BY_IB, |
| 96 | ETHOSU_PMU_AO_ACTIVE, |
| 97 | ETHOSU_PMU_AO_ACTIVE_8BIT, |
| 98 | ETHOSU_PMU_AO_ACTIVE_16BIT, |
| 99 | ETHOSU_PMU_AO_STALLED_BY_OFMP_OB, |
| 100 | ETHOSU_PMU_AO_STALLED_BY_OFMP, |
| 101 | ETHOSU_PMU_AO_STALLED_BY_OB, |
| 102 | ETHOSU_PMU_AO_STALLED_BY_ACC_IB, |
| 103 | ETHOSU_PMU_AO_STALLED_BY_ACC, |
| 104 | ETHOSU_PMU_AO_STALLED_BY_IB, |
| 105 | ETHOSU_PMU_WD_ACTIVE, |
| 106 | ETHOSU_PMU_WD_STALLED, |
| 107 | ETHOSU_PMU_WD_STALLED_BY_WS, |
| 108 | ETHOSU_PMU_WD_STALLED_BY_WD_BUF, |
| 109 | ETHOSU_PMU_WD_PARSE_ACTIVE, |
| 110 | ETHOSU_PMU_WD_PARSE_STALLED, |
| 111 | ETHOSU_PMU_WD_PARSE_STALLED_IN, |
| 112 | ETHOSU_PMU_WD_PARSE_STALLED_OUT, |
| 113 | ETHOSU_PMU_AXI0_RD_TRANS_ACCEPTED, |
| 114 | ETHOSU_PMU_AXI0_RD_TRANS_COMPLETED, |
| 115 | ETHOSU_PMU_AXI0_RD_DATA_BEAT_RECEIVED, |
| 116 | ETHOSU_PMU_AXI0_RD_TRAN_REQ_STALLED, |
| 117 | ETHOSU_PMU_AXI0_WR_TRANS_ACCEPTED, |
| 118 | ETHOSU_PMU_AXI0_WR_TRANS_COMPLETED_M, |
| 119 | ETHOSU_PMU_AXI0_WR_TRANS_COMPLETED_S, |
| 120 | ETHOSU_PMU_AXI0_WR_DATA_BEAT_WRITTEN, |
| 121 | ETHOSU_PMU_AXI0_WR_TRAN_REQ_STALLED, |
| 122 | ETHOSU_PMU_AXI0_WR_DATA_BEAT_STALLED, |
| 123 | ETHOSU_PMU_AXI0_ENABLED_CYCLES, |
| 124 | ETHOSU_PMU_AXI0_RD_STALL_LIMIT, |
| 125 | ETHOSU_PMU_AXI0_WR_STALL_LIMIT, |
| 126 | ETHOSU_PMU_AXI1_RD_TRANS_ACCEPTED, |
| 127 | ETHOSU_PMU_AXI1_RD_TRANS_COMPLETED, |
| 128 | ETHOSU_PMU_AXI1_RD_DATA_BEAT_RECEIVED, |
| 129 | ETHOSU_PMU_AXI1_RD_TRAN_REQ_STALLED, |
| 130 | ETHOSU_PMU_AXI1_WR_TRANS_ACCEPTED, |
| 131 | ETHOSU_PMU_AXI1_WR_TRANS_COMPLETED_M, |
| 132 | ETHOSU_PMU_AXI1_WR_TRANS_COMPLETED_S, |
| 133 | ETHOSU_PMU_AXI1_WR_DATA_BEAT_WRITTEN, |
| 134 | ETHOSU_PMU_AXI1_WR_TRAN_REQ_STALLED, |
| 135 | ETHOSU_PMU_AXI1_WR_DATA_BEAT_STALLED, |
| 136 | ETHOSU_PMU_AXI1_ENABLED_CYCLES, |
| 137 | ETHOSU_PMU_AXI1_RD_STALL_LIMIT, |
| 138 | ETHOSU_PMU_AXI1_WR_STALL_LIMIT, |
| 139 | ETHOSU_PMU_AXI_LATENCY_ANY, |
| 140 | ETHOSU_PMU_AXI_LATENCY_32, |
| 141 | ETHOSU_PMU_AXI_LATENCY_64, |
| 142 | ETHOSU_PMU_AXI_LATENCY_128, |
| 143 | ETHOSU_PMU_AXI_LATENCY_256, |
| 144 | ETHOSU_PMU_AXI_LATENCY_512, |
| 145 | ETHOSU_PMU_AXI_LATENCY_1024, |
| 146 | |
| 147 | ETHOSU_PMU_SENTINEL // End-marker (not event) |
| 148 | }; |
| 149 | |
| 150 | extern PMU_Ethosu_ctrl_Type *ethosu_pmu_ctrl; |
| 151 | extern PMU_Ethosu_cntr_Type *ethosu_pmu_cntr; |
| 152 | extern PMU_Ethosu_evnt_Type *ethosu_pmu_evnt; |
| 153 | |
| 154 | #define ETHOSU_PMU_CTRL_ENABLE_Msk (0x0001) |
| 155 | #define ETHOSU_PMU_CTRL_EVENTCNT_RESET_Msk (0x0002) |
| 156 | #define ETHOSU_PMU_CTRL_CYCCNT_RESET_Msk (0x0004) |
| 157 | #define ETHOSU_PMU_CNT1_Msk (1UL << 0) |
| 158 | #define ETHOSU_PMU_CNT2_Msk (1UL << 1) |
| 159 | #define ETHOSU_PMU_CNT3_Msk (1UL << 2) |
| 160 | #define ETHOSU_PMU_CNT4_Msk (1UL << 3) |
| 161 | #define ETHOSU_PMU_CCNT_Msk (1UL << 31) |
| 162 | |
| 163 | /* Transpose functions between HW-event-type and event-id*/ |
| 164 | enum ethosu_pmu_event_type pmu_event_type(uint32_t); |
| 165 | uint32_t pmu_event_value(enum ethosu_pmu_event_type); |
| 166 | |
| 167 | // CMSIS ref API |
| 168 | /** \brief PMU Functions */ |
| 169 | |
| 170 | __STATIC_INLINE void ETHOSU_PMU_Enable(void); |
| 171 | __STATIC_INLINE void ETHOSU_PMU_Disable(void); |
| 172 | |
| 173 | __STATIC_INLINE void ETHOSU_PMU_Set_EVTYPER(uint32_t num, enum ethosu_pmu_event_type type); |
| 174 | __STATIC_INLINE enum ethosu_pmu_event_type ETHOSU_PMU_Get_EVTYPER(uint32_t num); |
| 175 | |
| 176 | __STATIC_INLINE void ETHOSU_PMU_CYCCNT_Reset(void); |
| 177 | __STATIC_INLINE void ETHOSU_PMU_EVCNTR_ALL_Reset(void); |
| 178 | |
| 179 | __STATIC_INLINE void ETHOSU_PMU_CNTR_Enable(uint32_t mask); |
| 180 | __STATIC_INLINE void ETHOSU_PMU_CNTR_Disable(uint32_t mask); |
| 181 | __STATIC_INLINE uint32_t ETHOSU_PMU_CNTR_Status(); |
| 182 | |
| 183 | __STATIC_INLINE uint64_t ETHOSU_PMU_Get_CCNTR(void); |
| 184 | __STATIC_INLINE void ETHOSU_PMU_Set_CCNTR(uint64_t val); |
| 185 | __STATIC_INLINE uint32_t ETHOSU_PMU_Get_EVCNTR(uint32_t num); |
| 186 | __STATIC_INLINE void ETHOSU_PMU_Set_EVCNTR(uint32_t num, uint32_t val); |
| 187 | |
| 188 | __STATIC_INLINE uint32_t ETHOSU_PMU_Get_CNTR_OVS(void); |
| 189 | __STATIC_INLINE void ETHOSU_PMU_Set_CNTR_OVS(uint32_t mask); |
| 190 | |
| 191 | __STATIC_INLINE void ETHOSU_PMU_Set_CNTR_IRQ_Enable(uint32_t mask); |
| 192 | __STATIC_INLINE void ETHOSU_PMU_Set_CNTR_IRQ_Disable(uint32_t mask); |
| 193 | __STATIC_INLINE uint32_t ETHOSU_PMU_Get_IRQ_Enable(); |
| 194 | |
| 195 | __STATIC_INLINE void ETHOSU_PMU_CNTR_Increment(uint32_t mask); |
| 196 | |
| 197 | /** |
| 198 | \brief Enable the PMU |
| 199 | */ |
| 200 | __STATIC_INLINE void ETHOSU_PMU_Enable(void) |
| 201 | { |
| 202 | ethosu_pmu_ctrl->PMCR |= ETHOSU_PMU_CTRL_ENABLE_Msk; |
| 203 | } |
| 204 | |
| 205 | /** |
| 206 | \brief Disable the PMU |
| 207 | */ |
| 208 | __STATIC_INLINE void ETHOSU_PMU_Disable(void) |
| 209 | { |
| 210 | ethosu_pmu_ctrl->PMCR &= ~ETHOSU_PMU_CTRL_ENABLE_Msk; |
| 211 | } |
| 212 | |
| 213 | /** |
| 214 | \brief Set event to count for PMU eventer counter |
| 215 | \param [in] num Event counter (0-ETHOSU_PMU_NCOUNTERS) to configure |
| 216 | \param [in] type Event to count |
| 217 | */ |
| 218 | __STATIC_INLINE void ETHOSU_PMU_Set_EVTYPER(uint32_t num, enum ethosu_pmu_event_type type) |
| 219 | { |
| 220 | (*ethosu_pmu_evnt)[num] = pmu_event_value(type); |
| 221 | } |
| 222 | |
| 223 | /** |
| 224 | \brief Get event to count for PMU eventer counter |
| 225 | \param [in] num Event counter (0-ETHOSU_PMU_NCOUNTERS) to configure |
| 226 | \return type Event to count |
| 227 | */ |
| 228 | __STATIC_INLINE enum ethosu_pmu_event_type ETHOSU_PMU_Get_EVTYPER(uint32_t num) |
| 229 | { |
| 230 | return pmu_event_type((*ethosu_pmu_evnt)[num]); |
| 231 | } |
| 232 | |
| 233 | /** |
| 234 | \brief Reset cycle counter |
| 235 | */ |
| 236 | __STATIC_INLINE void ETHOSU_PMU_CYCCNT_Reset(void) |
| 237 | { |
| 238 | ethosu_pmu_ctrl->PMCR |= ETHOSU_PMU_CTRL_CYCCNT_RESET_Msk; |
| 239 | } |
| 240 | |
| 241 | /** |
| 242 | \brief Reset all event counters |
| 243 | */ |
| 244 | __STATIC_INLINE void ETHOSU_PMU_EVCNTR_ALL_Reset(void) |
| 245 | { |
| 246 | ethosu_pmu_ctrl->PMCR |= ETHOSU_PMU_CTRL_EVENTCNT_RESET_Msk; |
| 247 | } |
| 248 | |
| 249 | /** |
| 250 | \brief Enable counters |
| 251 | \param [in] mask Counters to enable |
| 252 | \note Enables one or more of the following: |
| 253 | - event counters (bit 0-ETHOSU_PMU_NCOUNTERS) |
| 254 | - cycle counter (bit 31) |
| 255 | */ |
| 256 | __STATIC_INLINE void ETHOSU_PMU_CNTR_Enable(uint32_t mask) |
| 257 | { |
| 258 | ethosu_pmu_ctrl->PMCNTENSET = mask; |
| 259 | } |
| 260 | |
| 261 | /** |
| 262 | \brief Disable counters |
| 263 | \param [in] mask Counters to disable |
| 264 | \note Disables one or more of the following: |
| 265 | - event counters (bit 0-ETHOSU_PMU_NCOUNTERS) |
| 266 | - cycle counter (bit 31) |
| 267 | */ |
| 268 | __STATIC_INLINE void ETHOSU_PMU_CNTR_Disable(uint32_t mask) |
| 269 | { |
| 270 | ethosu_pmu_ctrl->PMCNTENCLR = mask; |
| 271 | } |
| 272 | |
| 273 | /** |
| 274 | \brief Determine counters activation |
| 275 | |
| 276 | \return Event count |
| 277 | \param [in] mask Counters to enable |
| 278 | \return a bitmask where bit-set means: |
| 279 | - event counters activated (bit 0-ETHOSU_PMU_NCOUNTERS) |
| 280 | - cycle counter activate (bit 31) |
| 281 | \note ETHOSU specific. Usage breaks CMSIS complience |
| 282 | */ |
| 283 | __STATIC_INLINE uint32_t ETHOSU_PMU_CNTR_Status() |
| 284 | { |
| 285 | return ethosu_pmu_ctrl->PMCNTENSET; |
| 286 | } |
| 287 | |
| 288 | /** |
| 289 | \brief Read cycle counter (64 bit) |
| 290 | \return Cycle count |
| 291 | \note Two HW 32-bit registers that can increment independently in-between reads. |
| 292 | To work-around raciness yet still avoid turning |
| 293 | off the event both are read as one value twice. If the latter read |
| 294 | is not greater than the former, it means overflow of LSW without |
| 295 | incrementing MSW has occurred, in which case the former value is used. |
| 296 | */ |
| 297 | __STATIC_INLINE uint64_t ETHOSU_PMU_Get_CCNTR(void) |
| 298 | { |
| 299 | uint64_t val1 = ethosu_pmu_ctrl->PMCCNTR; |
| 300 | uint64_t val2 = ethosu_pmu_ctrl->PMCCNTR; |
| 301 | |
| 302 | if (val2 > val1) |
| 303 | { |
| 304 | return val2; |
| 305 | } |
| 306 | return val1; |
| 307 | } |
| 308 | |
| 309 | /** |
| 310 | \brief Set cycle counter (64 bit) |
| 311 | \param [in] val Conter value |
| 312 | \note Two HW 32-bit registers that can increment independently in-between reads. |
| 313 | To work-around raciness, counter is temporary disabled if enabled. |
| 314 | \note ETHOSU specific. Usage breaks CMSIS complience |
| 315 | */ |
| 316 | __STATIC_INLINE void ETHOSU_PMU_Set_CCNTR(uint64_t val) |
| 317 | { |
| 318 | uint32_t mask = ETHOSU_PMU_CNTR_Status(); |
| 319 | |
| 320 | if (mask & ETHOSU_PMU_CCNT_Msk) |
| 321 | { |
| 322 | ETHOSU_PMU_CNTR_Disable(ETHOSU_PMU_CCNT_Msk); |
| 323 | } |
| 324 | |
| 325 | ethosu_pmu_ctrl->PMCCNTR = val; |
| 326 | |
| 327 | if (mask & ETHOSU_PMU_CCNT_Msk) |
| 328 | { |
| 329 | ETHOSU_PMU_CNTR_Enable(ETHOSU_PMU_CCNT_Msk); |
| 330 | } |
| 331 | } |
| 332 | |
| 333 | /** |
| 334 | \brief Read event counter |
| 335 | \param [in] num Event counter (0-ETHOSU_PMU_NCOUNTERS) |
| 336 | \return Event count |
| 337 | */ |
| 338 | __STATIC_INLINE uint32_t ETHOSU_PMU_Get_EVCNTR(uint32_t num) |
| 339 | { |
| 340 | return (*ethosu_pmu_cntr)[num]; |
| 341 | } |
| 342 | |
| 343 | /** |
| 344 | \brief Set event counter value |
| 345 | \param [in] num Event counter (0-ETHOSU_PMU_NCOUNTERS) |
| 346 | \param [in] val Conter value |
| 347 | \note ETHOSU specific. Usage breaks CMSIS complience |
| 348 | */ |
| 349 | __STATIC_INLINE void ETHOSU_PMU_Set_EVCNTR(uint32_t num, uint32_t val) |
| 350 | { |
| 351 | (*ethosu_pmu_cntr)[num] = val; |
| 352 | } |
| 353 | /** |
| 354 | \brief Read counter overflow status |
| 355 | \return Counter overflow status bits for the following: |
| 356 | - event counters (bit 0-ETHOSU_PMU_NCOUNTERS)) |
| 357 | - cycle counter (bit 31) |
| 358 | */ |
| 359 | __STATIC_INLINE uint32_t ETHOSU_PMU_Get_CNTR_OVS(void) |
| 360 | { |
| 361 | return ethosu_pmu_ctrl->PMOVSSET; |
| 362 | } |
| 363 | |
| 364 | /** |
| 365 | \brief Clear counter overflow status |
| 366 | \param [in] mask Counter overflow status bits to clear |
| 367 | \note Clears overflow status bits for one or more of the following: |
| 368 | - event counters (bit 0-ETHOSU_PMU_NCOUNTERS) |
| 369 | - cycle counter (bit 31) |
| 370 | */ |
| 371 | __STATIC_INLINE void ETHOSU_PMU_Set_CNTR_OVS(uint32_t mask) |
| 372 | { |
| 373 | ethosu_pmu_ctrl->PMOVSCLR = mask; |
| 374 | } |
| 375 | |
| 376 | /** |
| 377 | \brief Enable counter overflow interrupt request |
| 378 | \param [in] mask Counter overflow interrupt request bits to set |
| 379 | \note Sets overflow interrupt request bits for one or more of the following: |
| 380 | - event counters (bit 0-ETHOSU_PMU_NCOUNTERS) |
| 381 | - cycle counter (bit 31) |
| 382 | */ |
| 383 | __STATIC_INLINE void ETHOSU_PMU_Set_CNTR_IRQ_Enable(uint32_t mask) |
| 384 | { |
| 385 | ethosu_pmu_ctrl->PMINTSET = mask; |
| 386 | } |
| 387 | |
| 388 | /** |
| 389 | \brief Disable counter overflow interrupt request |
| 390 | \param [in] mask Counter overflow interrupt request bits to clear |
| 391 | \note Clears overflow interrupt request bits for one or more of the following: |
| 392 | - event counters (bit 0-ETHOSU_PMU_NCOUNTERS) |
| 393 | - cycle counter (bit 31) |
| 394 | */ |
| 395 | __STATIC_INLINE void ETHOSU_PMU_Set_CNTR_IRQ_Disable(uint32_t mask) |
| 396 | { |
| 397 | ethosu_pmu_ctrl->PMINTCLR = mask; |
| 398 | } |
| 399 | |
| 400 | /** |
| 401 | \brief Get counters overflow interrupt request stiinings |
| 402 | \return mask Counter overflow interrupt request bits |
| 403 | \note Sets overflow interrupt request bits for one or more of the following: |
| 404 | - event counters (bit 0-ETHOSU_PMU_NCOUNTERS) |
| 405 | - cycle counter (bit 31) |
| 406 | \note ETHOSU specific. Usage breaks CMSIS complience |
| 407 | */ |
| 408 | __STATIC_INLINE uint32_t ETHOSU_PMU_Get_IRQ_Enable() |
| 409 | { |
| 410 | return ethosu_pmu_ctrl->PMINTSET; |
| 411 | } |
| 412 | |
| 413 | /** |
| 414 | \brief Software increment event counter |
| 415 | \param [in] mask Counters to increment |
| 416 | - event counters (bit 0-ETHOSU_PMU_NCOUNTERS) |
| 417 | - cycle counter (bit 31) |
| 418 | \note Software increment bits for one or more event counters. |
| 419 | */ |
| 420 | __STATIC_INLINE void ETHOSU_PMU_CNTR_Increment(uint32_t mask) |
| 421 | { |
| 422 | uint32_t cntrs_active = ETHOSU_PMU_CNTR_Status(); |
| 423 | |
| 424 | if (mask & ETHOSU_PMU_CCNT_Msk) |
| 425 | { |
| 426 | if (mask & ETHOSU_PMU_CCNT_Msk) |
| 427 | { |
| 428 | ETHOSU_PMU_CNTR_Disable(ETHOSU_PMU_CCNT_Msk); |
| 429 | ethosu_pmu_ctrl->PMCCNTR = ETHOSU_PMU_Get_CCNTR() + 1; |
| 430 | if (cntrs_active & ETHOSU_PMU_CCNT_Msk) |
| 431 | { |
| 432 | ETHOSU_PMU_CNTR_Enable(ETHOSU_PMU_CCNT_Msk); |
| 433 | } |
| 434 | } |
| 435 | } |
| 436 | for (int i = 0; i < ETHOSU_PMU_NCOUNTERS; i++) |
| 437 | { |
| 438 | uint32_t cntr = (0x0001 << i); |
| 439 | |
| 440 | if (mask & cntr) |
| 441 | { |
| 442 | ETHOSU_PMU_CNTR_Disable(cntr); |
| 443 | (*ethosu_pmu_cntr)[i]++; |
| 444 | if (cntrs_active & cntr) |
| 445 | { |
| 446 | ETHOSU_PMU_CNTR_Enable(cntr); |
| 447 | } |
| 448 | } |
| 449 | } |
| 450 | } |
| 451 | |
| 452 | #endif /* PMU_ETHOSU_H */ |