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Kristofer Jonsson49bdee82020-04-06 13:21:21 +02001/*
2 * Copyright (c) 2019-2020 Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Licensed under the Apache License, Version 2.0 (the License); you may
7 * not use this file except in compliance with the License.
8 * You may obtain a copy of the License at
9 *
10 * www.apache.org/licenses/LICENSE-2.0
11 *
12 * Unless required by applicable law or agreed to in writing, software
13 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
14 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15 * See the License for the specific language governing permissions and
16 * limitations under the License.
17 */
18
19#pragma once
20
21/******************************************************************************
22 * Includes
23 ******************************************************************************/
24
Bhavik Patel5da40922020-07-15 10:06:43 +020025#include "pmu_ethosu.h"
26
27#include <stdbool.h>
Kristofer Jonsson49bdee82020-04-06 13:21:21 +020028#include <stdint.h>
29
30#ifdef __cplusplus
31extern "C" {
32#endif
33
34/******************************************************************************
35 * Defines
36 ******************************************************************************/
37
38#define ETHOSU_DRIVER_VERSION_MAJOR 0 ///< Driver major version
Douglas Trohaf6a85da2020-05-11 11:45:28 +020039#define ETHOSU_DRIVER_VERSION_MINOR 16 ///< Driver minor version
Kristofer Jonsson49bdee82020-04-06 13:21:21 +020040#define ETHOSU_DRIVER_VERSION_PATCH 0 ///< Driver patch version
41#define ETHOSU_DRIVER_BASEP_INDEXES 8 ///< Number of base pointer indexes
42
43/******************************************************************************
44 * Types
45 ******************************************************************************/
46
47enum ethosu_error_codes
48{
49 ETHOSU_SUCCESS = 0, ///< Success
50 ETHOSU_GENERIC_FAILURE = -1, ///< Generic failure
51 ETHOSU_INVALID_PARAM = -2 ///< Invalid parameter
52};
53
Bhavik Pateldae5be02020-06-18 15:25:15 +020054struct ethosu_device
55{
56 uintptr_t base_address;
Bhavik Patel5da40922020-07-15 10:06:43 +020057 bool restore_pmu_config;
58 uint64_t pmccntr;
59 uint32_t pmu_evcntr[ETHOSU_PMU_NCOUNTERS];
60 enum ethosu_pmu_event_type pmu_evtypr[ETHOSU_PMU_NCOUNTERS];
Bhavik Pateldae5be02020-06-18 15:25:15 +020061};
62
Kristofer Jonsson49bdee82020-04-06 13:21:21 +020063struct ethosu_id
64{
65 uint32_t version_status; ///< Version status
66 uint32_t version_minor; ///< Version minor
67 uint32_t version_major; ///< Version major
68 uint32_t product_major; ///< Product major
69 uint32_t arch_patch_rev; ///< Architecture version patch
70 uint32_t arch_minor_rev; ///< Architecture version minor
71 uint32_t arch_major_rev; ///< Architecture version major
72};
73
74struct ethosu_config
75{
76 struct
77 {
78 uint32_t macs_per_cc; ///< MACs per clock cycle
79 uint32_t cmd_stream_version; ///< NPU command stream version
80 uint32_t shram_size; ///< SHRAM size
81 };
82};
83
84/**
85 * Memory type parameter for set_regioncfg_reg:
86 * Counter{0,1}: Outstanding transactions for
87 * AXI port 0 for memory type/region a=0,b=1
88 * Counter{2,3}: Outstanding transactions for
89 * AXI port 1 for memory type/region a=2,b=3
90 */
91enum ethosu_memory_type
92{
93 ETHOSU_AXI0_OUTSTANDING_COUNTER0 = 0, ///< NPU axi0_outstanding_counter0
94 ETHOSU_AXI0_OUTSTANDING_COUNTER1 = 1, ///< NPU axi0_outstanding_counter1
95 ETHOSU_AXI1_OUTSTANDING_COUNTER2 = 2, ///< NPU axi1_outstanding_counter2
96 ETHOSU_AXI1_OUTSTANDING_COUNTER3 = 3 ///< NPU axi1_outstanding_counter3
97};
98
99enum ethosu_axi_limit_beats
100{
101 ETHOSU_AXI_LIMIT_64_BYTES = 0, ///< NPU AXI limit 64 byte burst split alignment.
102 ETHOSU_AXI_LIMIT_128_BYTES = 1, ///< NPU AXI limit 128 byte burst split alignment.
103 ETHOSU_AXI_LIMIT_256_BYTES = 2 ///< NPU AXI limit 256 byte burst split alignment.
104};
105
106enum ethosu_axi_limit_mem_type
107{
108 ETHOSU_MEM_TYPE_DEVICE_NON_BUFFERABLE = 0,
109 ETHOSU_MEM_TYPE_DEVICE_BUFFERABLE = 1,
110 ETHOSU_MEM_TYPE_NORMAL_NON_CACHEABLE_NON_BUFFERABLE = 2,
111 ETHOSU_MEM_TYPE_NORMAL_NON_CACHEABLE_BUFFERABLE = 3,
112 ETHOSU_MEM_TYPE_WRITE_THROUGH_NO_ALLOCATE = 4,
113 ETHOSU_MEM_TYPE_WRITE_THROUGH_READ_ALLOCATE = 5,
114 ETHOSU_MEM_TYPE_WRITE_THROUGH_WRITE_ALLOCATE = 6,
115 ETHOSU_MEM_TYPE_WRITE_THROUGH_READ_AND_WRITE_ALLOCATE = 7,
116 ETHOSU_MEM_TYPE_WRITE_BACK_NO_ALLOCATE = 8,
117 ETHOSU_MEM_TYPE_WRITE_BACK_READ_ALLOCATE = 9,
118 ETHOSU_MEM_TYPE_WRITE_BACK_WRITE_ALLOCATE = 10,
119 ETHOSU_MEM_TYPE_WRITE_BACK_READ_AND_WRITE_ALLOCATE = 11
120};
121
122enum ethosu_clock_q_request
123{
124 ETHOSU_CLOCK_Q_DISABLE = 0, ///< Disble NPU signal ready for clock off.
125 ETHOSU_CLOCK_Q_ENABLE = 1 ///< Enable NPU signal ready for clock off when stop+idle state reached.
126};
127
128enum ethosu_power_q_request
129{
130 ETHOSU_POWER_Q_DISABLE = 0, ///< Disble NPU signal ready for power off.
131 ETHOSU_POWER_Q_ENABLE = 1 ///< Enable NPU signal ready for power off when stop+idle state reached.
132};
133
134/******************************************************************************
135 * Prototypes
136 ******************************************************************************/
137
138/**
139 * Initialize the device.
140 */
Bhavik Pateldae5be02020-06-18 15:25:15 +0200141enum ethosu_error_codes ethosu_dev_init(struct ethosu_device *dev, const void *base_address);
Kristofer Jonsson49bdee82020-04-06 13:21:21 +0200142
143/**
144 * Get device id.
145 */
Bhavik Pateldae5be02020-06-18 15:25:15 +0200146enum ethosu_error_codes ethosu_get_id(struct ethosu_device *dev, struct ethosu_id *id);
Kristofer Jonsson49bdee82020-04-06 13:21:21 +0200147
148/**
149 * Get device configuration.
150 */
Bhavik Pateldae5be02020-06-18 15:25:15 +0200151enum ethosu_error_codes ethosu_get_config(struct ethosu_device *dev, struct ethosu_config *config);
Kristofer Jonsson49bdee82020-04-06 13:21:21 +0200152
153/**
154 * Execute a given command stream on NPU.
155 * \param[in] cmd_stream_ptr Pointer to the command stream
156 * \param[in] cms_length Command stream length
157 * \param[in] base_addr Pointer to array of base addresses
158 * - 0: weight tensor
159 * - 1: scratch tensor
160 * - All input tensors
161 * - All output tensors
162 * \param[in] num_base_addr Number of base addresses.
163 * \return \ref ethosu_error_codes
164 */
Bhavik Pateldae5be02020-06-18 15:25:15 +0200165enum ethosu_error_codes ethosu_run_command_stream(struct ethosu_device *dev,
166 const uint8_t *cmd_stream_ptr,
Kristofer Jonsson49bdee82020-04-06 13:21:21 +0200167 uint32_t cms_length,
168 const uint64_t *base_addr,
169 int num_base_addr);
170
171/**
172 * Check if IRQ is raised.
173 * \param[out] irq_status Pointer to IRQ status
174 * - 0 IRQ not raised
175 * - 1 IRQ raised
176 * \return \ref ethosu_error_codes
177 */
Bhavik Pateldae5be02020-06-18 15:25:15 +0200178enum ethosu_error_codes ethosu_is_irq_raised(struct ethosu_device *dev, uint8_t *irq_status);
Kristofer Jonsson49bdee82020-04-06 13:21:21 +0200179
180/**
181 * Clear IRQ status.
182 * \return \ref ethosu_error_codes
183 */
Bhavik Pateldae5be02020-06-18 15:25:15 +0200184enum ethosu_error_codes ethosu_clear_irq_status(struct ethosu_device *dev);
Kristofer Jonsson49bdee82020-04-06 13:21:21 +0200185
186/**
187 * Get the 16 bit status mask.
188 * \param[out] irq_status_mask Pointer to the status mask.
189 * The lower 16 bits of status reg are returned.
190 * bit0: state
191 * bit1: irq_raised
192 * bit2: bus_status
193 * bit3: reset_status
194 * bit4: cmd_parse_error
195 * bit5: cmd_end_reached
196 * bit6: pmu_irq_raised
197 * bit7-15: reserved
198 * \return \ref ethosu_error_codes
199 */
Bhavik Pateldae5be02020-06-18 15:25:15 +0200200enum ethosu_error_codes ethosu_get_status_mask(struct ethosu_device *dev, uint16_t *status_mask);
Kristofer Jonsson49bdee82020-04-06 13:21:21 +0200201
202/**
203 * Get the 16 bit IRQ history mask.
204 * \param[out] irq_history_mask Pointer to the IRQ history mask.
205 * \return \ref ethosu_error_codes
206 */
Bhavik Pateldae5be02020-06-18 15:25:15 +0200207enum ethosu_error_codes ethosu_get_irq_history_mask(struct ethosu_device *dev, uint16_t *irq_history_mask);
Kristofer Jonsson49bdee82020-04-06 13:21:21 +0200208
209/**
210 * Clear the given bits in the
211 * IRQ history mask.
212 * \param[in] irq_history_clear_mask 16 bit mask indicating which bits to
213 * clear in the IRQ history mask.
214 * \return \ref ethosu_error_codes
215 */
Bhavik Pateldae5be02020-06-18 15:25:15 +0200216enum ethosu_error_codes ethosu_clear_irq_history_mask(struct ethosu_device *dev, uint16_t irq_history_clear_mask);
Kristofer Jonsson49bdee82020-04-06 13:21:21 +0200217
218/**
219 * Perform a NPU soft reset.
220 * \return \ref ethosu_error_codes
221 */
Bhavik Pateldae5be02020-06-18 15:25:15 +0200222enum ethosu_error_codes ethosu_soft_reset(struct ethosu_device *dev);
Kristofer Jonsson49bdee82020-04-06 13:21:21 +0200223
224/**
225 * Wait for reset ready.
226 * \return \ref ethosu_error_codes
227 */
Bhavik Pateldae5be02020-06-18 15:25:15 +0200228enum ethosu_error_codes ethosu_wait_for_reset(struct ethosu_device *dev);
Kristofer Jonsson49bdee82020-04-06 13:21:21 +0200229
230/**
231 * Read and return the content of a given NPU APB
232 * register range.
233 * \param[in] start_address Start address.
234 * \param[in] num_reg Number of registers to read.
235 * \param[out] reg_p Pointer to a output area, allocated by the
236 * caller, where the register content shall be
237 * written.
238 * \return \ref ethosu_error_codes
239 */
Bhavik Pateldae5be02020-06-18 15:25:15 +0200240enum ethosu_error_codes ethosu_read_apb_reg(struct ethosu_device *dev,
241 uint32_t start_address,
242 uint16_t num_reg,
243 uint32_t *reg_p);
Kristofer Jonsson49bdee82020-04-06 13:21:21 +0200244
245/**
246 * Set qconfig register. I.e.
247 * AXI configuration for the command stream.
248 * \param[in] memory_type Memory_type to use for command stream:
249 * enum ethosu_memory_type.
250 * \return \ref ethosu_error_codes
251 */
Bhavik Pateldae5be02020-06-18 15:25:15 +0200252enum ethosu_error_codes ethosu_set_qconfig(struct ethosu_device *dev, enum ethosu_memory_type memory_type);
Kristofer Jonsson49bdee82020-04-06 13:21:21 +0200253
254/**
255 * Set register REGIONCFG.
256 * Base pointer configuration.
257 * Bits[2*k+1:2*k] give the memory type for BASEP[k].
258 * \param[in] region Region field to set: 0 - 7.
259 * \param[in] memory_type Memory_type to use for region: enum ethosu_memory_type.
260 * \return \ref ethosu_error_codes
261 */
Bhavik Pateldae5be02020-06-18 15:25:15 +0200262enum ethosu_error_codes ethosu_set_regioncfg(struct ethosu_device *dev,
263 uint8_t region,
264 enum ethosu_memory_type memory_type);
Kristofer Jonsson49bdee82020-04-06 13:21:21 +0200265
266/**
267 * Set AXI limit parameters for port 0 counter 0.
268 * \param[in] max_beats Burst split alignment, \ref ethosu_axi_limit_beats.
269 * \param[in] memtype Cache policy \ref ethosu_axi_limit_mem_type
270 * \param[in] max_reads Maximum number of outstanding reads.
271 * \param[in] max_writes Maximum number of outstanding writes.
272 * \return \ref ethosu_error_codes
273 */
Bhavik Pateldae5be02020-06-18 15:25:15 +0200274enum ethosu_error_codes ethosu_set_axi_limit0(struct ethosu_device *dev,
275 enum ethosu_axi_limit_beats max_beats,
Kristofer Jonsson49bdee82020-04-06 13:21:21 +0200276 enum ethosu_axi_limit_mem_type memtype,
277 uint8_t max_reads,
278 uint8_t max_writes);
279/**
280 * Set AXI limit parameters for port 0 counter 1.
281 * \param[in] max_beats Burst split alignment, \ref ethosu_axi_limit_beats.
282 * \param[in] memtype Cache policy \ref ethosu_axi_limit_mem_type
283 * \param[in] max_reads Maximum number of outstanding reads.
284 * \param[in] max_writes Maximum number of outstanding writes.
285 * \return \ref ethosu_error_codes
286 */
Bhavik Pateldae5be02020-06-18 15:25:15 +0200287enum ethosu_error_codes ethosu_set_axi_limit1(struct ethosu_device *dev,
288 enum ethosu_axi_limit_beats max_beats,
Kristofer Jonsson49bdee82020-04-06 13:21:21 +0200289 enum ethosu_axi_limit_mem_type memtype,
290 uint8_t max_reads,
291 uint8_t max_writes);
292/**
293 * Set AXI limit parameters for port 1 counter 2.
294 * \param[in] max_beats Burst split alignment, \ref ethosu_axi_limit_beats.
295 * \param[in] memtype Cache policy \ref ethosu_axi_limit_mem_type
296 * \param[in] max_reads Maximum number of outstanding reads.
297 * \param[in] max_writes Maximum number of outstanding writes.
298 * \return \ref ethosu_error_codes
299 */
Bhavik Pateldae5be02020-06-18 15:25:15 +0200300enum ethosu_error_codes ethosu_set_axi_limit2(struct ethosu_device *dev,
301 enum ethosu_axi_limit_beats max_beats,
Kristofer Jonsson49bdee82020-04-06 13:21:21 +0200302 enum ethosu_axi_limit_mem_type memtype,
303 uint8_t max_reads,
304 uint8_t max_writes);
305/**
306 * Set AXI limit parameters for port 1 counter 3.
307 * \param[in] max_beats Burst split alignment, \ref ethosu_axi_limit_beats.
308 * \param[in] memtype Cache policy \ref ethosu_axi_limit_mem_type
309 * \param[in] max_reads Maximum number of outstanding reads.
310 * \param[in] max_writes Maximum number of outstanding writes.
311 * \return \ref ethosu_error_codes
312 */
Bhavik Pateldae5be02020-06-18 15:25:15 +0200313enum ethosu_error_codes ethosu_set_axi_limit3(struct ethosu_device *dev,
314 enum ethosu_axi_limit_beats max_beats,
Kristofer Jonsson49bdee82020-04-06 13:21:21 +0200315 enum ethosu_axi_limit_mem_type memtype,
316 uint8_t max_reads,
317 uint8_t max_writes);
318
319/**
320 * Get current command stream queue read position.
321 * \param[out] qread Pointer to queue read.
322 * \return \ref ethosu_error_codes
323 */
Bhavik Pateldae5be02020-06-18 15:25:15 +0200324enum ethosu_error_codes ethosu_get_qread(struct ethosu_device *dev, uint32_t *qread);
Kristofer Jonsson49bdee82020-04-06 13:21:21 +0200325
326/**
327 * Get revision of NPU
328 * \param[out] revision Pointer to revision read.
329 * \return \ref ethosu_error_codes
330 */
Bhavik Pateldae5be02020-06-18 15:25:15 +0200331enum ethosu_error_codes ethosu_get_revision(struct ethosu_device *dev, uint32_t *revision);
Kristofer Jonsson49bdee82020-04-06 13:21:21 +0200332
333/**
334 * Issue run command for the currently programmed
335 * command stream, starting at current queue read
336 * position.
337 * \return \ref ethosu_error_codes
338 */
Bhavik Pateldae5be02020-06-18 15:25:15 +0200339enum ethosu_error_codes ethosu_set_command_run(struct ethosu_device *dev);
Kristofer Jonsson49bdee82020-04-06 13:21:21 +0200340
341/**
342 * Dump a 1KB section of SHRAM.
343 * \param[in] section Section offset to 1KB section in SHRAM.
344 * \param[out] shram_p Pointer to a output area, allocated by the
345 * caller, where the SHRAM content shall be
346 * written.
347 * \return \ref ethosu_error_codes
348 */
Bhavik Pateldae5be02020-06-18 15:25:15 +0200349enum ethosu_error_codes ethosu_get_shram_data(struct ethosu_device *dev, int section, uint32_t *shram_p);
Kristofer Jonsson49bdee82020-04-06 13:21:21 +0200350
351/**
352 * Set clock and power q request enable bits.
353 * \param[in] clock_q Clock q ENABLE/DISABLE \ref clock_q_request.
354 * \param[in] power_q Power q ENABLE/DISABLE \ref power_q_request.
355 * \return \ref ethosu_error_codes
356 */
Bhavik Pateldae5be02020-06-18 15:25:15 +0200357enum ethosu_error_codes ethosu_set_clock_and_power(struct ethosu_device *dev,
358 enum ethosu_clock_q_request clock_q,
Kristofer Jonsson49bdee82020-04-06 13:21:21 +0200359 enum ethosu_power_q_request power_q);
360
Bhavik Pateldae5be02020-06-18 15:25:15 +0200361uint32_t ethosu_read_reg(struct ethosu_device *dev, uint32_t address);
362
363void ethosu_write_reg(struct ethosu_device *dev, uint32_t address, uint32_t value);
364
Bhavik Patel5da40922020-07-15 10:06:43 +0200365/**
366 * Save the PMU configuration to ethosu_device struct.
367 * \param[in] dev Ethos-U device where the PMU configuration is
368 * saved.
369 * \return \ref ethosu_error_codes
370 */
371enum ethosu_error_codes ethosu_save_pmu_config(struct ethosu_device *dev);
372
373/**
374 * Restore the PMU configuration from a ethosu_device struct.
375 * \param[in] dev Ethos-U device where the PMU configuration is
376 * stored.
377 * \return \ref ethosu_error_codes
378 */
379enum ethosu_error_codes ethosu_restore_pmu_config(struct ethosu_device *dev);
380
Kristofer Jonsson49bdee82020-04-06 13:21:21 +0200381#ifdef __cplusplus
382}
383#endif