Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 1 | /* |
Kristofer Jonsson | 09273d1 | 2021-03-15 08:43:08 +0100 | [diff] [blame] | 2 | * Copyright (c) 2019-2021 Arm Limited. All rights reserved. |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: Apache-2.0 |
| 5 | * |
| 6 | * Licensed under the Apache License, Version 2.0 (the License); you may |
| 7 | * not use this file except in compliance with the License. |
| 8 | * You may obtain a copy of the License at |
| 9 | * |
| 10 | * www.apache.org/licenses/LICENSE-2.0 |
| 11 | * |
| 12 | * Unless required by applicable law or agreed to in writing, software |
| 13 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT |
| 14 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 15 | * See the License for the specific language governing permissions and |
| 16 | * limitations under the License. |
| 17 | */ |
| 18 | |
Kristofer Jonsson | 2b201c3 | 2020-09-02 16:42:43 +0200 | [diff] [blame] | 19 | /****************************************************************************** |
| 20 | * Includes |
| 21 | ******************************************************************************/ |
| 22 | |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 23 | #include "ethosu_driver.h" |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 24 | #include "ethosu_common.h" |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 25 | #include "ethosu_config.h" |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 26 | #include "ethosu_device.h" |
Per Åstrand | 25d78c0 | 2020-04-21 14:19:44 +0200 | [diff] [blame] | 27 | |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 28 | #include <assert.h> |
Per Åstrand | 25d78c0 | 2020-04-21 14:19:44 +0200 | [diff] [blame] | 29 | #include <cmsis_compiler.h> |
Per Åstrand | 14ccfee | 2020-09-25 10:40:20 +0200 | [diff] [blame] | 30 | #include <inttypes.h> |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 31 | #include <stdbool.h> |
Bhavik Patel | bf7ae63 | 2020-06-11 21:00:16 +0200 | [diff] [blame] | 32 | #include <stddef.h> |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 33 | #include <stdio.h> |
| 34 | #include <stdlib.h> |
| 35 | |
Kristofer Jonsson | 2b201c3 | 2020-09-02 16:42:43 +0200 | [diff] [blame] | 36 | /****************************************************************************** |
| 37 | * Defines |
| 38 | ******************************************************************************/ |
| 39 | |
| 40 | #define MACS_PER_CYCLE_LOG2_MASK 0x000F |
| 41 | #define SHRAM_SIZE_MASK 0xFF00 |
| 42 | #define SHRAM_SIZE_RIGHT_SHIFT 8 |
| 43 | #define BYTES_IN_32_BITS 4 |
| 44 | #define CUSTOM_OPTION_LENGTH_32_BIT_WORD 1 |
| 45 | #define DRIVER_ACTION_LENGTH_32_BIT_WORD 1 |
| 46 | #define OPTIMIZER_CONFIG_LENGTH_32_BIT_WORD 2 |
| 47 | #define ETHOSU_FOURCC ('1' << 24 | 'P' << 16 | 'O' << 8 | 'C') // "Custom Operator Payload 1" |
| 48 | #define APB_START_ADDR_MASK 0x0FFF |
| 49 | #define APB_NUM_REG_BIT_SHIFT 12 |
| 50 | #define BYTES_1KB 1024 |
| 51 | #define PRODUCT_MAJOR_ETHOSU55 (4) |
| 52 | #define MASK_16_BYTE_ALIGN (0xF) |
| 53 | #define FAST_MEMORY_BASE_ADDR_INDEX 2 |
| 54 | |
| 55 | /****************************************************************************** |
| 56 | * Types |
| 57 | ******************************************************************************/ |
| 58 | |
| 59 | // Driver actions |
| 60 | enum DRIVER_ACTION_e |
| 61 | { |
| 62 | RESERVED = 0, |
| 63 | OPTIMIZER_CONFIG = 1, |
| 64 | COMMAND_STREAM = 2, |
| 65 | READ_APB_REG = 3, |
| 66 | DUMP_SHRAM = 4, |
| 67 | NOP = 5, |
| 68 | }; |
| 69 | |
| 70 | // Custom data struct |
| 71 | struct custom_data_s |
| 72 | { |
| 73 | union |
| 74 | { |
| 75 | // Driver action data |
| 76 | struct |
| 77 | { |
| 78 | // Driver action command (valid values in DRIVER_ACTION_e) |
| 79 | uint8_t driver_action_command; |
| 80 | |
| 81 | // reserved |
| 82 | uint8_t reserved; |
| 83 | |
| 84 | // Driver action data |
| 85 | union |
| 86 | { |
| 87 | // DA_CMD_OPT_CFG |
| 88 | struct |
| 89 | { |
| 90 | uint16_t rel_nbr : 4; |
| 91 | uint16_t patch_nbr : 4; |
| 92 | uint16_t opt_cfg_reserved : 8; |
| 93 | }; |
| 94 | |
| 95 | // DA_CMD_CMSTRM |
| 96 | struct |
| 97 | { |
| 98 | uint16_t length; |
| 99 | }; |
| 100 | |
| 101 | // DA_CMD_READAPB |
| 102 | struct |
| 103 | { |
| 104 | uint16_t start_address : 12; |
| 105 | uint16_t nbr_reg_minus1 : 4; |
| 106 | }; |
| 107 | |
| 108 | uint16_t driver_action_data; |
| 109 | }; |
| 110 | }; |
| 111 | |
| 112 | uint32_t word; |
| 113 | }; |
| 114 | }; |
| 115 | |
| 116 | // optimizer config struct |
| 117 | struct opt_cfg_s |
| 118 | { |
| 119 | struct custom_data_s da_data; |
| 120 | union |
| 121 | { |
| 122 | struct |
| 123 | { |
| 124 | uint32_t macs_per_cc : 4; |
| 125 | uint32_t cmd_stream_version : 4; |
| 126 | uint32_t shram_size : 8; |
Anton Moberg | b8bcf13 | 2021-03-29 10:02:25 +0200 | [diff] [blame^] | 127 | uint32_t reserved0 : 11; |
| 128 | uint32_t custom_dma : 1; |
| 129 | uint32_t product : 4; |
Kristofer Jonsson | 2b201c3 | 2020-09-02 16:42:43 +0200 | [diff] [blame] | 130 | }; |
| 131 | uint32_t npu_cfg; |
| 132 | }; |
| 133 | union |
| 134 | { |
| 135 | struct |
| 136 | { |
| 137 | uint32_t version_status : 4; |
| 138 | uint32_t version_minor : 4; |
| 139 | uint32_t version_major : 4; |
| 140 | uint32_t product_major : 4; |
| 141 | uint32_t arch_patch_rev : 4; |
| 142 | uint32_t arch_minor_rev : 8; |
| 143 | uint32_t arch_major_rev : 4; |
| 144 | }; |
| 145 | uint32_t ethosu_id; |
| 146 | }; |
| 147 | }; |
| 148 | |
| 149 | /****************************************************************************** |
| 150 | * Functions |
| 151 | ******************************************************************************/ |
| 152 | |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 153 | struct ethosu_driver ethosu_drv = { |
Kristofer Jonsson | c6e7a1f | 2020-11-24 09:20:14 +0100 | [diff] [blame] | 154 | .dev = {.base_address = NULL, .proto = 0, .pmccntr = {0}, .pmu_evcntr = {0, 0, 0, 0}, .pmu_evtypr = {0, 0, 0, 0}}, |
Anton Moberg | 8d65b6f | 2020-12-21 09:37:18 +0100 | [diff] [blame] | 155 | .abort_inference = false, |
| 156 | .status_error = false, |
| 157 | .dev_power_always_on = false}; |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 158 | |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 159 | // Registered drivers linked list HEAD |
| 160 | static struct ethosu_driver *registered_drivers = NULL; |
| 161 | |
Anton Moberg | dfed5fd | 2021-03-11 14:41:11 +0100 | [diff] [blame] | 162 | /* |
| 163 | * Following section handles the minimal sempahore and mutex implementation in case of baremetal applications. |
| 164 | * Weak symbols will be overwritten by RTOS definitions and implement true thread-safety. (Done in application layer) |
| 165 | */ |
| 166 | |
| 167 | // Baremetal sempahore implementation |
| 168 | struct ethosu_semaphore_t |
| 169 | { |
| 170 | int count; |
| 171 | }; |
| 172 | |
| 173 | // Minimal needed declaration to allow baremetal functionality. |
| 174 | static void *ethosu_mutex; |
| 175 | static void *ethosu_semaphore; |
| 176 | |
| 177 | void *__attribute__((weak)) ethosu_mutex_create(void) {} |
| 178 | |
| 179 | void __attribute__((weak)) ethosu_mutex_lock(void *mutex) {} |
| 180 | |
| 181 | void __attribute__((weak)) ethosu_mutex_unlock(void *mutex) {} |
| 182 | |
| 183 | // Baremetal implementation of creating a semaphore |
| 184 | void *__attribute__((weak)) ethosu_semaphore_create(void) |
| 185 | { |
| 186 | struct ethosu_semaphore_t *sem = malloc(sizeof(*sem)); |
| 187 | sem->count = 1; |
| 188 | return sem; |
| 189 | } |
| 190 | |
| 191 | // Baremetal simulation of waiting/sleeping for and then taking a semaphore using intrisics |
| 192 | void __attribute__((weak)) ethosu_semaphore_take(void *sem) |
| 193 | { |
| 194 | struct ethosu_semaphore_t *s = sem; |
| 195 | while (s->count <= 0) |
| 196 | { |
| 197 | __WFE(); |
| 198 | } |
| 199 | s->count--; |
| 200 | } |
| 201 | |
| 202 | // Baremetal simulation of giving a semaphore and waking up processes using intrinsics |
| 203 | void __attribute__((weak)) ethosu_semaphore_give(void *sem) |
| 204 | { |
| 205 | struct ethosu_semaphore_t *s = sem; |
| 206 | s->count++; |
| 207 | __SEV(); |
| 208 | } |
| 209 | // <--- End of semaphore and mutex implementations |
| 210 | |
Anton Moberg | 8d65b6f | 2020-12-21 09:37:18 +0100 | [diff] [blame] | 211 | static int ethosu_soft_reset_and_restore(struct ethosu_driver *drv); |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 212 | |
Kristofer Jonsson | 09273d1 | 2021-03-15 08:43:08 +0100 | [diff] [blame] | 213 | void __attribute__((weak)) ethosu_irq_handler_v2(struct ethosu_driver *drv) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 214 | { |
| 215 | uint8_t irq_raised = 0; |
Kristofer Jonsson | 125429a | 2020-08-20 16:52:23 +0200 | [diff] [blame] | 216 | |
| 217 | LOG_DEBUG("Interrupt. status=0x%08x, qread=%d\n", |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 218 | ethosu_read_reg(&drv->dev, NPU_REG_STATUS), |
| 219 | ethosu_read_reg(&drv->dev, NPU_REG_QREAD)); |
Kristofer Jonsson | 125429a | 2020-08-20 16:52:23 +0200 | [diff] [blame] | 220 | |
| 221 | // Verify that interrupt has been raised |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 222 | (void)ethosu_is_irq_raised(&drv->dev, &irq_raised); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 223 | ASSERT(irq_raised == 1); |
Anton Moberg | dfed5fd | 2021-03-11 14:41:11 +0100 | [diff] [blame] | 224 | drv->irq_triggered = true; |
Kristofer Jonsson | 125429a | 2020-08-20 16:52:23 +0200 | [diff] [blame] | 225 | |
| 226 | // Clear interrupt |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 227 | (void)ethosu_clear_irq_status(&drv->dev); |
Kristofer Jonsson | 125429a | 2020-08-20 16:52:23 +0200 | [diff] [blame] | 228 | |
Bhavik Patel | 5f8dad1 | 2020-09-30 09:06:52 +0200 | [diff] [blame] | 229 | // Verify that interrupt has been successfully cleared |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 230 | (void)ethosu_is_irq_raised(&drv->dev, &irq_raised); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 231 | ASSERT(irq_raised == 0); |
Bhavik Patel | 5f8dad1 | 2020-09-30 09:06:52 +0200 | [diff] [blame] | 232 | |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 233 | if (ethosu_status_has_error(&drv->dev)) |
Bhavik Patel | 5f8dad1 | 2020-09-30 09:06:52 +0200 | [diff] [blame] | 234 | { |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 235 | ethosu_soft_reset_and_restore(drv); |
| 236 | drv->status_error = true; |
Bhavik Patel | 5f8dad1 | 2020-09-30 09:06:52 +0200 | [diff] [blame] | 237 | } |
Anton Moberg | dfed5fd | 2021-03-11 14:41:11 +0100 | [diff] [blame] | 238 | |
| 239 | ethosu_semaphore_give(drv->semaphore); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 240 | } |
| 241 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 242 | static inline void wait_for_irq(struct ethosu_driver *drv) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 243 | { |
| 244 | while (1) |
| 245 | { |
Anton Moberg | dfed5fd | 2021-03-11 14:41:11 +0100 | [diff] [blame] | 246 | if (drv->irq_triggered || drv->abort_inference) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 247 | { |
Anton Moberg | dfed5fd | 2021-03-11 14:41:11 +0100 | [diff] [blame] | 248 | drv->irq_triggered = false; |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 249 | break; |
| 250 | } |
| 251 | |
Anton Moberg | dfed5fd | 2021-03-11 14:41:11 +0100 | [diff] [blame] | 252 | ethosu_semaphore_take(drv->semaphore); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 253 | } |
| 254 | } |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 255 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 256 | static int handle_optimizer_config(struct ethosu_driver *drv, struct opt_cfg_s *opt_cfg_p); |
| 257 | static int handle_command_stream(struct ethosu_driver *drv, |
| 258 | const uint8_t *cmd_stream, |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 259 | const int cms_length, |
| 260 | const uint64_t *base_addr, |
Per Åstrand | 3c8afcc | 2020-10-20 10:29:59 +0200 | [diff] [blame] | 261 | const size_t *base_addr_size, |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 262 | const int num_base_addr); |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 263 | static int read_apb_reg(struct ethosu_driver *drv, uint16_t); |
| 264 | static int dump_shram(struct ethosu_driver *drv); |
| 265 | static void dump_npu_register(struct ethosu_driver *drv, int npu_reg, int npu_reg_end); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 266 | static void dump_command_stream(const uint32_t *cmd_stream, const int cms_length, int qread); |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 267 | static void npu_axi_init(struct ethosu_driver *drv); |
Anton Moberg | df386e0 | 2021-02-02 11:26:48 +0100 | [diff] [blame] | 268 | static struct ethosu_driver *ethosu_find_and_reserve_driver(void); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 269 | |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 270 | int ethosu_init_v4(struct ethosu_driver *drv, |
| 271 | const void *base_address, |
Per Åstrand | e6498f0 | 2020-11-09 15:33:12 +0100 | [diff] [blame] | 272 | const void *fast_memory, |
| 273 | const size_t fast_memory_size, |
| 274 | uint32_t secure_enable, |
| 275 | uint32_t privilege_enable) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 276 | { |
| 277 | int return_code = 0; |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 278 | |
Bhavik Patel | 033bb1b | 2020-12-17 15:33:33 +0100 | [diff] [blame] | 279 | LOG_INFO("%s. base_address=%p, fast_memory=%p, fast_memory_size=%zu, secure=%" PRIu32 ", privileged=%" PRIu32 "\n", |
Kristofer Jonsson | 2b201c3 | 2020-09-02 16:42:43 +0200 | [diff] [blame] | 280 | __FUNCTION__, |
| 281 | base_address, |
| 282 | fast_memory, |
Per Åstrand | e6498f0 | 2020-11-09 15:33:12 +0100 | [diff] [blame] | 283 | fast_memory_size, |
| 284 | secure_enable, |
| 285 | privilege_enable); |
Kristofer Jonsson | 2b201c3 | 2020-09-02 16:42:43 +0200 | [diff] [blame] | 286 | |
Anton Moberg | dfed5fd | 2021-03-11 14:41:11 +0100 | [diff] [blame] | 287 | if (!ethosu_mutex) |
| 288 | { |
| 289 | ethosu_mutex = ethosu_mutex_create(); |
| 290 | } |
| 291 | |
| 292 | if (!ethosu_semaphore) |
| 293 | { |
| 294 | ethosu_semaphore = ethosu_semaphore_create(); |
| 295 | } |
| 296 | |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 297 | ethosu_register_driver(drv); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 298 | |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 299 | drv->fast_memory = (uint32_t)fast_memory; |
| 300 | drv->fast_memory_size = fast_memory_size; |
Anton Moberg | dfed5fd | 2021-03-11 14:41:11 +0100 | [diff] [blame] | 301 | drv->irq_triggered = false; |
| 302 | drv->semaphore = ethosu_semaphore_create(); |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 303 | |
| 304 | if (ETHOSU_SUCCESS != ethosu_dev_init(&drv->dev, base_address, secure_enable, privilege_enable)) |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 305 | { |
| 306 | LOG_ERR("Failed in ethosu_dev_init"); |
| 307 | return -1; |
| 308 | } |
| 309 | |
Anton Moberg | 0a61429 | 2021-03-24 14:08:22 +0100 | [diff] [blame] | 310 | if (ETHOSU_SUCCESS != |
| 311 | set_clock_and_power_request(drv, ETHOSU_INFERENCE_REQUEST, ETHOSU_CLOCK_Q_DISABLE, ETHOSU_POWER_Q_DISABLE)) |
Bhavik Patel | e645fed | 2020-06-12 14:46:47 +0200 | [diff] [blame] | 312 | { |
| 313 | LOG_ERR("Failed to disable clock-q & power-q for Ethos-U\n"); |
| 314 | return -1; |
| 315 | } |
| 316 | |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 317 | if (ETHOSU_SUCCESS != ethosu_soft_reset(&drv->dev)) |
Per Åstrand | 849cf69 | 2020-11-24 07:39:55 +0100 | [diff] [blame] | 318 | { |
| 319 | return -1; |
| 320 | } |
Kristofer Jonsson | daa0d20 | 2020-05-12 12:23:16 +0200 | [diff] [blame] | 321 | |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 322 | if (ETHOSU_SUCCESS != ethosu_wait_for_reset(&drv->dev)) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 323 | { |
| 324 | LOG_ERR("Failed reset of Ethos-U\n"); |
| 325 | return -1; |
| 326 | } |
Anton Moberg | 8d65b6f | 2020-12-21 09:37:18 +0100 | [diff] [blame] | 327 | |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 328 | drv->status_error = false; |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 329 | |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 330 | return return_code; |
| 331 | } |
| 332 | |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 333 | int ethosu_get_version_v2(struct ethosu_driver *drv, struct ethosu_version *version) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 334 | { |
| 335 | int return_code = 0; |
| 336 | |
| 337 | if (NULL != version) |
| 338 | { |
| 339 | struct ethosu_id id; |
| 340 | struct ethosu_config cfg; |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 341 | (void)ethosu_get_id(&drv->dev, &id); |
| 342 | (void)ethosu_get_config(&drv->dev, &cfg); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 343 | |
| 344 | version->id.version_status = id.version_status; |
| 345 | version->id.version_minor = id.version_minor; |
| 346 | version->id.version_major = id.version_major; |
| 347 | version->id.product_major = id.product_major; |
| 348 | version->id.arch_patch_rev = id.arch_patch_rev; |
| 349 | version->id.arch_minor_rev = id.arch_minor_rev; |
| 350 | version->id.arch_major_rev = id.arch_major_rev; |
| 351 | version->id.driver_patch_rev = ETHOSU_DRIVER_VERSION_PATCH; |
| 352 | version->id.driver_minor_rev = ETHOSU_DRIVER_VERSION_MINOR; |
| 353 | version->id.driver_major_rev = ETHOSU_DRIVER_VERSION_MAJOR; |
| 354 | version->cfg.macs_per_cc = cfg.macs_per_cc; |
| 355 | version->cfg.cmd_stream_version = cfg.cmd_stream_version; |
| 356 | version->cfg.shram_size = cfg.shram_size; |
Anton Moberg | b8bcf13 | 2021-03-29 10:02:25 +0200 | [diff] [blame^] | 357 | version->cfg.custom_dma = cfg.custom_dma; |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 358 | } |
| 359 | else |
| 360 | { |
| 361 | return_code = -1; |
| 362 | } |
| 363 | |
| 364 | return return_code; |
| 365 | } |
| 366 | |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 367 | int ethosu_invoke_v3(struct ethosu_driver *drv, |
| 368 | const void *custom_data_ptr, |
Kristofer Jonsson | 2b201c3 | 2020-09-02 16:42:43 +0200 | [diff] [blame] | 369 | const int custom_data_size, |
| 370 | const uint64_t *base_addr, |
| 371 | const size_t *base_addr_size, |
| 372 | const int num_base_addr) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 373 | { |
Kristofer Jonsson | 2b201c3 | 2020-09-02 16:42:43 +0200 | [diff] [blame] | 374 | const struct custom_data_s *data_ptr = custom_data_ptr; |
| 375 | const struct custom_data_s *data_end = custom_data_ptr + custom_data_size; |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 376 | int return_code = 0; |
| 377 | |
Kristofer Jonsson | 2b201c3 | 2020-09-02 16:42:43 +0200 | [diff] [blame] | 378 | LOG_INFO("%s\n", __FUNCTION__); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 379 | |
| 380 | // First word in custom_data_ptr should contain "Custom Operator Payload 1" |
Kristofer Jonsson | 2b201c3 | 2020-09-02 16:42:43 +0200 | [diff] [blame] | 381 | if (data_ptr->word != ETHOSU_FOURCC) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 382 | { |
Per Åstrand | 14ccfee | 2020-09-25 10:40:20 +0200 | [diff] [blame] | 383 | LOG_ERR("Custom Operator Payload: %" PRIu32 " is not correct, expected %x\n", data_ptr->word, ETHOSU_FOURCC); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 384 | return -1; |
| 385 | } |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 386 | |
Kristofer Jonsson | 2b201c3 | 2020-09-02 16:42:43 +0200 | [diff] [blame] | 387 | // Custom data length must be a multiple of 32 bits |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 388 | if ((custom_data_size % BYTES_IN_32_BITS) != 0) |
| 389 | { |
| 390 | LOG_ERR("ethosu_invoke ERROR custom_data_size=0x%x not a multiple of 4\n", custom_data_size); |
| 391 | return -1; |
| 392 | } |
Kristofer Jonsson | 2b201c3 | 2020-09-02 16:42:43 +0200 | [diff] [blame] | 393 | |
| 394 | ++data_ptr; |
| 395 | |
| 396 | // Adjust base address to fast memory area |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 397 | if (drv->fast_memory != 0 && num_base_addr >= FAST_MEMORY_BASE_ADDR_INDEX) |
Kristofer Jonsson | 2b201c3 | 2020-09-02 16:42:43 +0200 | [diff] [blame] | 398 | { |
| 399 | uint64_t *fast_memory = (uint64_t *)&base_addr[FAST_MEMORY_BASE_ADDR_INDEX]; |
| 400 | |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 401 | if (base_addr_size != NULL && base_addr_size[FAST_MEMORY_BASE_ADDR_INDEX] > drv->fast_memory_size) |
Kristofer Jonsson | 2b201c3 | 2020-09-02 16:42:43 +0200 | [diff] [blame] | 402 | { |
Kristofer Jonsson | 4c94b30 | 2020-11-06 10:33:21 +0100 | [diff] [blame] | 403 | LOG_ERR("Fast memory area too small. fast_memory_size=%u, base_addr_size=%u\n", |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 404 | drv->fast_memory_size, |
Kristofer Jonsson | 4c94b30 | 2020-11-06 10:33:21 +0100 | [diff] [blame] | 405 | base_addr_size[FAST_MEMORY_BASE_ADDR_INDEX]); |
| 406 | return -1; |
Kristofer Jonsson | 2b201c3 | 2020-09-02 16:42:43 +0200 | [diff] [blame] | 407 | } |
Kristofer Jonsson | 4c94b30 | 2020-11-06 10:33:21 +0100 | [diff] [blame] | 408 | |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 409 | *fast_memory = drv->fast_memory; |
Kristofer Jonsson | 2b201c3 | 2020-09-02 16:42:43 +0200 | [diff] [blame] | 410 | } |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 411 | |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 412 | if (!drv->dev_power_always_on) |
Bhavik Patel | 5f8dad1 | 2020-09-30 09:06:52 +0200 | [diff] [blame] | 413 | { |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 414 | // Only soft reset if securty state or privilege level needs changing |
| 415 | if (drv->dev.proto != ethosu_read_reg(&drv->dev, NPU_REG_PROT)) |
Per Åstrand | 849cf69 | 2020-11-24 07:39:55 +0100 | [diff] [blame] | 416 | { |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 417 | if (ETHOSU_SUCCESS != ethosu_soft_reset(&drv->dev)) |
Anton Moberg | 8d65b6f | 2020-12-21 09:37:18 +0100 | [diff] [blame] | 418 | { |
| 419 | return -1; |
| 420 | } |
Per Åstrand | 849cf69 | 2020-11-24 07:39:55 +0100 | [diff] [blame] | 421 | } |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 422 | |
| 423 | drv->status_error = false; |
Anton Moberg | 0a61429 | 2021-03-24 14:08:22 +0100 | [diff] [blame] | 424 | set_clock_and_power_request(drv, ETHOSU_INFERENCE_REQUEST, ETHOSU_CLOCK_Q_ENABLE, ETHOSU_POWER_Q_DISABLE); |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 425 | ethosu_restore_pmu_config(&drv->dev); |
| 426 | npu_axi_init(drv); |
Bhavik Patel | 5f8dad1 | 2020-09-30 09:06:52 +0200 | [diff] [blame] | 427 | } |
Kristofer Jonsson | c6e7a1f | 2020-11-24 09:20:14 +0100 | [diff] [blame] | 428 | |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 429 | drv->status_error = false; |
Kristofer Jonsson | 125429a | 2020-08-20 16:52:23 +0200 | [diff] [blame] | 430 | |
Kristofer Jonsson | 2b201c3 | 2020-09-02 16:42:43 +0200 | [diff] [blame] | 431 | while (data_ptr < data_end) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 432 | { |
Bhavik Patel | e645fed | 2020-06-12 14:46:47 +0200 | [diff] [blame] | 433 | int ret = 0; |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 434 | switch (data_ptr->driver_action_command) |
| 435 | { |
| 436 | case OPTIMIZER_CONFIG: |
| 437 | LOG_INFO("ethosu_invoke OPTIMIZER_CONFIG\n"); |
| 438 | struct opt_cfg_s *opt_cfg_p = (struct opt_cfg_s *)data_ptr; |
| 439 | |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 440 | ret = handle_optimizer_config(drv, opt_cfg_p); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 441 | data_ptr += DRIVER_ACTION_LENGTH_32_BIT_WORD + OPTIMIZER_CONFIG_LENGTH_32_BIT_WORD; |
| 442 | break; |
| 443 | case COMMAND_STREAM: |
| 444 | LOG_INFO("ethosu_invoke COMMAND_STREAM\n"); |
| 445 | void *command_stream = (uint8_t *)(data_ptr) + sizeof(struct custom_data_s); |
| 446 | int cms_length = (data_ptr->reserved << 16) | data_ptr->length; |
| 447 | |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 448 | drv->abort_inference = false; |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 449 | // It is safe to clear this flag without atomic, because npu is not running. |
Anton Moberg | dfed5fd | 2021-03-11 14:41:11 +0100 | [diff] [blame] | 450 | drv->irq_triggered = false; |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 451 | |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 452 | ret = handle_command_stream(drv, command_stream, cms_length, base_addr, base_addr_size, num_base_addr); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 453 | |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 454 | if (return_code == -1 && drv->abort_inference) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 455 | { |
| 456 | uint32_t qread = 0; |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 457 | ethosu_get_qread(&drv->dev, &qread); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 458 | LOG_ERR("NPU timeout\n"); |
| 459 | dump_command_stream(command_stream, cms_length, qread); |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 460 | dump_npu_register(drv, 0x200, 0x2BF); |
| 461 | dump_npu_register(drv, 0x800, 0xB3F); |
| 462 | dump_shram(drv); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 463 | } |
| 464 | |
| 465 | data_ptr += DRIVER_ACTION_LENGTH_32_BIT_WORD + cms_length; |
| 466 | break; |
| 467 | case READ_APB_REG: |
| 468 | LOG_INFO("ethosu_invoke READ_APB_REG\n"); |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 469 | ret = read_apb_reg(drv, data_ptr->driver_action_data); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 470 | data_ptr += DRIVER_ACTION_LENGTH_32_BIT_WORD; |
| 471 | break; |
| 472 | case DUMP_SHRAM: |
| 473 | LOG_INFO("ethosu_invoke DUMP_SHRAM\n"); |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 474 | ret = dump_shram(drv); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 475 | data_ptr += DRIVER_ACTION_LENGTH_32_BIT_WORD; |
| 476 | break; |
| 477 | case NOP: |
| 478 | LOG_INFO("ethosu_invoke NOP\n"); |
| 479 | data_ptr += DRIVER_ACTION_LENGTH_32_BIT_WORD; |
| 480 | break; |
| 481 | default: |
| 482 | LOG_ERR("ethosu_invoke UNSUPPORTED driver_action_command %d \n", data_ptr->driver_action_command); |
Bhavik Patel | e645fed | 2020-06-12 14:46:47 +0200 | [diff] [blame] | 483 | ret = -1; |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 484 | break; |
| 485 | } |
Bhavik Patel | e645fed | 2020-06-12 14:46:47 +0200 | [diff] [blame] | 486 | if (ret != 0) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 487 | { |
Bhavik Patel | e645fed | 2020-06-12 14:46:47 +0200 | [diff] [blame] | 488 | return_code = -1; |
| 489 | break; |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 490 | } |
| 491 | } |
Kristofer Jonsson | 2b201c3 | 2020-09-02 16:42:43 +0200 | [diff] [blame] | 492 | |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 493 | if (!drv->status_error && !drv->dev_power_always_on) |
Bhavik Patel | 5f8dad1 | 2020-09-30 09:06:52 +0200 | [diff] [blame] | 494 | { |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 495 | ethosu_save_pmu_counters(&drv->dev); |
Anton Moberg | 0a61429 | 2021-03-24 14:08:22 +0100 | [diff] [blame] | 496 | set_clock_and_power_request(drv, ETHOSU_INFERENCE_REQUEST, ETHOSU_CLOCK_Q_ENABLE, ETHOSU_POWER_Q_ENABLE); |
Bhavik Patel | 5f8dad1 | 2020-09-30 09:06:52 +0200 | [diff] [blame] | 497 | } |
Kristofer Jonsson | 2b201c3 | 2020-09-02 16:42:43 +0200 | [diff] [blame] | 498 | |
Bhavik Patel | e645fed | 2020-06-12 14:46:47 +0200 | [diff] [blame] | 499 | return return_code; |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 500 | } |
| 501 | |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 502 | void ethosu_abort_v2(struct ethosu_driver *drv) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 503 | { |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 504 | drv->abort_inference = true; |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 505 | } |
| 506 | |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 507 | void ethosu_set_power_mode_v2(struct ethosu_driver *drv, bool always_on) |
Anton Moberg | 8d65b6f | 2020-12-21 09:37:18 +0100 | [diff] [blame] | 508 | { |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 509 | drv->dev_power_always_on = always_on; |
Anton Moberg | 8d65b6f | 2020-12-21 09:37:18 +0100 | [diff] [blame] | 510 | |
| 511 | if (always_on) |
| 512 | { |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 513 | npu_axi_init(drv); |
| 514 | } |
| 515 | } |
| 516 | |
| 517 | int ethosu_register_driver(struct ethosu_driver *drv) |
| 518 | { |
| 519 | // Safeguard check for if driver is already registered |
| 520 | struct ethosu_driver *cur = registered_drivers; |
| 521 | while (cur != NULL) |
| 522 | { |
| 523 | if (cur == drv) |
| 524 | { |
| 525 | LOG_ERR("%s: NPU driver at address %p is already registered.\n", __FUNCTION__, drv); |
| 526 | return -1; |
| 527 | } |
| 528 | cur = cur->next; |
| 529 | } |
| 530 | |
| 531 | drv->next = registered_drivers; |
| 532 | // Designate new registered driver HEAD |
| 533 | registered_drivers = drv; |
| 534 | |
| 535 | LOG_INFO("%s: New NPU driver at address %p is registered.\n", __FUNCTION__, drv); |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 536 | return 0; |
| 537 | } |
| 538 | |
| 539 | int ethosu_deregister_driver(struct ethosu_driver *drv) |
| 540 | { |
| 541 | struct ethosu_driver *cur = registered_drivers; |
| 542 | struct ethosu_driver **prev = ®istered_drivers; |
| 543 | |
| 544 | while (cur != NULL) |
| 545 | { |
| 546 | if (cur == drv) |
| 547 | { |
| 548 | *prev = cur->next; |
| 549 | LOG_INFO("%s: NPU driver at address %p is deregistered.\n", __FUNCTION__, drv); |
| 550 | return 0; |
| 551 | } |
| 552 | |
| 553 | prev = &cur->next; |
| 554 | cur = cur->next; |
| 555 | } |
| 556 | |
| 557 | LOG_ERR("%s: NPU driver at address %p does not match a registered driver and therefore may not be deregistered.\n", |
| 558 | __FUNCTION__, |
| 559 | drv); |
Anton Moberg | df386e0 | 2021-02-02 11:26:48 +0100 | [diff] [blame] | 560 | |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 561 | return -1; |
| 562 | } |
| 563 | |
| 564 | struct ethosu_driver *ethosu_reserve_driver(void) |
| 565 | { |
Anton Moberg | df386e0 | 2021-02-02 11:26:48 +0100 | [diff] [blame] | 566 | struct ethosu_driver *drv = NULL; |
| 567 | |
| 568 | do |
| 569 | { |
Anton Moberg | dfed5fd | 2021-03-11 14:41:11 +0100 | [diff] [blame] | 570 | ethosu_mutex_lock(ethosu_mutex); |
Anton Moberg | df386e0 | 2021-02-02 11:26:48 +0100 | [diff] [blame] | 571 | drv = ethosu_find_and_reserve_driver(); |
Anton Moberg | dfed5fd | 2021-03-11 14:41:11 +0100 | [diff] [blame] | 572 | ethosu_mutex_unlock(ethosu_mutex); |
Anton Moberg | df386e0 | 2021-02-02 11:26:48 +0100 | [diff] [blame] | 573 | |
| 574 | if (drv != NULL) |
| 575 | { |
| 576 | break; |
| 577 | } |
| 578 | |
Anton Moberg | dfed5fd | 2021-03-11 14:41:11 +0100 | [diff] [blame] | 579 | LOG_INFO("%s - Waiting for driver \n", __FUNCTION__); |
| 580 | ethosu_semaphore_take(ethosu_semaphore); |
Anton Moberg | df386e0 | 2021-02-02 11:26:48 +0100 | [diff] [blame] | 581 | |
| 582 | } while (1); |
| 583 | |
| 584 | return drv; |
| 585 | } |
| 586 | |
| 587 | static struct ethosu_driver *ethosu_find_and_reserve_driver(void) |
| 588 | { |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 589 | struct ethosu_driver *drv = registered_drivers; |
| 590 | |
| 591 | while (drv != NULL) |
| 592 | { |
| 593 | if (!drv->reserved) |
| 594 | { |
| 595 | drv->reserved = true; |
| 596 | LOG_INFO("%s - Driver %p reserved.\n", __FUNCTION__, drv); |
| 597 | return drv; |
| 598 | } |
| 599 | drv = drv->next; |
| 600 | } |
| 601 | |
| 602 | LOG_INFO("%s: No available drivers.\n", __FUNCTION__, drv); |
| 603 | |
| 604 | return NULL; |
| 605 | } |
| 606 | |
| 607 | void ethosu_release_driver(struct ethosu_driver *drv) |
| 608 | { |
Anton Moberg | dfed5fd | 2021-03-11 14:41:11 +0100 | [diff] [blame] | 609 | ethosu_mutex_lock(ethosu_mutex); |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 610 | if (drv != NULL && drv->reserved) |
| 611 | { |
| 612 | drv->reserved = false; |
| 613 | LOG_INFO("%s - Driver %p released\n", __FUNCTION__, drv); |
Anton Moberg | dfed5fd | 2021-03-11 14:41:11 +0100 | [diff] [blame] | 614 | ethosu_semaphore_give(ethosu_semaphore); |
Anton Moberg | 8d65b6f | 2020-12-21 09:37:18 +0100 | [diff] [blame] | 615 | } |
Anton Moberg | dfed5fd | 2021-03-11 14:41:11 +0100 | [diff] [blame] | 616 | ethosu_mutex_unlock(ethosu_mutex); |
Anton Moberg | 8d65b6f | 2020-12-21 09:37:18 +0100 | [diff] [blame] | 617 | } |
| 618 | |
| 619 | static int ethosu_soft_reset_and_restore(struct ethosu_driver *drv) |
| 620 | { |
| 621 | |
| 622 | if (ETHOSU_SUCCESS != ethosu_soft_reset(&drv->dev)) |
| 623 | { |
| 624 | return -1; |
| 625 | } |
| 626 | |
Anton Moberg | 0a61429 | 2021-03-24 14:08:22 +0100 | [diff] [blame] | 627 | set_clock_and_power_request(drv, ETHOSU_INFERENCE_REQUEST, ETHOSU_CLOCK_Q_ENABLE, ETHOSU_POWER_Q_DISABLE); |
Anton Moberg | 8d65b6f | 2020-12-21 09:37:18 +0100 | [diff] [blame] | 628 | |
| 629 | npu_axi_init(drv); |
| 630 | ethosu_restore_pmu_config(&drv->dev); |
| 631 | |
| 632 | return 0; |
| 633 | } |
| 634 | |
Anton Moberg | 0a61429 | 2021-03-24 14:08:22 +0100 | [diff] [blame] | 635 | enum ethosu_error_codes set_clock_and_power_request(struct ethosu_driver *drv, |
| 636 | enum ethosu_request_clients client, |
| 637 | enum ethosu_clock_q_request clock_request, |
| 638 | enum ethosu_power_q_request power_request) |
| 639 | { |
| 640 | // Set clock request bit for client |
| 641 | if (clock_request == ETHOSU_CLOCK_Q_DISABLE) |
| 642 | { |
| 643 | drv->clock_request |= (1 << client); |
| 644 | } |
| 645 | else |
| 646 | { |
| 647 | drv->clock_request &= ~(1 << client); |
| 648 | } |
| 649 | // Get current clock request (ENABLE if both PMU and INFERENCE asks for clock request, else DISABLE) |
| 650 | clock_request = drv->clock_request == 0 ? ETHOSU_CLOCK_Q_ENABLE : ETHOSU_CLOCK_Q_DISABLE; |
| 651 | |
| 652 | // Set power request bit for client |
| 653 | if (power_request == ETHOSU_CLOCK_Q_DISABLE) |
| 654 | { |
| 655 | drv->power_request |= (1 << client); |
| 656 | } |
| 657 | else |
| 658 | { |
| 659 | drv->power_request &= ~(1 << client); |
| 660 | } |
| 661 | // Get current power request (ENABLE if both PMU and INFERENCE asks for power request, else DISABLE) |
| 662 | power_request = drv->power_request == 0 ? ETHOSU_POWER_Q_ENABLE : ETHOSU_POWER_Q_DISABLE; |
| 663 | // Set clock and power |
| 664 | enum ethosu_error_codes ret = ethosu_set_clock_and_power(&drv->dev, clock_request, power_request); |
| 665 | |
| 666 | return ret; |
| 667 | } |
| 668 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 669 | static int handle_optimizer_config(struct ethosu_driver *drv, struct opt_cfg_s *opt_cfg_p) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 670 | { |
| 671 | struct ethosu_config cfg; |
| 672 | struct ethosu_id id; |
| 673 | int return_code = 0; |
| 674 | |
| 675 | LOG_INFO("handle_optimizer_config:\n"); |
| 676 | LOG_INFO("Optimizer release nbr: %d patch: %d\n", opt_cfg_p->da_data.rel_nbr, opt_cfg_p->da_data.patch_nbr); |
Anton Moberg | b8bcf13 | 2021-03-29 10:02:25 +0200 | [diff] [blame^] | 677 | LOG_INFO("Optimizer config cmd_stream_version: %d macs_per_cc: %d shram_size: %d custom_dma: %d\n", |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 678 | opt_cfg_p->cmd_stream_version, |
| 679 | opt_cfg_p->macs_per_cc, |
Anton Moberg | b8bcf13 | 2021-03-29 10:02:25 +0200 | [diff] [blame^] | 680 | opt_cfg_p->shram_size, |
| 681 | opt_cfg_p->custom_dma); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 682 | LOG_INFO("Optimizer config Ethos-U version: %d.%d.%d\n", |
| 683 | opt_cfg_p->arch_major_rev, |
| 684 | opt_cfg_p->arch_minor_rev, |
| 685 | opt_cfg_p->arch_patch_rev); |
| 686 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 687 | (void)ethosu_get_config(&drv->dev, &cfg); |
| 688 | (void)ethosu_get_id(&drv->dev, &id); |
Anton Moberg | b8bcf13 | 2021-03-29 10:02:25 +0200 | [diff] [blame^] | 689 | LOG_INFO("Ethos-U config cmd_stream_version: %" PRIu32 " macs_per_cc: %" PRIu32 " shram_size: %" PRIu32 |
| 690 | " custom_dma: %" PRIu32 "\n", |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 691 | cfg.cmd_stream_version, |
| 692 | cfg.macs_per_cc, |
Anton Moberg | b8bcf13 | 2021-03-29 10:02:25 +0200 | [diff] [blame^] | 693 | cfg.shram_size, |
| 694 | cfg.custom_dma); |
Per Åstrand | 14ccfee | 2020-09-25 10:40:20 +0200 | [diff] [blame] | 695 | LOG_INFO("Ethos-U version: %" PRIu32 ".%" PRIu32 ".%" PRIu32 "\n", |
| 696 | id.arch_major_rev, |
| 697 | id.arch_minor_rev, |
| 698 | id.arch_patch_rev); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 699 | |
| 700 | if ((cfg.macs_per_cc != opt_cfg_p->macs_per_cc) || (cfg.shram_size != opt_cfg_p->shram_size) || |
Anton Moberg | b8bcf13 | 2021-03-29 10:02:25 +0200 | [diff] [blame^] | 701 | (cfg.cmd_stream_version != opt_cfg_p->cmd_stream_version) || (!cfg.custom_dma && opt_cfg_p->custom_dma)) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 702 | { |
| 703 | if (cfg.macs_per_cc != opt_cfg_p->macs_per_cc) |
| 704 | { |
Per Åstrand | 14ccfee | 2020-09-25 10:40:20 +0200 | [diff] [blame] | 705 | LOG_ERR("NPU config mismatch: npu.macs_per_cc=%" PRIu32 " optimizer.macs_per_cc=%d\n", |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 706 | cfg.macs_per_cc, |
| 707 | opt_cfg_p->macs_per_cc); |
| 708 | } |
| 709 | if (cfg.shram_size != opt_cfg_p->shram_size) |
| 710 | { |
Per Åstrand | 14ccfee | 2020-09-25 10:40:20 +0200 | [diff] [blame] | 711 | LOG_ERR("NPU config mismatch: npu.shram_size=%" PRIu32 " optimizer.shram_size=%d\n", |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 712 | cfg.shram_size, |
| 713 | opt_cfg_p->shram_size); |
| 714 | } |
| 715 | if (cfg.cmd_stream_version != opt_cfg_p->cmd_stream_version) |
| 716 | { |
Per Åstrand | 14ccfee | 2020-09-25 10:40:20 +0200 | [diff] [blame] | 717 | LOG_ERR("NPU config mismatch: npu.cmd_stream_version=%" PRIu32 " optimizer.cmd_stream_version=%d\n", |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 718 | cfg.cmd_stream_version, |
| 719 | opt_cfg_p->cmd_stream_version); |
| 720 | } |
Anton Moberg | b8bcf13 | 2021-03-29 10:02:25 +0200 | [diff] [blame^] | 721 | if (!cfg.custom_dma && opt_cfg_p->custom_dma) |
| 722 | { |
| 723 | LOG_ERR("NPU config mismatch: npu.custom_dma=%" PRIu32 " optimize.custom_dma=%d\n", |
| 724 | cfg.custom_dma, |
| 725 | opt_cfg_p->custom_dma); |
| 726 | } |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 727 | return_code = -1; |
| 728 | } |
| 729 | |
Douglas Troha | 91e0be5 | 2021-01-18 13:57:38 +0100 | [diff] [blame] | 730 | if ((id.arch_major_rev != opt_cfg_p->arch_major_rev) || (id.arch_minor_rev < opt_cfg_p->arch_minor_rev)) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 731 | { |
Per Åstrand | 14ccfee | 2020-09-25 10:40:20 +0200 | [diff] [blame] | 732 | LOG_ERR("NPU arch mismatch: npu.arch=%" PRIu32 ".%" PRIu32 ".%" PRIu32 " optimizer.arch=%d.%d.%d\n", |
Bhavik Patel | 790ef36 | 2020-06-03 10:05:28 +0200 | [diff] [blame] | 733 | id.arch_major_rev, |
| 734 | id.arch_minor_rev, |
| 735 | id.arch_patch_rev, |
| 736 | opt_cfg_p->arch_major_rev, |
| 737 | opt_cfg_p->arch_minor_rev, |
| 738 | opt_cfg_p->arch_patch_rev); |
| 739 | return_code = -1; |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 740 | } |
| 741 | |
| 742 | #if !defined(LOG_ENABLED) |
| 743 | UNUSED(opt_cfg_p); |
| 744 | #endif |
| 745 | return return_code; |
| 746 | } |
| 747 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 748 | static void npu_axi_init(struct ethosu_driver *drv) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 749 | { |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 750 | ethosu_set_qconfig(&drv->dev, NPU_QCONFIG); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 751 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 752 | ethosu_set_regioncfg(&drv->dev, 0, NPU_REGIONCFG_0); |
| 753 | ethosu_set_regioncfg(&drv->dev, 1, NPU_REGIONCFG_1); |
| 754 | ethosu_set_regioncfg(&drv->dev, 2, NPU_REGIONCFG_2); |
| 755 | ethosu_set_regioncfg(&drv->dev, 3, NPU_REGIONCFG_3); |
| 756 | ethosu_set_regioncfg(&drv->dev, 4, NPU_REGIONCFG_4); |
| 757 | ethosu_set_regioncfg(&drv->dev, 5, NPU_REGIONCFG_5); |
| 758 | ethosu_set_regioncfg(&drv->dev, 6, NPU_REGIONCFG_6); |
| 759 | ethosu_set_regioncfg(&drv->dev, 7, NPU_REGIONCFG_7); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 760 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 761 | (void)ethosu_set_axi_limit0(&drv->dev, |
| 762 | AXI_LIMIT0_MAX_BEATS_BYTES, |
Bhavik Patel | 790ef36 | 2020-06-03 10:05:28 +0200 | [diff] [blame] | 763 | AXI_LIMIT0_MEM_TYPE, |
| 764 | AXI_LIMIT0_MAX_OUTSTANDING_READS, |
| 765 | AXI_LIMIT0_MAX_OUTSTANDING_WRITES); |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 766 | (void)ethosu_set_axi_limit1(&drv->dev, |
| 767 | AXI_LIMIT1_MAX_BEATS_BYTES, |
Bhavik Patel | 790ef36 | 2020-06-03 10:05:28 +0200 | [diff] [blame] | 768 | AXI_LIMIT1_MEM_TYPE, |
| 769 | AXI_LIMIT1_MAX_OUTSTANDING_READS, |
| 770 | AXI_LIMIT1_MAX_OUTSTANDING_WRITES); |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 771 | (void)ethosu_set_axi_limit2(&drv->dev, |
| 772 | AXI_LIMIT2_MAX_BEATS_BYTES, |
Bhavik Patel | 790ef36 | 2020-06-03 10:05:28 +0200 | [diff] [blame] | 773 | AXI_LIMIT2_MEM_TYPE, |
| 774 | AXI_LIMIT2_MAX_OUTSTANDING_READS, |
| 775 | AXI_LIMIT2_MAX_OUTSTANDING_WRITES); |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 776 | (void)ethosu_set_axi_limit3(&drv->dev, |
| 777 | AXI_LIMIT3_MAX_BEATS_BYTES, |
Bhavik Patel | 790ef36 | 2020-06-03 10:05:28 +0200 | [diff] [blame] | 778 | AXI_LIMIT3_MEM_TYPE, |
| 779 | AXI_LIMIT3_MAX_OUTSTANDING_READS, |
| 780 | AXI_LIMIT3_MAX_OUTSTANDING_WRITES); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 781 | } |
| 782 | |
Per Åstrand | 3c8afcc | 2020-10-20 10:29:59 +0200 | [diff] [blame] | 783 | /* Default implementation to flush the data cache. Override if available on the targeted device. |
| 784 | * Passing NULL as p argument expects the whole cache to be flushed. |
| 785 | */ |
| 786 | void __attribute__((weak)) ethosu_flush_dcache(uint32_t *p, size_t bytes) |
| 787 | { |
| 788 | (void)p; |
| 789 | (void)bytes; |
| 790 | } |
| 791 | |
| 792 | /* Default implementation to invalidate the data cache. Override if available on the targeted device. |
| 793 | * Passing NULL as p argument expects the whole cache to be flushed. |
| 794 | */ |
| 795 | void __attribute__((weak)) ethosu_invalidate_dcache(uint32_t *p, size_t bytes) |
| 796 | { |
| 797 | (void)p; |
| 798 | (void)bytes; |
| 799 | } |
| 800 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 801 | static int handle_command_stream(struct ethosu_driver *drv, |
| 802 | const uint8_t *cmd_stream, |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 803 | const int cms_length, |
| 804 | const uint64_t *base_addr, |
Per Åstrand | 3c8afcc | 2020-10-20 10:29:59 +0200 | [diff] [blame] | 805 | const size_t *base_addr_size, |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 806 | const int num_base_addr) |
| 807 | { |
Kristofer Jonsson | c6e7a1f | 2020-11-24 09:20:14 +0100 | [diff] [blame] | 808 | uint32_t qread = 0; |
| 809 | uint32_t cms_bytes = cms_length * BYTES_IN_32_BITS; |
| 810 | ptrdiff_t cmd_stream_ptr = (ptrdiff_t)cmd_stream; |
| 811 | |
Kristofer Jonsson | 125429a | 2020-08-20 16:52:23 +0200 | [diff] [blame] | 812 | LOG_INFO("handle_command_stream: cmd_stream=%p, cms_length %d\n", cmd_stream, cms_length); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 813 | |
Bhavik Patel | bf7ae63 | 2020-06-11 21:00:16 +0200 | [diff] [blame] | 814 | if (0 != ((ptrdiff_t)cmd_stream & MASK_16_BYTE_ALIGN)) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 815 | { |
Bhavik Patel | bf7ae63 | 2020-06-11 21:00:16 +0200 | [diff] [blame] | 816 | LOG_ERR("Error: Command stream addr %p not aligned to 16 bytes\n", cmd_stream); |
| 817 | return -1; |
| 818 | } |
| 819 | |
| 820 | bool base_addr_invalid = false; |
| 821 | for (int i = 0; i < num_base_addr; i++) |
| 822 | { |
| 823 | if (0 != (base_addr[i] & MASK_16_BYTE_ALIGN)) |
| 824 | { |
Per Åstrand | 14ccfee | 2020-09-25 10:40:20 +0200 | [diff] [blame] | 825 | LOG_ERR("Error: Base addr %d: 0x%llx not aligned to 16 bytes\n", i, base_addr[i]); |
Bhavik Patel | bf7ae63 | 2020-06-11 21:00:16 +0200 | [diff] [blame] | 826 | base_addr_invalid = true; |
| 827 | } |
| 828 | } |
Kristofer Jonsson | c6e7a1f | 2020-11-24 09:20:14 +0100 | [diff] [blame] | 829 | |
Bhavik Patel | bf7ae63 | 2020-06-11 21:00:16 +0200 | [diff] [blame] | 830 | if (base_addr_invalid) |
| 831 | { |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 832 | return -1; |
| 833 | } |
Kristofer Jonsson | c6e7a1f | 2020-11-24 09:20:14 +0100 | [diff] [blame] | 834 | |
Per Åstrand | 3c8afcc | 2020-10-20 10:29:59 +0200 | [diff] [blame] | 835 | /* Flush the cache if available on our CPU. |
| 836 | * The upcasting to uin32_t* is ok since the pointer never is dereferenced. |
| 837 | * The base_addr_size is null if invoking from prior to invoke_V2, in that case |
| 838 | * the whole cache is being flushed. |
| 839 | */ |
| 840 | |
| 841 | if (base_addr_size != NULL) |
| 842 | { |
Kristofer Jonsson | c6e7a1f | 2020-11-24 09:20:14 +0100 | [diff] [blame] | 843 | ethosu_flush_dcache((uint32_t *)cmd_stream_ptr, cms_bytes); |
Per Åstrand | 3c8afcc | 2020-10-20 10:29:59 +0200 | [diff] [blame] | 844 | for (int i = 0; i < num_base_addr; i++) |
| 845 | { |
Bhavik Patel | 033bb1b | 2020-12-17 15:33:33 +0100 | [diff] [blame] | 846 | ethosu_flush_dcache((uint32_t *)(uintptr_t)base_addr[i], base_addr_size[i]); |
Per Åstrand | 3c8afcc | 2020-10-20 10:29:59 +0200 | [diff] [blame] | 847 | } |
| 848 | } |
| 849 | else |
| 850 | { |
| 851 | ethosu_flush_dcache(NULL, 0); |
| 852 | } |
| 853 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 854 | if (ETHOSU_SUCCESS != ethosu_run_command_stream(&drv->dev, cmd_stream, cms_bytes, base_addr, num_base_addr)) |
Bhavik Patel | 790ef36 | 2020-06-03 10:05:28 +0200 | [diff] [blame] | 855 | { |
| 856 | return -1; |
| 857 | } |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 858 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 859 | wait_for_irq(drv); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 860 | |
Bhavik Patel | 5f8dad1 | 2020-09-30 09:06:52 +0200 | [diff] [blame] | 861 | if (drv->status_error) |
| 862 | { |
| 863 | return -1; |
| 864 | } |
| 865 | |
Per Åstrand | 3c8afcc | 2020-10-20 10:29:59 +0200 | [diff] [blame] | 866 | if (base_addr_size != NULL) |
| 867 | { |
| 868 | for (int i = 0; i < num_base_addr; i++) |
| 869 | { |
Bhavik Patel | 033bb1b | 2020-12-17 15:33:33 +0100 | [diff] [blame] | 870 | ethosu_invalidate_dcache((uint32_t *)(uintptr_t)base_addr[i], base_addr_size[i]); |
Per Åstrand | 3c8afcc | 2020-10-20 10:29:59 +0200 | [diff] [blame] | 871 | } |
| 872 | } |
| 873 | else |
| 874 | { |
| 875 | ethosu_invalidate_dcache(NULL, 0); |
| 876 | } |
| 877 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 878 | (void)ethosu_get_qread(&drv->dev, &qread); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 879 | if (qread != cms_bytes) |
| 880 | { |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 881 | LOG_WARN( |
Per Åstrand | 14ccfee | 2020-09-25 10:40:20 +0200 | [diff] [blame] | 882 | "Failure: IRQ received but qread (%" PRIu32 ") not at end of stream (%" PRIu32 ").\n", qread, cms_bytes); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 883 | return -1; |
| 884 | } |
| 885 | |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 886 | return 0; |
| 887 | } |
| 888 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 889 | static int read_apb_reg(struct ethosu_driver *drv, uint16_t da_data) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 890 | { |
| 891 | uint32_t *reg_p; |
| 892 | uint32_t start_address = (uint32_t)(da_data & APB_START_ADDR_MASK); |
| 893 | uint16_t num_reg = (da_data >> APB_NUM_REG_BIT_SHIFT) + 1; |
| 894 | |
| 895 | reg_p = (uint32_t *)malloc(num_reg * sizeof(uint32_t)); |
| 896 | if (reg_p == NULL) |
| 897 | { |
| 898 | LOG_INFO("read_apb_reg, Error! memory not allocated."); |
| 899 | return -1; |
| 900 | } |
| 901 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 902 | if (ETHOSU_SUCCESS == ethosu_read_apb_reg(&drv->dev, start_address, num_reg, reg_p)) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 903 | { |
| 904 | for (int i = 0; i < num_reg; i++) |
| 905 | { |
Per Åstrand | 14ccfee | 2020-09-25 10:40:20 +0200 | [diff] [blame] | 906 | LOG_INFO( |
| 907 | "NPU_REG ADDR 0x%04" PRIu32 " = 0x%08" PRIu32 "\n", (start_address + (i * BYTES_IN_32_BITS)), reg_p[i]); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 908 | } |
| 909 | } |
| 910 | else |
| 911 | { |
| 912 | free(reg_p); |
| 913 | return -1; |
| 914 | } |
| 915 | |
| 916 | free(reg_p); |
| 917 | return 0; |
| 918 | } |
| 919 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 920 | static int dump_shram(struct ethosu_driver *drv) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 921 | { |
| 922 | struct ethosu_config cfg; |
| 923 | uint32_t *shram_p; |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 924 | (void)ethosu_get_config(&drv->dev, &cfg); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 925 | |
Per Åstrand | 14ccfee | 2020-09-25 10:40:20 +0200 | [diff] [blame] | 926 | LOG_INFO("dump_shram size = %" PRIu32 " KB\n", cfg.shram_size); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 927 | |
| 928 | shram_p = (uint32_t *)malloc(BYTES_1KB); |
| 929 | if (shram_p == NULL) |
| 930 | { |
| 931 | LOG_ERR("read_shram, Error! memory not allocated."); |
| 932 | return -1; |
| 933 | } |
| 934 | |
| 935 | for (uint32_t i = 0; i < cfg.shram_size; i++) |
| 936 | { |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 937 | ethosu_get_shram_data(&drv->dev, i, (uint32_t *)shram_p); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 938 | // Output 1KB of SHRAM |
Per Åstrand | 14ccfee | 2020-09-25 10:40:20 +0200 | [diff] [blame] | 939 | LOG_INFO("***SHRAM SECTION %" PRIu32 "***\n", i); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 940 | for (int j = 0; j < (BYTES_1KB / BYTES_IN_32_BITS); j++) |
| 941 | { |
Per Åstrand | 14ccfee | 2020-09-25 10:40:20 +0200 | [diff] [blame] | 942 | LOG_INFO("[0x%04" PRIx32 "] %" PRIx32 "\n", (i * 1024 + j * 4), shram_p[j]); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 943 | } |
| 944 | } |
| 945 | free(shram_p); |
| 946 | |
| 947 | return 0; |
| 948 | } |
| 949 | |
| 950 | typedef struct |
| 951 | { |
| 952 | int number; |
| 953 | const char *name; |
| 954 | } name_lookup_t; |
| 955 | |
| 956 | static const name_lookup_t npu_reg_name_tbl[] = { |
| 957 | {0x200, "KERNEL_X"}, |
| 958 | {0x204, "KERNEL_Y"}, |
| 959 | {0x208, "KERNEL_W_M1"}, |
| 960 | {0x20C, "KERNEL_H_M1"}, |
| 961 | {0x210, "OFM_CBLK_WIDTH_M1"}, |
| 962 | {0x214, "OFM_CBLK_HEIGHT_M1"}, |
| 963 | {0x218, "OFM_CBLK_DEPTH_M1"}, |
| 964 | {0x21c, "IFM_CBLK_DEPTH_M1"}, |
| 965 | {0x220, "OFM_X"}, |
| 966 | {0x224, "OFM_Y"}, |
| 967 | {0x228, "OFM_Z"}, |
| 968 | {0x22C, "IFM_Z"}, |
| 969 | {0x230, "PAD_TOP"}, |
| 970 | {0x234, "PAD_LEFT"}, |
| 971 | {0x238, "IFM_CBLK_WIDTH"}, |
| 972 | {0x23C, "IFM_CBLK_HEIGHT"}, |
| 973 | {0x240, "DMA_IFM_SRC"}, |
| 974 | {0x244, "DMA_IFM_SRC_HI"}, |
| 975 | {0x248, "DMA_IFM_DST"}, |
| 976 | {0x24c, "DMA_OFM_SRC"}, |
| 977 | {0x250, "DMA_OFM_DST"}, |
| 978 | {0x254, "DMA_OFM_DST_HI"}, |
| 979 | {0x258, "DMA_WEIGHT_SRC"}, |
| 980 | {0x25c, "DMA_WEIGHT_SRC_HI"}, |
| 981 | {0x260, "DMA_CMD_SRC"}, |
| 982 | {0x264, "DMA_CMD_SRC_HI"}, |
| 983 | {0x268, "DMA_CMD_SIZE"}, |
| 984 | {0x26c, "DMA_M2M_SRC"}, |
| 985 | {0x270, "DMA_M2M_SRC_HI"}, |
| 986 | {0x274, "DMA_M2M_DST"}, |
| 987 | {0x278, "DMA_M2M_DST_HI"}, |
| 988 | {0x27c, "CURRENT_QREAD"}, |
| 989 | {0x280, "DMA_SCALE_SRC"}, |
| 990 | {0x284, "DMA_SCALE_SRC_HI"}, |
| 991 | {0x2BC, "CURRENT_CMD"}, |
| 992 | {0x800, "IFM_PAD_TOP"}, |
| 993 | {0x804, "IFM_PAD_LEFT"}, |
| 994 | {0x808, "IFM_PAD_RIGHT"}, |
| 995 | {0x80C, "IFM_PAD_BOTTOM"}, |
| 996 | {0x810, "IFM_DEPTH_M1"}, |
| 997 | {0x814, "IFM_PRECISION"}, |
| 998 | {0x81C, "IFM_UPSCALE"}, |
| 999 | {0x824, "IFM_ZERO_POINT"}, |
| 1000 | {0x828, "IFM_WIDTH0_M1"}, |
| 1001 | {0x82C, "IFM_HEIGHT0_M1"}, |
| 1002 | {0x830, "IFM_HEIGHT1_M1"}, |
| 1003 | {0x834, "IFM_IB_END"}, |
| 1004 | {0x83C, "IFM_REGION"}, |
| 1005 | {0x844, "OFM_WIDTH_M1"}, |
| 1006 | {0x848, "OFM_HEIGHT_M1"}, |
| 1007 | {0x84C, "OFM_DEPTH_M1"}, |
| 1008 | {0x850, "OFM_PRECISION"}, |
| 1009 | {0x854, "OFM_BLK_WIDTH_M1"}, |
| 1010 | {0x858, "OFM_BLK_HEIGHT_M1"}, |
| 1011 | {0x85C, "OFM_BLK_DEPTH_M1"}, |
| 1012 | {0x860, "OFM_ZERO_POINT"}, |
| 1013 | {0x868, "OFM_WIDTH0_M1"}, |
| 1014 | {0x86C, "OFM_HEIGHT0_M1"}, |
| 1015 | {0x870, "OFM_HEIGHT1_M1"}, |
| 1016 | {0x87C, "OFM_REGION"}, |
| 1017 | {0x880, "KERNEL_WIDTH_M1"}, |
| 1018 | {0x884, "KERNEL_HEIGHT_M1"}, |
| 1019 | {0x888, "KERNEL_STRIDE"}, |
| 1020 | {0x88C, "PARALLEL_MODE"}, |
| 1021 | {0x890, "ACC_FORMAT"}, |
| 1022 | {0x894, "ACTIVATION"}, |
| 1023 | {0x898, "ACTIVATION_MIN"}, |
| 1024 | {0x89C, "ACTIVATION_MAX"}, |
| 1025 | {0x8A0, "WEIGHT_REGION"}, |
| 1026 | {0x8A4, "SCALE_REGION"}, |
| 1027 | {0x8B4, "AB_START"}, |
| 1028 | {0x8BC, "BLOCKDEP"}, |
| 1029 | {0x8C0, "DMA0_SRC_REGION"}, |
| 1030 | {0x8C4, "DMA0_DST_REGION"}, |
| 1031 | {0x8C8, "DMA0_SIZE0"}, |
| 1032 | {0x8CC, "DMA0_SIZE1"}, |
| 1033 | {0x900, "IFM2_BROADCAST"}, |
| 1034 | {0x904, "IFM2_SCALAR"}, |
| 1035 | {0x924, "IFM2_ZERO_POINT"}, |
| 1036 | {0x928, "IFM2_WIDTH0_M1"}, |
| 1037 | {0x92C, "IFM2_HEIGHT0_M1"}, |
| 1038 | {0x930, "IFM2_HEIGHT1_M1"}, |
| 1039 | {0x934, "IFM2_IB_START"}, |
| 1040 | {0x93C, "IFM2_REGION"}, |
| 1041 | {0xA00, "IFM_BASE0"}, |
| 1042 | {0xA04, "IFM_BASE0_HI"}, |
| 1043 | {0xA08, "IFM_BASE1"}, |
| 1044 | {0xA0C, "IFM_BASE1_HI"}, |
| 1045 | {0xA10, "IFM_BASE2"}, |
| 1046 | {0xA14, "IFM_BASE2_HI"}, |
| 1047 | {0xA18, "IFM_BASE3"}, |
| 1048 | {0xA1C, "IFM_BASE3_HI"}, |
| 1049 | {0xA20, "IFM_STRIDE_X"}, |
| 1050 | {0xA24, "IFM_STRIDE_X_HI"}, |
| 1051 | {0xA28, "IFM_STRIDE_Y"}, |
| 1052 | {0xA2C, "IFM_STRIDE_Y_HI"}, |
| 1053 | {0xA30, "IFM_STRIDE_C"}, |
| 1054 | {0xA34, "IFM_STRIDE_C_HI"}, |
| 1055 | {0xA40, "OFM_BASE0"}, |
| 1056 | {0xA44, "OFM_BASE0_HI"}, |
| 1057 | {0xA48, "OFM_BASE1"}, |
| 1058 | {0xA4C, "OFM_BASE1_HI"}, |
| 1059 | {0xA50, "OFM_BASE2"}, |
| 1060 | {0xA54, "OFM_BASE2_HI"}, |
| 1061 | {0xA58, "OFM_BASE3"}, |
| 1062 | {0xA5C, "OFM_BASE3_HI"}, |
| 1063 | {0xA60, "OFM_STRIDE_X"}, |
| 1064 | {0xA64, "OFM_STRIDE_X_HI"}, |
| 1065 | {0xA68, "OFM_STRIDE_Y"}, |
| 1066 | {0xA6C, "OFM_STRIDE_Y_HI"}, |
| 1067 | {0xA70, "OFM_STRIDE_C"}, |
| 1068 | {0xA74, "OFM_STRIDE_C_HI"}, |
| 1069 | {0xA80, "WEIGHT_BASE"}, |
| 1070 | {0xA84, "WEIGHT_BASE_HI"}, |
| 1071 | {0xA88, "WEIGHT_LENGTH"}, |
| 1072 | {0xA8C, "WEIGHT_LENGTH_HI"}, |
| 1073 | {0xA90, "SCALE_BASE"}, |
| 1074 | {0xA94, "SCALE_BASE_HI"}, |
| 1075 | {0xA98, "SCALE_LENGTH"}, |
| 1076 | {0xAA0, "OFM_SCALE"}, |
| 1077 | {0xAA4, "OFM_SCALE_SHIFT"}, |
| 1078 | {0xAA8, "OPA_SCALE "}, |
| 1079 | {0xAB0, "OPB_SCALE"}, |
| 1080 | {0xAC0, "DMA0_SRC"}, |
| 1081 | {0xAC4, "DMA0_SRC_HI"}, |
| 1082 | {0xAC8, "DMA0_DST"}, |
| 1083 | {0xACC, "DMA0_DST_HI"}, |
| 1084 | {0xAD0, "DMA0_LEN"}, |
| 1085 | {0xAD4, "DMA0_LEN_HI"}, |
| 1086 | {0xAD8, "DMA0_SKIP0"}, |
| 1087 | {0xADC, "DMA0_SKIP0_HI"}, |
| 1088 | {0xAE0, "DMA0_SKIP1"}, |
| 1089 | {0xAE4, "DMA0_SKIP1_HI"}, |
| 1090 | {0xB00, "IFM2_BASE0"}, |
| 1091 | {0xB04, "IFM2_BASE0_HI"}, |
| 1092 | {0xB08, "IFM2_BASE1"}, |
| 1093 | {0xB0C, "IFM2_BASE1_HI"}, |
| 1094 | {0xB10, "IFM2_BASE2"}, |
| 1095 | {0xB14, "IFM2_BASE2_HI"}, |
| 1096 | {0xB18, "IFM2_BASE3"}, |
| 1097 | {0xB1C, "IFM2_BASE3_HI"}, |
| 1098 | {0xB20, "IFM2_STRIDE_X"}, |
| 1099 | {0xB24, "IFM2_STRIDE_X_HI"}, |
| 1100 | {0xB28, "IFM2_STRIDE_Y"}, |
| 1101 | {0xB2C, "IFM2_STRIDE_Y_HI"}, |
| 1102 | {0xB30, "IFM2_STRIDE_C"}, |
| 1103 | {0xB34, "IFM2_STRIDE_C_HI"}, |
| 1104 | {0xB40, "WEIGHT1_BASE"}, |
| 1105 | {0xB44, "WEIGHT1_BASE_HI"}, |
| 1106 | {0xB48, "WEIGHT1_LENGTH"}, |
| 1107 | {0xB4C, "WEIGHT1_LENGTH_HI"}, |
| 1108 | {0xB50, "SCALE1_BASE"}, |
| 1109 | {0xB54, "SCALE1_BASE_HI"}, |
| 1110 | {0xB58, "SCALE1_LENGTH"}, |
| 1111 | }; |
| 1112 | |
| 1113 | static const char *lookup_name(const name_lookup_t *lookup_table, int lookup_table_count, int find) |
| 1114 | { |
| 1115 | int n; |
| 1116 | for (n = 0; n < lookup_table_count; n++) |
| 1117 | { |
| 1118 | if (lookup_table[n].number == find) |
| 1119 | { |
| 1120 | return lookup_table[n].name; |
| 1121 | } |
| 1122 | } |
| 1123 | // Not found |
| 1124 | return 0; |
| 1125 | } |
| 1126 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 1127 | static void dump_npu_register(struct ethosu_driver *drv, int npu_reg, int npu_reg_end) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 1128 | { |
| 1129 | unsigned int reg_val; |
| 1130 | const char *reg_name; |
| 1131 | int npu_reg_name_tbl_count = sizeof(npu_reg_name_tbl) / sizeof(npu_reg_name_tbl[0]); |
| 1132 | |
| 1133 | LOG_INFO("dump_register %X - %X\n", npu_reg, npu_reg_end); |
| 1134 | for (; npu_reg <= npu_reg_end; npu_reg += sizeof(int)) |
| 1135 | { |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 1136 | reg_val = ethosu_read_reg(&drv->dev, npu_reg); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 1137 | reg_name = lookup_name(npu_reg_name_tbl, npu_reg_name_tbl_count, npu_reg); |
| 1138 | LOG_INFO("[0x%.4X] 0x%.8X\t%s\n", npu_reg, reg_val, (reg_name) ? reg_name : ""); |
| 1139 | } |
| 1140 | } |
| 1141 | |
| 1142 | static const name_lookup_t cmd0_name_tbl[] = { |
| 1143 | {0x000, "NPU_OP_STOP"}, |
| 1144 | {0x001, "NPU_OP_IRQ"}, |
| 1145 | {0x002, "NPU_OP_CONV"}, |
| 1146 | {0x003, "NPU_OP_DEPTHWISE"}, |
| 1147 | {0x004, "NPU_OP_VECTOR_PROD"}, |
| 1148 | {0x005, "NPU_OP_POOL"}, |
| 1149 | {0x006, "NPU_OP_ELEMENTWISE"}, |
| 1150 | {0x010, "NPU_OP_DMA_START"}, |
| 1151 | {0x011, "NPU_OP_DMA_WAIT"}, |
| 1152 | {0x012, "NPU_OP_KERNEL_WAIT"}, |
| 1153 | {0x100, "NPU_SET_IFM_PAD_TOP"}, |
| 1154 | {0x101, "NPU_SET_IFM_PAD_LEFT"}, |
| 1155 | {0x102, "NPU_SET_IFM_PAD_RIGHT"}, |
| 1156 | {0x103, "NPU_SET_IFM_PAD_BOTTOM"}, |
| 1157 | {0x104, "NPU_SET_IFM_DEPTH_M1"}, |
| 1158 | {0x105, "NPU_SET_IFM_PRECISION"}, |
| 1159 | {0x107, "NPU_SET_IFM_UPSCALE"}, |
| 1160 | {0x109, "NPU_SET_IFM_ZERO_POINT"}, |
| 1161 | {0x10A, "NPU_SET_IFM_WIDTH0_M1"}, |
| 1162 | {0x10B, "NPU_SET_IFM_HEIGHT0_M1"}, |
| 1163 | {0x10C, "NPU_SET_IFM_HEIGHT1_M1"}, |
| 1164 | {0x10D, "NPU_SET_IFM_IB_END"}, |
| 1165 | {0x10F, "NPU_SET_IFM_REGION"}, |
| 1166 | {0x110, "NPU_SET_OFM_BATCH_SIZE_M1"}, |
| 1167 | {0x111, "NPU_SET_OFM_WIDTH_M1"}, |
| 1168 | {0x112, "NPU_SET_OFM_HEIGHT_M1"}, |
| 1169 | {0x113, "NPU_SET_OFM_DEPTH_M1"}, |
| 1170 | {0x114, "NPU_SET_OFM_PRECISION"}, |
| 1171 | {0x115, "NPU_SET_OFM_BLK_WIDTH_M1"}, |
| 1172 | {0x116, "NPU_SET_OFM_BLK_HEIGHT_M1"}, |
| 1173 | {0x117, "NPU_SET_OFM_BLK_DEPTH_M1"}, |
| 1174 | {0x118, "NPU_SET_OFM_ZERO_POINT"}, |
| 1175 | {0x11A, "NPU_SET_OFM_WIDTH0_M1"}, |
| 1176 | {0x11B, "NPU_SET_OFM_HEIGHT0_M1"}, |
| 1177 | {0x11C, "NPU_SET_OFM_HEIGHT1_M1"}, |
| 1178 | {0x11F, "NPU_SET_OFM_REGION"}, |
| 1179 | {0x120, "NPU_SET_KERNEL_WIDTH_M1"}, |
| 1180 | {0x121, "NPU_SET_KERNEL_HEIGHT_M1"}, |
| 1181 | {0x122, "NPU_SET_KERNEL_STRIDE"}, |
| 1182 | {0x124, "NPU_SET_ACC_FORMAT"}, |
| 1183 | {0x125, "NPU_SET_ACTIVATION"}, |
| 1184 | {0x126, "NPU_SET_ACTIVATION_MIN"}, |
| 1185 | {0x127, "NPU_SET_ACTIVATION_MAX"}, |
| 1186 | {0x128, "NPU_SET_WEIGHT_REGION"}, |
| 1187 | {0x129, "NPU_SET_SCALE_REGION"}, |
| 1188 | {0x12D, "NPU_SET_AB_START"}, |
| 1189 | {0x12F, "NPU_SET_BLOCKDEP"}, |
| 1190 | {0x130, "NPU_SET_DMA0_SRC_REGION"}, |
| 1191 | {0x131, "NPU_SET_DMA0_DST_REGION"}, |
| 1192 | {0x180, "NPU_SET_IFM2_BROADCAST"}, |
| 1193 | {0x181, "NPU_SET_IFM2_SCALAR"}, |
| 1194 | {0x185, "NPU_SET_IFM2_PRECISION"}, |
| 1195 | {0x189, "NPU_SET_IFM2_ZERO_POINT"}, |
| 1196 | {0x18A, "NPU_SET_IFM2_WIDTH0_M1"}, |
| 1197 | {0x18B, "NPU_SET_IFM2_HEIGHT0_M1"}, |
| 1198 | {0x18C, "NPU_SET_IFM2_HEIGHT1_M1"}, |
| 1199 | {0x18D, "NPU_SET_IFM2_IB_START"}, |
| 1200 | {0x18F, "NPU_SET_IFM2_REGION"}, |
| 1201 | }; |
| 1202 | |
| 1203 | static const name_lookup_t cmd1_name_tbl[] = { |
| 1204 | {0x000, "NPU_SET_IFM_BASE0"}, {0x001, "NPU_SET_IFM_BASE1"}, {0x002, "NPU_SET_IFM_BASE2"}, |
| 1205 | {0x003, "NPU_SET_IFM_BASE3"}, {0x004, "NPU_SET_IFM_STRIDE_X"}, {0x005, "NPU_SET_IFM_STRIDE_Y"}, |
| 1206 | {0x006, "NPU_SET_IFM_STRIDE_C"}, {0x007, "NPU_SET_IFM_STRIDE_N"}, {0x010, "NPU_SET_OFM_BASE0"}, |
| 1207 | {0x011, "NPU_SET_OFM_BASE1"}, {0x012, "NPU_SET_OFM_BASE2"}, {0x013, "NPU_SET_OFM_BASE3"}, |
| 1208 | {0x014, "NPU_SET_OFM_STRIDE_X"}, {0x015, "NPU_SET_OFM_STRIDE_Y"}, {0x016, "NPU_SET_OFM_STRIDE_C"}, |
| 1209 | {0x017, "NPU_SET_OFM_STRIDE_N"}, {0x020, "NPU_SET_WEIGHT_BASE"}, {0x021, "NPU_SET_WEIGHT_LENGTH"}, |
| 1210 | {0x022, "NPU_SET_SCALE_BASE"}, {0x023, "NPU_SET_SCALE_LENGTH"}, {0x024, "NPU_SET_OFM_SCALE"}, |
| 1211 | {0x025, "NPU_SET_OPA_SCALE"}, {0x026, "NPU_SET_OPB_SCALE"}, {0x030, "NPU_SET_DMA0_SRC"}, |
| 1212 | {0x031, "NPU_SET_DMA0_DST"}, {0x032, "NPU_SET_DMA0_LEN"}, {0x080, "NPU_SET_IFM2_BASE0"}, |
| 1213 | {0x081, "NPU_SET_IFM2_BASE1"}, {0x082, "NPU_SET_IFM2_BASE2"}, {0x083, "NPU_SET_IFM2_BASE3"}, |
| 1214 | {0x084, "NPU_SET_IFM2_STRIDE_X"}, {0x085, "NPU_SET_IFM2_STRIDE_Y"}, {0x086, "NPU_SET_IFM2_STRIDE_C"}, |
| 1215 | }; |
| 1216 | |
| 1217 | static void dump_command_stream(const uint32_t *cmd_stream, const int cms_length, int qread) |
| 1218 | { |
| 1219 | int n; |
| 1220 | int offset; |
| 1221 | uint32_t cmd_val; |
| 1222 | const uint8_t *cmd_ptr; |
| 1223 | const char *cmd_name; |
| 1224 | int cmd0_name_tbl_count = sizeof(cmd0_name_tbl) / sizeof(cmd0_name_tbl[0]); |
| 1225 | int cmd1_name_tbl_count = sizeof(cmd1_name_tbl) / sizeof(cmd1_name_tbl[0]); |
| 1226 | |
| 1227 | LOG_INFO("dump_command_stream cmd_stream = 0x%8p cms_length = %d\n", cmd_stream, cms_length); |
| 1228 | for (n = 0; n < cms_length; n++) |
| 1229 | { |
| 1230 | // Offset |
| 1231 | offset = n * sizeof(int); |
| 1232 | LOG_INFO("[%.4d] ", offset); |
| 1233 | // Command |
| 1234 | cmd_ptr = (const uint8_t *)&cmd_stream[n]; |
| 1235 | LOG_INFO("0x%.2X 0x%.2X 0x%.2X 0x%.2X ", cmd_ptr[0], cmd_ptr[1], cmd_ptr[2], cmd_ptr[3]); |
| 1236 | // Command name and payload |
| 1237 | if (cmd_stream[n] & 0x4000) |
| 1238 | { |
| 1239 | cmd_name = lookup_name(cmd1_name_tbl, cmd1_name_tbl_count, cmd_stream[n] & 0x3FF); |
| 1240 | n++; |
| 1241 | cmd_val = cmd_stream[n]; |
| 1242 | cmd_ptr = (const uint8_t *)&cmd_stream[n]; |
| 1243 | LOG_INFO("0x%.2X 0x%.2X 0x%.2X 0x%.2X ", cmd_ptr[0], cmd_ptr[1], cmd_ptr[2], cmd_ptr[3]); |
| 1244 | } |
| 1245 | else |
| 1246 | { |
| 1247 | cmd_val = cmd_stream[n] >> 16; |
| 1248 | cmd_name = lookup_name(cmd0_name_tbl, cmd0_name_tbl_count, cmd_stream[n] & 0x3FF); |
| 1249 | } |
| 1250 | if (cmd_name) |
| 1251 | { |
Per Åstrand | 14ccfee | 2020-09-25 10:40:20 +0200 | [diff] [blame] | 1252 | LOG_INFO("\t%s 0x%.8" PRIX32, cmd_name, cmd_val); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 1253 | } |
| 1254 | if (offset == qread) |
| 1255 | { |
| 1256 | LOG_INFO(" <<== QREAD\n"); |
| 1257 | } |
| 1258 | else |
| 1259 | { |
| 1260 | LOG_INFO("\n"); |
| 1261 | } |
| 1262 | } |
| 1263 | } |