Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 1 | /* |
Kristofer Jonsson | 09273d1 | 2021-03-15 08:43:08 +0100 | [diff] [blame] | 2 | * Copyright (c) 2019-2021 Arm Limited. All rights reserved. |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: Apache-2.0 |
| 5 | * |
| 6 | * Licensed under the Apache License, Version 2.0 (the License); you may |
| 7 | * not use this file except in compliance with the License. |
| 8 | * You may obtain a copy of the License at |
| 9 | * |
| 10 | * www.apache.org/licenses/LICENSE-2.0 |
| 11 | * |
| 12 | * Unless required by applicable law or agreed to in writing, software |
| 13 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT |
| 14 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 15 | * See the License for the specific language governing permissions and |
| 16 | * limitations under the License. |
| 17 | */ |
| 18 | |
Kristofer Jonsson | 2b201c3 | 2020-09-02 16:42:43 +0200 | [diff] [blame] | 19 | /****************************************************************************** |
| 20 | * Includes |
| 21 | ******************************************************************************/ |
| 22 | |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 23 | #include "ethosu_driver.h" |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 24 | #include "ethosu_common.h" |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 25 | #include "ethosu_config.h" |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 26 | #include "ethosu_device.h" |
Per Åstrand | 25d78c0 | 2020-04-21 14:19:44 +0200 | [diff] [blame] | 27 | |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 28 | #include <assert.h> |
Per Åstrand | 25d78c0 | 2020-04-21 14:19:44 +0200 | [diff] [blame] | 29 | #include <cmsis_compiler.h> |
Per Åstrand | 14ccfee | 2020-09-25 10:40:20 +0200 | [diff] [blame] | 30 | #include <inttypes.h> |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 31 | #include <stdbool.h> |
Bhavik Patel | bf7ae63 | 2020-06-11 21:00:16 +0200 | [diff] [blame] | 32 | #include <stddef.h> |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 33 | #include <stdio.h> |
| 34 | #include <stdlib.h> |
| 35 | |
Kristofer Jonsson | 2b201c3 | 2020-09-02 16:42:43 +0200 | [diff] [blame] | 36 | /****************************************************************************** |
| 37 | * Defines |
| 38 | ******************************************************************************/ |
| 39 | |
| 40 | #define MACS_PER_CYCLE_LOG2_MASK 0x000F |
| 41 | #define SHRAM_SIZE_MASK 0xFF00 |
| 42 | #define SHRAM_SIZE_RIGHT_SHIFT 8 |
| 43 | #define BYTES_IN_32_BITS 4 |
| 44 | #define CUSTOM_OPTION_LENGTH_32_BIT_WORD 1 |
| 45 | #define DRIVER_ACTION_LENGTH_32_BIT_WORD 1 |
| 46 | #define OPTIMIZER_CONFIG_LENGTH_32_BIT_WORD 2 |
| 47 | #define ETHOSU_FOURCC ('1' << 24 | 'P' << 16 | 'O' << 8 | 'C') // "Custom Operator Payload 1" |
| 48 | #define APB_START_ADDR_MASK 0x0FFF |
| 49 | #define APB_NUM_REG_BIT_SHIFT 12 |
| 50 | #define BYTES_1KB 1024 |
| 51 | #define PRODUCT_MAJOR_ETHOSU55 (4) |
| 52 | #define MASK_16_BYTE_ALIGN (0xF) |
| 53 | #define FAST_MEMORY_BASE_ADDR_INDEX 2 |
| 54 | |
| 55 | /****************************************************************************** |
| 56 | * Types |
| 57 | ******************************************************************************/ |
| 58 | |
| 59 | // Driver actions |
| 60 | enum DRIVER_ACTION_e |
| 61 | { |
| 62 | RESERVED = 0, |
| 63 | OPTIMIZER_CONFIG = 1, |
| 64 | COMMAND_STREAM = 2, |
| 65 | READ_APB_REG = 3, |
| 66 | DUMP_SHRAM = 4, |
| 67 | NOP = 5, |
| 68 | }; |
| 69 | |
| 70 | // Custom data struct |
| 71 | struct custom_data_s |
| 72 | { |
| 73 | union |
| 74 | { |
| 75 | // Driver action data |
| 76 | struct |
| 77 | { |
| 78 | // Driver action command (valid values in DRIVER_ACTION_e) |
| 79 | uint8_t driver_action_command; |
| 80 | |
| 81 | // reserved |
| 82 | uint8_t reserved; |
| 83 | |
| 84 | // Driver action data |
| 85 | union |
| 86 | { |
| 87 | // DA_CMD_OPT_CFG |
| 88 | struct |
| 89 | { |
| 90 | uint16_t rel_nbr : 4; |
| 91 | uint16_t patch_nbr : 4; |
| 92 | uint16_t opt_cfg_reserved : 8; |
| 93 | }; |
| 94 | |
| 95 | // DA_CMD_CMSTRM |
| 96 | struct |
| 97 | { |
| 98 | uint16_t length; |
| 99 | }; |
| 100 | |
| 101 | // DA_CMD_READAPB |
| 102 | struct |
| 103 | { |
| 104 | uint16_t start_address : 12; |
| 105 | uint16_t nbr_reg_minus1 : 4; |
| 106 | }; |
| 107 | |
| 108 | uint16_t driver_action_data; |
| 109 | }; |
| 110 | }; |
| 111 | |
| 112 | uint32_t word; |
| 113 | }; |
| 114 | }; |
| 115 | |
| 116 | // optimizer config struct |
| 117 | struct opt_cfg_s |
| 118 | { |
| 119 | struct custom_data_s da_data; |
| 120 | union |
| 121 | { |
| 122 | struct |
| 123 | { |
| 124 | uint32_t macs_per_cc : 4; |
| 125 | uint32_t cmd_stream_version : 4; |
| 126 | uint32_t shram_size : 8; |
Anton Moberg | b8bcf13 | 2021-03-29 10:02:25 +0200 | [diff] [blame] | 127 | uint32_t reserved0 : 11; |
| 128 | uint32_t custom_dma : 1; |
| 129 | uint32_t product : 4; |
Kristofer Jonsson | 2b201c3 | 2020-09-02 16:42:43 +0200 | [diff] [blame] | 130 | }; |
| 131 | uint32_t npu_cfg; |
| 132 | }; |
| 133 | union |
| 134 | { |
| 135 | struct |
| 136 | { |
| 137 | uint32_t version_status : 4; |
| 138 | uint32_t version_minor : 4; |
| 139 | uint32_t version_major : 4; |
| 140 | uint32_t product_major : 4; |
| 141 | uint32_t arch_patch_rev : 4; |
| 142 | uint32_t arch_minor_rev : 8; |
| 143 | uint32_t arch_major_rev : 4; |
| 144 | }; |
| 145 | uint32_t ethosu_id; |
| 146 | }; |
| 147 | }; |
| 148 | |
| 149 | /****************************************************************************** |
| 150 | * Functions |
| 151 | ******************************************************************************/ |
| 152 | |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 153 | struct ethosu_driver ethosu_drv = { |
Kristofer Jonsson | c6e7a1f | 2020-11-24 09:20:14 +0100 | [diff] [blame] | 154 | .dev = {.base_address = NULL, .proto = 0, .pmccntr = {0}, .pmu_evcntr = {0, 0, 0, 0}, .pmu_evtypr = {0, 0, 0, 0}}, |
Anton Moberg | 8d65b6f | 2020-12-21 09:37:18 +0100 | [diff] [blame] | 155 | .abort_inference = false, |
| 156 | .status_error = false, |
| 157 | .dev_power_always_on = false}; |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 158 | |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 159 | // Registered drivers linked list HEAD |
| 160 | static struct ethosu_driver *registered_drivers = NULL; |
| 161 | |
Anton Moberg | dfed5fd | 2021-03-11 14:41:11 +0100 | [diff] [blame] | 162 | /* |
| 163 | * Following section handles the minimal sempahore and mutex implementation in case of baremetal applications. |
| 164 | * Weak symbols will be overwritten by RTOS definitions and implement true thread-safety. (Done in application layer) |
| 165 | */ |
| 166 | |
| 167 | // Baremetal sempahore implementation |
| 168 | struct ethosu_semaphore_t |
| 169 | { |
| 170 | int count; |
| 171 | }; |
| 172 | |
| 173 | // Minimal needed declaration to allow baremetal functionality. |
| 174 | static void *ethosu_mutex; |
| 175 | static void *ethosu_semaphore; |
| 176 | |
Anton Moberg | 9f346ab | 2021-05-21 17:20:21 +0200 | [diff] [blame] | 177 | void *__attribute__((weak)) ethosu_mutex_create(void) |
| 178 | { |
| 179 | return NULL; |
| 180 | } |
Anton Moberg | dfed5fd | 2021-03-11 14:41:11 +0100 | [diff] [blame] | 181 | |
Anton Moberg | 61ec36b | 2021-04-30 17:10:48 +0200 | [diff] [blame] | 182 | void __attribute__((weak)) ethosu_mutex_lock(void *mutex) |
| 183 | { |
| 184 | UNUSED(mutex); |
| 185 | } |
Anton Moberg | dfed5fd | 2021-03-11 14:41:11 +0100 | [diff] [blame] | 186 | |
Anton Moberg | 61ec36b | 2021-04-30 17:10:48 +0200 | [diff] [blame] | 187 | void __attribute__((weak)) ethosu_mutex_unlock(void *mutex) |
| 188 | { |
| 189 | UNUSED(mutex); |
| 190 | } |
Anton Moberg | dfed5fd | 2021-03-11 14:41:11 +0100 | [diff] [blame] | 191 | |
| 192 | // Baremetal implementation of creating a semaphore |
| 193 | void *__attribute__((weak)) ethosu_semaphore_create(void) |
| 194 | { |
| 195 | struct ethosu_semaphore_t *sem = malloc(sizeof(*sem)); |
| 196 | sem->count = 1; |
| 197 | return sem; |
| 198 | } |
| 199 | |
| 200 | // Baremetal simulation of waiting/sleeping for and then taking a semaphore using intrisics |
| 201 | void __attribute__((weak)) ethosu_semaphore_take(void *sem) |
| 202 | { |
| 203 | struct ethosu_semaphore_t *s = sem; |
| 204 | while (s->count <= 0) |
| 205 | { |
| 206 | __WFE(); |
| 207 | } |
| 208 | s->count--; |
| 209 | } |
| 210 | |
| 211 | // Baremetal simulation of giving a semaphore and waking up processes using intrinsics |
| 212 | void __attribute__((weak)) ethosu_semaphore_give(void *sem) |
| 213 | { |
| 214 | struct ethosu_semaphore_t *s = sem; |
| 215 | s->count++; |
| 216 | __SEV(); |
| 217 | } |
| 218 | // <--- End of semaphore and mutex implementations |
| 219 | |
Anton Moberg | 8d65b6f | 2020-12-21 09:37:18 +0100 | [diff] [blame] | 220 | static int ethosu_soft_reset_and_restore(struct ethosu_driver *drv); |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 221 | |
Anton Moberg | effc7aa | 2021-05-03 09:25:06 +0200 | [diff] [blame] | 222 | void __attribute__((weak)) ethosu_irq_handler(struct ethosu_driver *drv) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 223 | { |
| 224 | uint8_t irq_raised = 0; |
Kristofer Jonsson | 125429a | 2020-08-20 16:52:23 +0200 | [diff] [blame] | 225 | |
| 226 | LOG_DEBUG("Interrupt. status=0x%08x, qread=%d\n", |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 227 | ethosu_read_reg(&drv->dev, NPU_REG_STATUS), |
| 228 | ethosu_read_reg(&drv->dev, NPU_REG_QREAD)); |
Kristofer Jonsson | 125429a | 2020-08-20 16:52:23 +0200 | [diff] [blame] | 229 | |
| 230 | // Verify that interrupt has been raised |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 231 | (void)ethosu_is_irq_raised(&drv->dev, &irq_raised); |
Kristofer Jonsson | 1c893b5 | 2021-05-26 12:06:14 +0200 | [diff] [blame] | 232 | assert(irq_raised == 1); |
Anton Moberg | dfed5fd | 2021-03-11 14:41:11 +0100 | [diff] [blame] | 233 | drv->irq_triggered = true; |
Kristofer Jonsson | 125429a | 2020-08-20 16:52:23 +0200 | [diff] [blame] | 234 | |
| 235 | // Clear interrupt |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 236 | (void)ethosu_clear_irq_status(&drv->dev); |
Kristofer Jonsson | 125429a | 2020-08-20 16:52:23 +0200 | [diff] [blame] | 237 | |
Bhavik Patel | 5f8dad1 | 2020-09-30 09:06:52 +0200 | [diff] [blame] | 238 | // Verify that interrupt has been successfully cleared |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 239 | (void)ethosu_is_irq_raised(&drv->dev, &irq_raised); |
Kristofer Jonsson | 1c893b5 | 2021-05-26 12:06:14 +0200 | [diff] [blame] | 240 | assert(irq_raised == 0); |
Bhavik Patel | 5f8dad1 | 2020-09-30 09:06:52 +0200 | [diff] [blame] | 241 | |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 242 | if (ethosu_status_has_error(&drv->dev)) |
Bhavik Patel | 5f8dad1 | 2020-09-30 09:06:52 +0200 | [diff] [blame] | 243 | { |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 244 | ethosu_soft_reset_and_restore(drv); |
| 245 | drv->status_error = true; |
Bhavik Patel | 5f8dad1 | 2020-09-30 09:06:52 +0200 | [diff] [blame] | 246 | } |
Anton Moberg | dfed5fd | 2021-03-11 14:41:11 +0100 | [diff] [blame] | 247 | |
| 248 | ethosu_semaphore_give(drv->semaphore); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 249 | } |
| 250 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 251 | static inline void wait_for_irq(struct ethosu_driver *drv) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 252 | { |
| 253 | while (1) |
| 254 | { |
Anton Moberg | dfed5fd | 2021-03-11 14:41:11 +0100 | [diff] [blame] | 255 | if (drv->irq_triggered || drv->abort_inference) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 256 | { |
Anton Moberg | dfed5fd | 2021-03-11 14:41:11 +0100 | [diff] [blame] | 257 | drv->irq_triggered = false; |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 258 | break; |
| 259 | } |
| 260 | |
Anton Moberg | dfed5fd | 2021-03-11 14:41:11 +0100 | [diff] [blame] | 261 | ethosu_semaphore_take(drv->semaphore); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 262 | } |
| 263 | } |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 264 | |
Jens Elofsson | 04961a4 | 2021-04-08 18:51:38 +0200 | [diff] [blame] | 265 | void __attribute__((weak)) ethosu_inference_begin(struct ethosu_driver *drv, const void *inference_data) |
| 266 | { |
| 267 | (void)inference_data; |
| 268 | (void)drv; |
| 269 | } |
| 270 | |
| 271 | void __attribute__((weak)) ethosu_inference_end(struct ethosu_driver *drv, const void *inference_data) |
| 272 | { |
| 273 | (void)inference_data; |
| 274 | (void)drv; |
| 275 | } |
| 276 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 277 | static int handle_optimizer_config(struct ethosu_driver *drv, struct opt_cfg_s *opt_cfg_p); |
| 278 | static int handle_command_stream(struct ethosu_driver *drv, |
| 279 | const uint8_t *cmd_stream, |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 280 | const int cms_length, |
| 281 | const uint64_t *base_addr, |
Per Åstrand | 3c8afcc | 2020-10-20 10:29:59 +0200 | [diff] [blame] | 282 | const size_t *base_addr_size, |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 283 | const int num_base_addr); |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 284 | static int read_apb_reg(struct ethosu_driver *drv, uint16_t); |
| 285 | static int dump_shram(struct ethosu_driver *drv); |
| 286 | static void dump_npu_register(struct ethosu_driver *drv, int npu_reg, int npu_reg_end); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 287 | static void dump_command_stream(const uint32_t *cmd_stream, const int cms_length, int qread); |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 288 | static void npu_axi_init(struct ethosu_driver *drv); |
Anton Moberg | df386e0 | 2021-02-02 11:26:48 +0100 | [diff] [blame] | 289 | static struct ethosu_driver *ethosu_find_and_reserve_driver(void); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 290 | |
Anton Moberg | effc7aa | 2021-05-03 09:25:06 +0200 | [diff] [blame] | 291 | int ethosu_init(struct ethosu_driver *drv, |
| 292 | const void *base_address, |
| 293 | const void *fast_memory, |
| 294 | const size_t fast_memory_size, |
| 295 | uint32_t secure_enable, |
| 296 | uint32_t privilege_enable) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 297 | { |
| 298 | int return_code = 0; |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 299 | |
Bhavik Patel | 033bb1b | 2020-12-17 15:33:33 +0100 | [diff] [blame] | 300 | LOG_INFO("%s. base_address=%p, fast_memory=%p, fast_memory_size=%zu, secure=%" PRIu32 ", privileged=%" PRIu32 "\n", |
Kristofer Jonsson | 2b201c3 | 2020-09-02 16:42:43 +0200 | [diff] [blame] | 301 | __FUNCTION__, |
| 302 | base_address, |
| 303 | fast_memory, |
Per Åstrand | e6498f0 | 2020-11-09 15:33:12 +0100 | [diff] [blame] | 304 | fast_memory_size, |
| 305 | secure_enable, |
| 306 | privilege_enable); |
Kristofer Jonsson | 2b201c3 | 2020-09-02 16:42:43 +0200 | [diff] [blame] | 307 | |
Anton Moberg | dfed5fd | 2021-03-11 14:41:11 +0100 | [diff] [blame] | 308 | if (!ethosu_mutex) |
| 309 | { |
| 310 | ethosu_mutex = ethosu_mutex_create(); |
| 311 | } |
| 312 | |
| 313 | if (!ethosu_semaphore) |
| 314 | { |
| 315 | ethosu_semaphore = ethosu_semaphore_create(); |
| 316 | } |
| 317 | |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 318 | ethosu_register_driver(drv); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 319 | |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 320 | drv->fast_memory = (uint32_t)fast_memory; |
| 321 | drv->fast_memory_size = fast_memory_size; |
Anton Moberg | dfed5fd | 2021-03-11 14:41:11 +0100 | [diff] [blame] | 322 | drv->irq_triggered = false; |
| 323 | drv->semaphore = ethosu_semaphore_create(); |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 324 | |
| 325 | if (ETHOSU_SUCCESS != ethosu_dev_init(&drv->dev, base_address, secure_enable, privilege_enable)) |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 326 | { |
| 327 | LOG_ERR("Failed in ethosu_dev_init"); |
| 328 | return -1; |
| 329 | } |
| 330 | |
Anton Moberg | 0a61429 | 2021-03-24 14:08:22 +0100 | [diff] [blame] | 331 | if (ETHOSU_SUCCESS != |
| 332 | set_clock_and_power_request(drv, ETHOSU_INFERENCE_REQUEST, ETHOSU_CLOCK_Q_DISABLE, ETHOSU_POWER_Q_DISABLE)) |
Bhavik Patel | e645fed | 2020-06-12 14:46:47 +0200 | [diff] [blame] | 333 | { |
| 334 | LOG_ERR("Failed to disable clock-q & power-q for Ethos-U\n"); |
| 335 | return -1; |
| 336 | } |
| 337 | |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 338 | if (ETHOSU_SUCCESS != ethosu_soft_reset(&drv->dev)) |
Per Åstrand | 849cf69 | 2020-11-24 07:39:55 +0100 | [diff] [blame] | 339 | { |
| 340 | return -1; |
| 341 | } |
Kristofer Jonsson | daa0d20 | 2020-05-12 12:23:16 +0200 | [diff] [blame] | 342 | |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 343 | if (ETHOSU_SUCCESS != ethosu_wait_for_reset(&drv->dev)) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 344 | { |
| 345 | LOG_ERR("Failed reset of Ethos-U\n"); |
| 346 | return -1; |
| 347 | } |
Anton Moberg | 8d65b6f | 2020-12-21 09:37:18 +0100 | [diff] [blame] | 348 | |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 349 | drv->status_error = false; |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 350 | |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 351 | return return_code; |
| 352 | } |
| 353 | |
Anton Moberg | effc7aa | 2021-05-03 09:25:06 +0200 | [diff] [blame] | 354 | int ethosu_get_version(struct ethosu_driver *drv, struct ethosu_version *version) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 355 | { |
| 356 | int return_code = 0; |
| 357 | |
| 358 | if (NULL != version) |
| 359 | { |
| 360 | struct ethosu_id id; |
| 361 | struct ethosu_config cfg; |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 362 | (void)ethosu_get_id(&drv->dev, &id); |
| 363 | (void)ethosu_get_config(&drv->dev, &cfg); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 364 | |
| 365 | version->id.version_status = id.version_status; |
| 366 | version->id.version_minor = id.version_minor; |
| 367 | version->id.version_major = id.version_major; |
| 368 | version->id.product_major = id.product_major; |
| 369 | version->id.arch_patch_rev = id.arch_patch_rev; |
| 370 | version->id.arch_minor_rev = id.arch_minor_rev; |
| 371 | version->id.arch_major_rev = id.arch_major_rev; |
| 372 | version->id.driver_patch_rev = ETHOSU_DRIVER_VERSION_PATCH; |
| 373 | version->id.driver_minor_rev = ETHOSU_DRIVER_VERSION_MINOR; |
| 374 | version->id.driver_major_rev = ETHOSU_DRIVER_VERSION_MAJOR; |
| 375 | version->cfg.macs_per_cc = cfg.macs_per_cc; |
| 376 | version->cfg.cmd_stream_version = cfg.cmd_stream_version; |
| 377 | version->cfg.shram_size = cfg.shram_size; |
Anton Moberg | b8bcf13 | 2021-03-29 10:02:25 +0200 | [diff] [blame] | 378 | version->cfg.custom_dma = cfg.custom_dma; |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 379 | } |
| 380 | else |
| 381 | { |
| 382 | return_code = -1; |
| 383 | } |
| 384 | |
| 385 | return return_code; |
| 386 | } |
| 387 | |
Anton Moberg | effc7aa | 2021-05-03 09:25:06 +0200 | [diff] [blame] | 388 | int ethosu_invoke(struct ethosu_driver *drv, |
| 389 | const void *custom_data_ptr, |
| 390 | const int custom_data_size, |
| 391 | const uint64_t *base_addr, |
| 392 | const size_t *base_addr_size, |
| 393 | const int num_base_addr) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 394 | { |
Kristofer Jonsson | 2b201c3 | 2020-09-02 16:42:43 +0200 | [diff] [blame] | 395 | const struct custom_data_s *data_ptr = custom_data_ptr; |
| 396 | const struct custom_data_s *data_end = custom_data_ptr + custom_data_size; |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 397 | int return_code = 0; |
| 398 | |
Kristofer Jonsson | 2b201c3 | 2020-09-02 16:42:43 +0200 | [diff] [blame] | 399 | LOG_INFO("%s\n", __FUNCTION__); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 400 | |
| 401 | // First word in custom_data_ptr should contain "Custom Operator Payload 1" |
Kristofer Jonsson | 2b201c3 | 2020-09-02 16:42:43 +0200 | [diff] [blame] | 402 | if (data_ptr->word != ETHOSU_FOURCC) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 403 | { |
Per Åstrand | 14ccfee | 2020-09-25 10:40:20 +0200 | [diff] [blame] | 404 | LOG_ERR("Custom Operator Payload: %" PRIu32 " is not correct, expected %x\n", data_ptr->word, ETHOSU_FOURCC); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 405 | return -1; |
| 406 | } |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 407 | |
Kristofer Jonsson | 2b201c3 | 2020-09-02 16:42:43 +0200 | [diff] [blame] | 408 | // Custom data length must be a multiple of 32 bits |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 409 | if ((custom_data_size % BYTES_IN_32_BITS) != 0) |
| 410 | { |
| 411 | LOG_ERR("ethosu_invoke ERROR custom_data_size=0x%x not a multiple of 4\n", custom_data_size); |
| 412 | return -1; |
| 413 | } |
Kristofer Jonsson | 2b201c3 | 2020-09-02 16:42:43 +0200 | [diff] [blame] | 414 | |
| 415 | ++data_ptr; |
| 416 | |
| 417 | // Adjust base address to fast memory area |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 418 | if (drv->fast_memory != 0 && num_base_addr >= FAST_MEMORY_BASE_ADDR_INDEX) |
Kristofer Jonsson | 2b201c3 | 2020-09-02 16:42:43 +0200 | [diff] [blame] | 419 | { |
| 420 | uint64_t *fast_memory = (uint64_t *)&base_addr[FAST_MEMORY_BASE_ADDR_INDEX]; |
| 421 | |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 422 | if (base_addr_size != NULL && base_addr_size[FAST_MEMORY_BASE_ADDR_INDEX] > drv->fast_memory_size) |
Kristofer Jonsson | 2b201c3 | 2020-09-02 16:42:43 +0200 | [diff] [blame] | 423 | { |
Kristofer Jonsson | 4c94b30 | 2020-11-06 10:33:21 +0100 | [diff] [blame] | 424 | LOG_ERR("Fast memory area too small. fast_memory_size=%u, base_addr_size=%u\n", |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 425 | drv->fast_memory_size, |
Kristofer Jonsson | 4c94b30 | 2020-11-06 10:33:21 +0100 | [diff] [blame] | 426 | base_addr_size[FAST_MEMORY_BASE_ADDR_INDEX]); |
| 427 | return -1; |
Kristofer Jonsson | 2b201c3 | 2020-09-02 16:42:43 +0200 | [diff] [blame] | 428 | } |
Kristofer Jonsson | 4c94b30 | 2020-11-06 10:33:21 +0100 | [diff] [blame] | 429 | |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 430 | *fast_memory = drv->fast_memory; |
Kristofer Jonsson | 2b201c3 | 2020-09-02 16:42:43 +0200 | [diff] [blame] | 431 | } |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 432 | |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 433 | if (!drv->dev_power_always_on) |
Bhavik Patel | 5f8dad1 | 2020-09-30 09:06:52 +0200 | [diff] [blame] | 434 | { |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 435 | // Only soft reset if securty state or privilege level needs changing |
| 436 | if (drv->dev.proto != ethosu_read_reg(&drv->dev, NPU_REG_PROT)) |
Per Åstrand | 849cf69 | 2020-11-24 07:39:55 +0100 | [diff] [blame] | 437 | { |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 438 | if (ETHOSU_SUCCESS != ethosu_soft_reset(&drv->dev)) |
Anton Moberg | 8d65b6f | 2020-12-21 09:37:18 +0100 | [diff] [blame] | 439 | { |
| 440 | return -1; |
| 441 | } |
Per Åstrand | 849cf69 | 2020-11-24 07:39:55 +0100 | [diff] [blame] | 442 | } |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 443 | |
| 444 | drv->status_error = false; |
Anton Moberg | 0a61429 | 2021-03-24 14:08:22 +0100 | [diff] [blame] | 445 | set_clock_and_power_request(drv, ETHOSU_INFERENCE_REQUEST, ETHOSU_CLOCK_Q_ENABLE, ETHOSU_POWER_Q_DISABLE); |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 446 | ethosu_restore_pmu_config(&drv->dev); |
| 447 | npu_axi_init(drv); |
Bhavik Patel | 5f8dad1 | 2020-09-30 09:06:52 +0200 | [diff] [blame] | 448 | } |
Kristofer Jonsson | c6e7a1f | 2020-11-24 09:20:14 +0100 | [diff] [blame] | 449 | |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 450 | drv->status_error = false; |
Kristofer Jonsson | 125429a | 2020-08-20 16:52:23 +0200 | [diff] [blame] | 451 | |
Jens Elofsson | 04961a4 | 2021-04-08 18:51:38 +0200 | [diff] [blame] | 452 | ethosu_inference_begin(drv, custom_data_ptr); |
Kristofer Jonsson | 2b201c3 | 2020-09-02 16:42:43 +0200 | [diff] [blame] | 453 | while (data_ptr < data_end) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 454 | { |
Bhavik Patel | e645fed | 2020-06-12 14:46:47 +0200 | [diff] [blame] | 455 | int ret = 0; |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 456 | switch (data_ptr->driver_action_command) |
| 457 | { |
| 458 | case OPTIMIZER_CONFIG: |
| 459 | LOG_INFO("ethosu_invoke OPTIMIZER_CONFIG\n"); |
| 460 | struct opt_cfg_s *opt_cfg_p = (struct opt_cfg_s *)data_ptr; |
| 461 | |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 462 | ret = handle_optimizer_config(drv, opt_cfg_p); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 463 | data_ptr += DRIVER_ACTION_LENGTH_32_BIT_WORD + OPTIMIZER_CONFIG_LENGTH_32_BIT_WORD; |
| 464 | break; |
| 465 | case COMMAND_STREAM: |
| 466 | LOG_INFO("ethosu_invoke COMMAND_STREAM\n"); |
| 467 | void *command_stream = (uint8_t *)(data_ptr) + sizeof(struct custom_data_s); |
| 468 | int cms_length = (data_ptr->reserved << 16) | data_ptr->length; |
| 469 | |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 470 | drv->abort_inference = false; |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 471 | // It is safe to clear this flag without atomic, because npu is not running. |
Anton Moberg | dfed5fd | 2021-03-11 14:41:11 +0100 | [diff] [blame] | 472 | drv->irq_triggered = false; |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 473 | |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 474 | ret = handle_command_stream(drv, command_stream, cms_length, base_addr, base_addr_size, num_base_addr); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 475 | |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 476 | if (return_code == -1 && drv->abort_inference) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 477 | { |
| 478 | uint32_t qread = 0; |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 479 | ethosu_get_qread(&drv->dev, &qread); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 480 | LOG_ERR("NPU timeout\n"); |
| 481 | dump_command_stream(command_stream, cms_length, qread); |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 482 | dump_npu_register(drv, 0x200, 0x2BF); |
| 483 | dump_npu_register(drv, 0x800, 0xB3F); |
| 484 | dump_shram(drv); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 485 | } |
| 486 | |
| 487 | data_ptr += DRIVER_ACTION_LENGTH_32_BIT_WORD + cms_length; |
| 488 | break; |
| 489 | case READ_APB_REG: |
| 490 | LOG_INFO("ethosu_invoke READ_APB_REG\n"); |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 491 | ret = read_apb_reg(drv, data_ptr->driver_action_data); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 492 | data_ptr += DRIVER_ACTION_LENGTH_32_BIT_WORD; |
| 493 | break; |
| 494 | case DUMP_SHRAM: |
| 495 | LOG_INFO("ethosu_invoke DUMP_SHRAM\n"); |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 496 | ret = dump_shram(drv); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 497 | data_ptr += DRIVER_ACTION_LENGTH_32_BIT_WORD; |
| 498 | break; |
| 499 | case NOP: |
| 500 | LOG_INFO("ethosu_invoke NOP\n"); |
| 501 | data_ptr += DRIVER_ACTION_LENGTH_32_BIT_WORD; |
| 502 | break; |
| 503 | default: |
| 504 | LOG_ERR("ethosu_invoke UNSUPPORTED driver_action_command %d \n", data_ptr->driver_action_command); |
Bhavik Patel | e645fed | 2020-06-12 14:46:47 +0200 | [diff] [blame] | 505 | ret = -1; |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 506 | break; |
| 507 | } |
Bhavik Patel | e645fed | 2020-06-12 14:46:47 +0200 | [diff] [blame] | 508 | if (ret != 0) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 509 | { |
Bhavik Patel | e645fed | 2020-06-12 14:46:47 +0200 | [diff] [blame] | 510 | return_code = -1; |
| 511 | break; |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 512 | } |
| 513 | } |
Jens Elofsson | 04961a4 | 2021-04-08 18:51:38 +0200 | [diff] [blame] | 514 | ethosu_inference_end(drv, custom_data_ptr); |
Kristofer Jonsson | 2b201c3 | 2020-09-02 16:42:43 +0200 | [diff] [blame] | 515 | |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 516 | if (!drv->status_error && !drv->dev_power_always_on) |
Bhavik Patel | 5f8dad1 | 2020-09-30 09:06:52 +0200 | [diff] [blame] | 517 | { |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 518 | ethosu_save_pmu_counters(&drv->dev); |
Anton Moberg | 0a61429 | 2021-03-24 14:08:22 +0100 | [diff] [blame] | 519 | set_clock_and_power_request(drv, ETHOSU_INFERENCE_REQUEST, ETHOSU_CLOCK_Q_ENABLE, ETHOSU_POWER_Q_ENABLE); |
Bhavik Patel | 5f8dad1 | 2020-09-30 09:06:52 +0200 | [diff] [blame] | 520 | } |
Kristofer Jonsson | 2b201c3 | 2020-09-02 16:42:43 +0200 | [diff] [blame] | 521 | |
Bhavik Patel | e645fed | 2020-06-12 14:46:47 +0200 | [diff] [blame] | 522 | return return_code; |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 523 | } |
| 524 | |
Anton Moberg | effc7aa | 2021-05-03 09:25:06 +0200 | [diff] [blame] | 525 | void ethosu_abort(struct ethosu_driver *drv) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 526 | { |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 527 | drv->abort_inference = true; |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 528 | } |
| 529 | |
Anton Moberg | effc7aa | 2021-05-03 09:25:06 +0200 | [diff] [blame] | 530 | void ethosu_set_power_mode(struct ethosu_driver *drv, bool always_on) |
Anton Moberg | 8d65b6f | 2020-12-21 09:37:18 +0100 | [diff] [blame] | 531 | { |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 532 | drv->dev_power_always_on = always_on; |
Anton Moberg | 8d65b6f | 2020-12-21 09:37:18 +0100 | [diff] [blame] | 533 | |
| 534 | if (always_on) |
| 535 | { |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 536 | npu_axi_init(drv); |
| 537 | } |
| 538 | } |
| 539 | |
| 540 | int ethosu_register_driver(struct ethosu_driver *drv) |
| 541 | { |
| 542 | // Safeguard check for if driver is already registered |
| 543 | struct ethosu_driver *cur = registered_drivers; |
| 544 | while (cur != NULL) |
| 545 | { |
| 546 | if (cur == drv) |
| 547 | { |
| 548 | LOG_ERR("%s: NPU driver at address %p is already registered.\n", __FUNCTION__, drv); |
| 549 | return -1; |
| 550 | } |
| 551 | cur = cur->next; |
| 552 | } |
| 553 | |
| 554 | drv->next = registered_drivers; |
| 555 | // Designate new registered driver HEAD |
| 556 | registered_drivers = drv; |
| 557 | |
| 558 | LOG_INFO("%s: New NPU driver at address %p is registered.\n", __FUNCTION__, drv); |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 559 | return 0; |
| 560 | } |
| 561 | |
| 562 | int ethosu_deregister_driver(struct ethosu_driver *drv) |
| 563 | { |
| 564 | struct ethosu_driver *cur = registered_drivers; |
| 565 | struct ethosu_driver **prev = ®istered_drivers; |
| 566 | |
| 567 | while (cur != NULL) |
| 568 | { |
| 569 | if (cur == drv) |
| 570 | { |
| 571 | *prev = cur->next; |
| 572 | LOG_INFO("%s: NPU driver at address %p is deregistered.\n", __FUNCTION__, drv); |
| 573 | return 0; |
| 574 | } |
| 575 | |
| 576 | prev = &cur->next; |
| 577 | cur = cur->next; |
| 578 | } |
| 579 | |
| 580 | LOG_ERR("%s: NPU driver at address %p does not match a registered driver and therefore may not be deregistered.\n", |
| 581 | __FUNCTION__, |
| 582 | drv); |
Anton Moberg | df386e0 | 2021-02-02 11:26:48 +0100 | [diff] [blame] | 583 | |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 584 | return -1; |
| 585 | } |
| 586 | |
| 587 | struct ethosu_driver *ethosu_reserve_driver(void) |
| 588 | { |
Anton Moberg | df386e0 | 2021-02-02 11:26:48 +0100 | [diff] [blame] | 589 | struct ethosu_driver *drv = NULL; |
| 590 | |
| 591 | do |
| 592 | { |
Anton Moberg | dfed5fd | 2021-03-11 14:41:11 +0100 | [diff] [blame] | 593 | ethosu_mutex_lock(ethosu_mutex); |
Anton Moberg | df386e0 | 2021-02-02 11:26:48 +0100 | [diff] [blame] | 594 | drv = ethosu_find_and_reserve_driver(); |
Anton Moberg | dfed5fd | 2021-03-11 14:41:11 +0100 | [diff] [blame] | 595 | ethosu_mutex_unlock(ethosu_mutex); |
Anton Moberg | df386e0 | 2021-02-02 11:26:48 +0100 | [diff] [blame] | 596 | |
| 597 | if (drv != NULL) |
| 598 | { |
| 599 | break; |
| 600 | } |
| 601 | |
Anton Moberg | dfed5fd | 2021-03-11 14:41:11 +0100 | [diff] [blame] | 602 | LOG_INFO("%s - Waiting for driver \n", __FUNCTION__); |
| 603 | ethosu_semaphore_take(ethosu_semaphore); |
Anton Moberg | df386e0 | 2021-02-02 11:26:48 +0100 | [diff] [blame] | 604 | |
| 605 | } while (1); |
| 606 | |
| 607 | return drv; |
| 608 | } |
| 609 | |
| 610 | static struct ethosu_driver *ethosu_find_and_reserve_driver(void) |
| 611 | { |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 612 | struct ethosu_driver *drv = registered_drivers; |
| 613 | |
| 614 | while (drv != NULL) |
| 615 | { |
| 616 | if (!drv->reserved) |
| 617 | { |
| 618 | drv->reserved = true; |
| 619 | LOG_INFO("%s - Driver %p reserved.\n", __FUNCTION__, drv); |
| 620 | return drv; |
| 621 | } |
| 622 | drv = drv->next; |
| 623 | } |
| 624 | |
| 625 | LOG_INFO("%s: No available drivers.\n", __FUNCTION__, drv); |
| 626 | |
| 627 | return NULL; |
| 628 | } |
| 629 | |
| 630 | void ethosu_release_driver(struct ethosu_driver *drv) |
| 631 | { |
Anton Moberg | dfed5fd | 2021-03-11 14:41:11 +0100 | [diff] [blame] | 632 | ethosu_mutex_lock(ethosu_mutex); |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 633 | if (drv != NULL && drv->reserved) |
| 634 | { |
| 635 | drv->reserved = false; |
| 636 | LOG_INFO("%s - Driver %p released\n", __FUNCTION__, drv); |
Anton Moberg | dfed5fd | 2021-03-11 14:41:11 +0100 | [diff] [blame] | 637 | ethosu_semaphore_give(ethosu_semaphore); |
Anton Moberg | 8d65b6f | 2020-12-21 09:37:18 +0100 | [diff] [blame] | 638 | } |
Anton Moberg | dfed5fd | 2021-03-11 14:41:11 +0100 | [diff] [blame] | 639 | ethosu_mutex_unlock(ethosu_mutex); |
Anton Moberg | 8d65b6f | 2020-12-21 09:37:18 +0100 | [diff] [blame] | 640 | } |
| 641 | |
| 642 | static int ethosu_soft_reset_and_restore(struct ethosu_driver *drv) |
| 643 | { |
| 644 | |
| 645 | if (ETHOSU_SUCCESS != ethosu_soft_reset(&drv->dev)) |
| 646 | { |
| 647 | return -1; |
| 648 | } |
| 649 | |
Anton Moberg | 0a61429 | 2021-03-24 14:08:22 +0100 | [diff] [blame] | 650 | set_clock_and_power_request(drv, ETHOSU_INFERENCE_REQUEST, ETHOSU_CLOCK_Q_ENABLE, ETHOSU_POWER_Q_DISABLE); |
Anton Moberg | 8d65b6f | 2020-12-21 09:37:18 +0100 | [diff] [blame] | 651 | |
| 652 | npu_axi_init(drv); |
| 653 | ethosu_restore_pmu_config(&drv->dev); |
| 654 | |
| 655 | return 0; |
| 656 | } |
| 657 | |
Anton Moberg | 0a61429 | 2021-03-24 14:08:22 +0100 | [diff] [blame] | 658 | enum ethosu_error_codes set_clock_and_power_request(struct ethosu_driver *drv, |
| 659 | enum ethosu_request_clients client, |
| 660 | enum ethosu_clock_q_request clock_request, |
| 661 | enum ethosu_power_q_request power_request) |
| 662 | { |
| 663 | // Set clock request bit for client |
| 664 | if (clock_request == ETHOSU_CLOCK_Q_DISABLE) |
| 665 | { |
| 666 | drv->clock_request |= (1 << client); |
| 667 | } |
| 668 | else |
| 669 | { |
| 670 | drv->clock_request &= ~(1 << client); |
| 671 | } |
| 672 | // Get current clock request (ENABLE if both PMU and INFERENCE asks for clock request, else DISABLE) |
| 673 | clock_request = drv->clock_request == 0 ? ETHOSU_CLOCK_Q_ENABLE : ETHOSU_CLOCK_Q_DISABLE; |
| 674 | |
| 675 | // Set power request bit for client |
Anton Moberg | 35b5d0e | 2021-04-13 13:32:17 +0200 | [diff] [blame] | 676 | if (power_request == ETHOSU_POWER_Q_DISABLE) |
Anton Moberg | 0a61429 | 2021-03-24 14:08:22 +0100 | [diff] [blame] | 677 | { |
| 678 | drv->power_request |= (1 << client); |
| 679 | } |
| 680 | else |
| 681 | { |
| 682 | drv->power_request &= ~(1 << client); |
| 683 | } |
| 684 | // Get current power request (ENABLE if both PMU and INFERENCE asks for power request, else DISABLE) |
| 685 | power_request = drv->power_request == 0 ? ETHOSU_POWER_Q_ENABLE : ETHOSU_POWER_Q_DISABLE; |
Anton Moberg | 35b5d0e | 2021-04-13 13:32:17 +0200 | [diff] [blame] | 686 | |
Anton Moberg | 0a61429 | 2021-03-24 14:08:22 +0100 | [diff] [blame] | 687 | // Set clock and power |
| 688 | enum ethosu_error_codes ret = ethosu_set_clock_and_power(&drv->dev, clock_request, power_request); |
| 689 | |
| 690 | return ret; |
| 691 | } |
| 692 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 693 | static int handle_optimizer_config(struct ethosu_driver *drv, struct opt_cfg_s *opt_cfg_p) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 694 | { |
| 695 | struct ethosu_config cfg; |
| 696 | struct ethosu_id id; |
| 697 | int return_code = 0; |
| 698 | |
| 699 | LOG_INFO("handle_optimizer_config:\n"); |
| 700 | LOG_INFO("Optimizer release nbr: %d patch: %d\n", opt_cfg_p->da_data.rel_nbr, opt_cfg_p->da_data.patch_nbr); |
Anton Moberg | b8bcf13 | 2021-03-29 10:02:25 +0200 | [diff] [blame] | 701 | LOG_INFO("Optimizer config cmd_stream_version: %d macs_per_cc: %d shram_size: %d custom_dma: %d\n", |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 702 | opt_cfg_p->cmd_stream_version, |
| 703 | opt_cfg_p->macs_per_cc, |
Anton Moberg | b8bcf13 | 2021-03-29 10:02:25 +0200 | [diff] [blame] | 704 | opt_cfg_p->shram_size, |
| 705 | opt_cfg_p->custom_dma); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 706 | LOG_INFO("Optimizer config Ethos-U version: %d.%d.%d\n", |
| 707 | opt_cfg_p->arch_major_rev, |
| 708 | opt_cfg_p->arch_minor_rev, |
| 709 | opt_cfg_p->arch_patch_rev); |
| 710 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 711 | (void)ethosu_get_config(&drv->dev, &cfg); |
| 712 | (void)ethosu_get_id(&drv->dev, &id); |
Anton Moberg | b8bcf13 | 2021-03-29 10:02:25 +0200 | [diff] [blame] | 713 | LOG_INFO("Ethos-U config cmd_stream_version: %" PRIu32 " macs_per_cc: %" PRIu32 " shram_size: %" PRIu32 |
| 714 | " custom_dma: %" PRIu32 "\n", |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 715 | cfg.cmd_stream_version, |
| 716 | cfg.macs_per_cc, |
Anton Moberg | b8bcf13 | 2021-03-29 10:02:25 +0200 | [diff] [blame] | 717 | cfg.shram_size, |
| 718 | cfg.custom_dma); |
Per Åstrand | 14ccfee | 2020-09-25 10:40:20 +0200 | [diff] [blame] | 719 | LOG_INFO("Ethos-U version: %" PRIu32 ".%" PRIu32 ".%" PRIu32 "\n", |
| 720 | id.arch_major_rev, |
| 721 | id.arch_minor_rev, |
| 722 | id.arch_patch_rev); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 723 | |
| 724 | if ((cfg.macs_per_cc != opt_cfg_p->macs_per_cc) || (cfg.shram_size != opt_cfg_p->shram_size) || |
Anton Moberg | b8bcf13 | 2021-03-29 10:02:25 +0200 | [diff] [blame] | 725 | (cfg.cmd_stream_version != opt_cfg_p->cmd_stream_version) || (!cfg.custom_dma && opt_cfg_p->custom_dma)) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 726 | { |
| 727 | if (cfg.macs_per_cc != opt_cfg_p->macs_per_cc) |
| 728 | { |
Per Åstrand | 14ccfee | 2020-09-25 10:40:20 +0200 | [diff] [blame] | 729 | LOG_ERR("NPU config mismatch: npu.macs_per_cc=%" PRIu32 " optimizer.macs_per_cc=%d\n", |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 730 | cfg.macs_per_cc, |
| 731 | opt_cfg_p->macs_per_cc); |
| 732 | } |
| 733 | if (cfg.shram_size != opt_cfg_p->shram_size) |
| 734 | { |
Per Åstrand | 14ccfee | 2020-09-25 10:40:20 +0200 | [diff] [blame] | 735 | LOG_ERR("NPU config mismatch: npu.shram_size=%" PRIu32 " optimizer.shram_size=%d\n", |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 736 | cfg.shram_size, |
| 737 | opt_cfg_p->shram_size); |
| 738 | } |
| 739 | if (cfg.cmd_stream_version != opt_cfg_p->cmd_stream_version) |
| 740 | { |
Per Åstrand | 14ccfee | 2020-09-25 10:40:20 +0200 | [diff] [blame] | 741 | LOG_ERR("NPU config mismatch: npu.cmd_stream_version=%" PRIu32 " optimizer.cmd_stream_version=%d\n", |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 742 | cfg.cmd_stream_version, |
| 743 | opt_cfg_p->cmd_stream_version); |
| 744 | } |
Anton Moberg | b8bcf13 | 2021-03-29 10:02:25 +0200 | [diff] [blame] | 745 | if (!cfg.custom_dma && opt_cfg_p->custom_dma) |
| 746 | { |
| 747 | LOG_ERR("NPU config mismatch: npu.custom_dma=%" PRIu32 " optimize.custom_dma=%d\n", |
| 748 | cfg.custom_dma, |
| 749 | opt_cfg_p->custom_dma); |
| 750 | } |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 751 | return_code = -1; |
| 752 | } |
| 753 | |
Douglas Troha | 91e0be5 | 2021-01-18 13:57:38 +0100 | [diff] [blame] | 754 | if ((id.arch_major_rev != opt_cfg_p->arch_major_rev) || (id.arch_minor_rev < opt_cfg_p->arch_minor_rev)) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 755 | { |
Per Åstrand | 14ccfee | 2020-09-25 10:40:20 +0200 | [diff] [blame] | 756 | LOG_ERR("NPU arch mismatch: npu.arch=%" PRIu32 ".%" PRIu32 ".%" PRIu32 " optimizer.arch=%d.%d.%d\n", |
Bhavik Patel | 790ef36 | 2020-06-03 10:05:28 +0200 | [diff] [blame] | 757 | id.arch_major_rev, |
| 758 | id.arch_minor_rev, |
| 759 | id.arch_patch_rev, |
| 760 | opt_cfg_p->arch_major_rev, |
| 761 | opt_cfg_p->arch_minor_rev, |
| 762 | opt_cfg_p->arch_patch_rev); |
| 763 | return_code = -1; |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 764 | } |
| 765 | |
| 766 | #if !defined(LOG_ENABLED) |
| 767 | UNUSED(opt_cfg_p); |
| 768 | #endif |
| 769 | return return_code; |
| 770 | } |
| 771 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 772 | static void npu_axi_init(struct ethosu_driver *drv) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 773 | { |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 774 | ethosu_set_qconfig(&drv->dev, NPU_QCONFIG); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 775 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 776 | ethosu_set_regioncfg(&drv->dev, 0, NPU_REGIONCFG_0); |
| 777 | ethosu_set_regioncfg(&drv->dev, 1, NPU_REGIONCFG_1); |
| 778 | ethosu_set_regioncfg(&drv->dev, 2, NPU_REGIONCFG_2); |
| 779 | ethosu_set_regioncfg(&drv->dev, 3, NPU_REGIONCFG_3); |
| 780 | ethosu_set_regioncfg(&drv->dev, 4, NPU_REGIONCFG_4); |
| 781 | ethosu_set_regioncfg(&drv->dev, 5, NPU_REGIONCFG_5); |
| 782 | ethosu_set_regioncfg(&drv->dev, 6, NPU_REGIONCFG_6); |
| 783 | ethosu_set_regioncfg(&drv->dev, 7, NPU_REGIONCFG_7); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 784 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 785 | (void)ethosu_set_axi_limit0(&drv->dev, |
| 786 | AXI_LIMIT0_MAX_BEATS_BYTES, |
Bhavik Patel | 790ef36 | 2020-06-03 10:05:28 +0200 | [diff] [blame] | 787 | AXI_LIMIT0_MEM_TYPE, |
| 788 | AXI_LIMIT0_MAX_OUTSTANDING_READS, |
| 789 | AXI_LIMIT0_MAX_OUTSTANDING_WRITES); |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 790 | (void)ethosu_set_axi_limit1(&drv->dev, |
| 791 | AXI_LIMIT1_MAX_BEATS_BYTES, |
Bhavik Patel | 790ef36 | 2020-06-03 10:05:28 +0200 | [diff] [blame] | 792 | AXI_LIMIT1_MEM_TYPE, |
| 793 | AXI_LIMIT1_MAX_OUTSTANDING_READS, |
| 794 | AXI_LIMIT1_MAX_OUTSTANDING_WRITES); |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 795 | (void)ethosu_set_axi_limit2(&drv->dev, |
| 796 | AXI_LIMIT2_MAX_BEATS_BYTES, |
Bhavik Patel | 790ef36 | 2020-06-03 10:05:28 +0200 | [diff] [blame] | 797 | AXI_LIMIT2_MEM_TYPE, |
| 798 | AXI_LIMIT2_MAX_OUTSTANDING_READS, |
| 799 | AXI_LIMIT2_MAX_OUTSTANDING_WRITES); |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 800 | (void)ethosu_set_axi_limit3(&drv->dev, |
| 801 | AXI_LIMIT3_MAX_BEATS_BYTES, |
Bhavik Patel | 790ef36 | 2020-06-03 10:05:28 +0200 | [diff] [blame] | 802 | AXI_LIMIT3_MEM_TYPE, |
| 803 | AXI_LIMIT3_MAX_OUTSTANDING_READS, |
| 804 | AXI_LIMIT3_MAX_OUTSTANDING_WRITES); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 805 | } |
| 806 | |
Per Åstrand | 3c8afcc | 2020-10-20 10:29:59 +0200 | [diff] [blame] | 807 | /* Default implementation to flush the data cache. Override if available on the targeted device. |
| 808 | * Passing NULL as p argument expects the whole cache to be flushed. |
| 809 | */ |
| 810 | void __attribute__((weak)) ethosu_flush_dcache(uint32_t *p, size_t bytes) |
| 811 | { |
| 812 | (void)p; |
| 813 | (void)bytes; |
| 814 | } |
| 815 | |
| 816 | /* Default implementation to invalidate the data cache. Override if available on the targeted device. |
| 817 | * Passing NULL as p argument expects the whole cache to be flushed. |
| 818 | */ |
| 819 | void __attribute__((weak)) ethosu_invalidate_dcache(uint32_t *p, size_t bytes) |
| 820 | { |
| 821 | (void)p; |
| 822 | (void)bytes; |
| 823 | } |
| 824 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 825 | static int handle_command_stream(struct ethosu_driver *drv, |
| 826 | const uint8_t *cmd_stream, |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 827 | const int cms_length, |
| 828 | const uint64_t *base_addr, |
Per Åstrand | 3c8afcc | 2020-10-20 10:29:59 +0200 | [diff] [blame] | 829 | const size_t *base_addr_size, |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 830 | const int num_base_addr) |
| 831 | { |
Kristofer Jonsson | c6e7a1f | 2020-11-24 09:20:14 +0100 | [diff] [blame] | 832 | uint32_t qread = 0; |
| 833 | uint32_t cms_bytes = cms_length * BYTES_IN_32_BITS; |
| 834 | ptrdiff_t cmd_stream_ptr = (ptrdiff_t)cmd_stream; |
| 835 | |
Kristofer Jonsson | 125429a | 2020-08-20 16:52:23 +0200 | [diff] [blame] | 836 | LOG_INFO("handle_command_stream: cmd_stream=%p, cms_length %d\n", cmd_stream, cms_length); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 837 | |
Bhavik Patel | bf7ae63 | 2020-06-11 21:00:16 +0200 | [diff] [blame] | 838 | if (0 != ((ptrdiff_t)cmd_stream & MASK_16_BYTE_ALIGN)) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 839 | { |
Bhavik Patel | bf7ae63 | 2020-06-11 21:00:16 +0200 | [diff] [blame] | 840 | LOG_ERR("Error: Command stream addr %p not aligned to 16 bytes\n", cmd_stream); |
| 841 | return -1; |
| 842 | } |
| 843 | |
| 844 | bool base_addr_invalid = false; |
| 845 | for (int i = 0; i < num_base_addr; i++) |
| 846 | { |
| 847 | if (0 != (base_addr[i] & MASK_16_BYTE_ALIGN)) |
| 848 | { |
Per Åstrand | 14ccfee | 2020-09-25 10:40:20 +0200 | [diff] [blame] | 849 | LOG_ERR("Error: Base addr %d: 0x%llx not aligned to 16 bytes\n", i, base_addr[i]); |
Bhavik Patel | bf7ae63 | 2020-06-11 21:00:16 +0200 | [diff] [blame] | 850 | base_addr_invalid = true; |
| 851 | } |
| 852 | } |
Kristofer Jonsson | c6e7a1f | 2020-11-24 09:20:14 +0100 | [diff] [blame] | 853 | |
Bhavik Patel | bf7ae63 | 2020-06-11 21:00:16 +0200 | [diff] [blame] | 854 | if (base_addr_invalid) |
| 855 | { |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 856 | return -1; |
| 857 | } |
Kristofer Jonsson | c6e7a1f | 2020-11-24 09:20:14 +0100 | [diff] [blame] | 858 | |
Per Åstrand | 3c8afcc | 2020-10-20 10:29:59 +0200 | [diff] [blame] | 859 | /* Flush the cache if available on our CPU. |
| 860 | * The upcasting to uin32_t* is ok since the pointer never is dereferenced. |
| 861 | * The base_addr_size is null if invoking from prior to invoke_V2, in that case |
| 862 | * the whole cache is being flushed. |
| 863 | */ |
| 864 | |
| 865 | if (base_addr_size != NULL) |
| 866 | { |
Kristofer Jonsson | c6e7a1f | 2020-11-24 09:20:14 +0100 | [diff] [blame] | 867 | ethosu_flush_dcache((uint32_t *)cmd_stream_ptr, cms_bytes); |
Per Åstrand | 3c8afcc | 2020-10-20 10:29:59 +0200 | [diff] [blame] | 868 | for (int i = 0; i < num_base_addr; i++) |
| 869 | { |
Bhavik Patel | 033bb1b | 2020-12-17 15:33:33 +0100 | [diff] [blame] | 870 | ethosu_flush_dcache((uint32_t *)(uintptr_t)base_addr[i], base_addr_size[i]); |
Per Åstrand | 3c8afcc | 2020-10-20 10:29:59 +0200 | [diff] [blame] | 871 | } |
| 872 | } |
| 873 | else |
| 874 | { |
| 875 | ethosu_flush_dcache(NULL, 0); |
| 876 | } |
| 877 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 878 | if (ETHOSU_SUCCESS != ethosu_run_command_stream(&drv->dev, cmd_stream, cms_bytes, base_addr, num_base_addr)) |
Bhavik Patel | 790ef36 | 2020-06-03 10:05:28 +0200 | [diff] [blame] | 879 | { |
| 880 | return -1; |
| 881 | } |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 882 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 883 | wait_for_irq(drv); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 884 | |
Bhavik Patel | 5f8dad1 | 2020-09-30 09:06:52 +0200 | [diff] [blame] | 885 | if (drv->status_error) |
| 886 | { |
| 887 | return -1; |
| 888 | } |
| 889 | |
Per Åstrand | 3c8afcc | 2020-10-20 10:29:59 +0200 | [diff] [blame] | 890 | if (base_addr_size != NULL) |
| 891 | { |
| 892 | for (int i = 0; i < num_base_addr; i++) |
| 893 | { |
Bhavik Patel | 033bb1b | 2020-12-17 15:33:33 +0100 | [diff] [blame] | 894 | ethosu_invalidate_dcache((uint32_t *)(uintptr_t)base_addr[i], base_addr_size[i]); |
Per Åstrand | 3c8afcc | 2020-10-20 10:29:59 +0200 | [diff] [blame] | 895 | } |
| 896 | } |
| 897 | else |
| 898 | { |
| 899 | ethosu_invalidate_dcache(NULL, 0); |
| 900 | } |
| 901 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 902 | (void)ethosu_get_qread(&drv->dev, &qread); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 903 | if (qread != cms_bytes) |
| 904 | { |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 905 | LOG_WARN( |
Per Åstrand | 14ccfee | 2020-09-25 10:40:20 +0200 | [diff] [blame] | 906 | "Failure: IRQ received but qread (%" PRIu32 ") not at end of stream (%" PRIu32 ").\n", qread, cms_bytes); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 907 | return -1; |
| 908 | } |
| 909 | |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 910 | return 0; |
| 911 | } |
| 912 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 913 | static int read_apb_reg(struct ethosu_driver *drv, uint16_t da_data) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 914 | { |
| 915 | uint32_t *reg_p; |
| 916 | uint32_t start_address = (uint32_t)(da_data & APB_START_ADDR_MASK); |
| 917 | uint16_t num_reg = (da_data >> APB_NUM_REG_BIT_SHIFT) + 1; |
| 918 | |
| 919 | reg_p = (uint32_t *)malloc(num_reg * sizeof(uint32_t)); |
| 920 | if (reg_p == NULL) |
| 921 | { |
| 922 | LOG_INFO("read_apb_reg, Error! memory not allocated."); |
| 923 | return -1; |
| 924 | } |
| 925 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 926 | if (ETHOSU_SUCCESS == ethosu_read_apb_reg(&drv->dev, start_address, num_reg, reg_p)) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 927 | { |
| 928 | for (int i = 0; i < num_reg; i++) |
| 929 | { |
Per Åstrand | 14ccfee | 2020-09-25 10:40:20 +0200 | [diff] [blame] | 930 | LOG_INFO( |
| 931 | "NPU_REG ADDR 0x%04" PRIu32 " = 0x%08" PRIu32 "\n", (start_address + (i * BYTES_IN_32_BITS)), reg_p[i]); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 932 | } |
| 933 | } |
| 934 | else |
| 935 | { |
| 936 | free(reg_p); |
| 937 | return -1; |
| 938 | } |
| 939 | |
| 940 | free(reg_p); |
| 941 | return 0; |
| 942 | } |
| 943 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 944 | static int dump_shram(struct ethosu_driver *drv) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 945 | { |
| 946 | struct ethosu_config cfg; |
| 947 | uint32_t *shram_p; |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 948 | (void)ethosu_get_config(&drv->dev, &cfg); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 949 | |
Per Åstrand | 14ccfee | 2020-09-25 10:40:20 +0200 | [diff] [blame] | 950 | LOG_INFO("dump_shram size = %" PRIu32 " KB\n", cfg.shram_size); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 951 | |
| 952 | shram_p = (uint32_t *)malloc(BYTES_1KB); |
| 953 | if (shram_p == NULL) |
| 954 | { |
| 955 | LOG_ERR("read_shram, Error! memory not allocated."); |
| 956 | return -1; |
| 957 | } |
| 958 | |
| 959 | for (uint32_t i = 0; i < cfg.shram_size; i++) |
| 960 | { |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 961 | ethosu_get_shram_data(&drv->dev, i, (uint32_t *)shram_p); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 962 | // Output 1KB of SHRAM |
Per Åstrand | 14ccfee | 2020-09-25 10:40:20 +0200 | [diff] [blame] | 963 | LOG_INFO("***SHRAM SECTION %" PRIu32 "***\n", i); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 964 | for (int j = 0; j < (BYTES_1KB / BYTES_IN_32_BITS); j++) |
| 965 | { |
Per Åstrand | 14ccfee | 2020-09-25 10:40:20 +0200 | [diff] [blame] | 966 | LOG_INFO("[0x%04" PRIx32 "] %" PRIx32 "\n", (i * 1024 + j * 4), shram_p[j]); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 967 | } |
| 968 | } |
| 969 | free(shram_p); |
| 970 | |
| 971 | return 0; |
| 972 | } |
| 973 | |
| 974 | typedef struct |
| 975 | { |
| 976 | int number; |
| 977 | const char *name; |
| 978 | } name_lookup_t; |
| 979 | |
| 980 | static const name_lookup_t npu_reg_name_tbl[] = { |
| 981 | {0x200, "KERNEL_X"}, |
| 982 | {0x204, "KERNEL_Y"}, |
| 983 | {0x208, "KERNEL_W_M1"}, |
| 984 | {0x20C, "KERNEL_H_M1"}, |
| 985 | {0x210, "OFM_CBLK_WIDTH_M1"}, |
| 986 | {0x214, "OFM_CBLK_HEIGHT_M1"}, |
| 987 | {0x218, "OFM_CBLK_DEPTH_M1"}, |
| 988 | {0x21c, "IFM_CBLK_DEPTH_M1"}, |
| 989 | {0x220, "OFM_X"}, |
| 990 | {0x224, "OFM_Y"}, |
| 991 | {0x228, "OFM_Z"}, |
| 992 | {0x22C, "IFM_Z"}, |
| 993 | {0x230, "PAD_TOP"}, |
| 994 | {0x234, "PAD_LEFT"}, |
| 995 | {0x238, "IFM_CBLK_WIDTH"}, |
| 996 | {0x23C, "IFM_CBLK_HEIGHT"}, |
| 997 | {0x240, "DMA_IFM_SRC"}, |
| 998 | {0x244, "DMA_IFM_SRC_HI"}, |
| 999 | {0x248, "DMA_IFM_DST"}, |
| 1000 | {0x24c, "DMA_OFM_SRC"}, |
| 1001 | {0x250, "DMA_OFM_DST"}, |
| 1002 | {0x254, "DMA_OFM_DST_HI"}, |
| 1003 | {0x258, "DMA_WEIGHT_SRC"}, |
| 1004 | {0x25c, "DMA_WEIGHT_SRC_HI"}, |
| 1005 | {0x260, "DMA_CMD_SRC"}, |
| 1006 | {0x264, "DMA_CMD_SRC_HI"}, |
| 1007 | {0x268, "DMA_CMD_SIZE"}, |
| 1008 | {0x26c, "DMA_M2M_SRC"}, |
| 1009 | {0x270, "DMA_M2M_SRC_HI"}, |
| 1010 | {0x274, "DMA_M2M_DST"}, |
| 1011 | {0x278, "DMA_M2M_DST_HI"}, |
| 1012 | {0x27c, "CURRENT_QREAD"}, |
| 1013 | {0x280, "DMA_SCALE_SRC"}, |
| 1014 | {0x284, "DMA_SCALE_SRC_HI"}, |
| 1015 | {0x2BC, "CURRENT_CMD"}, |
| 1016 | {0x800, "IFM_PAD_TOP"}, |
| 1017 | {0x804, "IFM_PAD_LEFT"}, |
| 1018 | {0x808, "IFM_PAD_RIGHT"}, |
| 1019 | {0x80C, "IFM_PAD_BOTTOM"}, |
| 1020 | {0x810, "IFM_DEPTH_M1"}, |
| 1021 | {0x814, "IFM_PRECISION"}, |
| 1022 | {0x81C, "IFM_UPSCALE"}, |
| 1023 | {0x824, "IFM_ZERO_POINT"}, |
| 1024 | {0x828, "IFM_WIDTH0_M1"}, |
| 1025 | {0x82C, "IFM_HEIGHT0_M1"}, |
| 1026 | {0x830, "IFM_HEIGHT1_M1"}, |
| 1027 | {0x834, "IFM_IB_END"}, |
| 1028 | {0x83C, "IFM_REGION"}, |
| 1029 | {0x844, "OFM_WIDTH_M1"}, |
| 1030 | {0x848, "OFM_HEIGHT_M1"}, |
| 1031 | {0x84C, "OFM_DEPTH_M1"}, |
| 1032 | {0x850, "OFM_PRECISION"}, |
| 1033 | {0x854, "OFM_BLK_WIDTH_M1"}, |
| 1034 | {0x858, "OFM_BLK_HEIGHT_M1"}, |
| 1035 | {0x85C, "OFM_BLK_DEPTH_M1"}, |
| 1036 | {0x860, "OFM_ZERO_POINT"}, |
| 1037 | {0x868, "OFM_WIDTH0_M1"}, |
| 1038 | {0x86C, "OFM_HEIGHT0_M1"}, |
| 1039 | {0x870, "OFM_HEIGHT1_M1"}, |
| 1040 | {0x87C, "OFM_REGION"}, |
| 1041 | {0x880, "KERNEL_WIDTH_M1"}, |
| 1042 | {0x884, "KERNEL_HEIGHT_M1"}, |
| 1043 | {0x888, "KERNEL_STRIDE"}, |
| 1044 | {0x88C, "PARALLEL_MODE"}, |
| 1045 | {0x890, "ACC_FORMAT"}, |
| 1046 | {0x894, "ACTIVATION"}, |
| 1047 | {0x898, "ACTIVATION_MIN"}, |
| 1048 | {0x89C, "ACTIVATION_MAX"}, |
| 1049 | {0x8A0, "WEIGHT_REGION"}, |
| 1050 | {0x8A4, "SCALE_REGION"}, |
| 1051 | {0x8B4, "AB_START"}, |
| 1052 | {0x8BC, "BLOCKDEP"}, |
| 1053 | {0x8C0, "DMA0_SRC_REGION"}, |
| 1054 | {0x8C4, "DMA0_DST_REGION"}, |
| 1055 | {0x8C8, "DMA0_SIZE0"}, |
| 1056 | {0x8CC, "DMA0_SIZE1"}, |
| 1057 | {0x900, "IFM2_BROADCAST"}, |
| 1058 | {0x904, "IFM2_SCALAR"}, |
| 1059 | {0x924, "IFM2_ZERO_POINT"}, |
| 1060 | {0x928, "IFM2_WIDTH0_M1"}, |
| 1061 | {0x92C, "IFM2_HEIGHT0_M1"}, |
| 1062 | {0x930, "IFM2_HEIGHT1_M1"}, |
| 1063 | {0x934, "IFM2_IB_START"}, |
| 1064 | {0x93C, "IFM2_REGION"}, |
| 1065 | {0xA00, "IFM_BASE0"}, |
| 1066 | {0xA04, "IFM_BASE0_HI"}, |
| 1067 | {0xA08, "IFM_BASE1"}, |
| 1068 | {0xA0C, "IFM_BASE1_HI"}, |
| 1069 | {0xA10, "IFM_BASE2"}, |
| 1070 | {0xA14, "IFM_BASE2_HI"}, |
| 1071 | {0xA18, "IFM_BASE3"}, |
| 1072 | {0xA1C, "IFM_BASE3_HI"}, |
| 1073 | {0xA20, "IFM_STRIDE_X"}, |
| 1074 | {0xA24, "IFM_STRIDE_X_HI"}, |
| 1075 | {0xA28, "IFM_STRIDE_Y"}, |
| 1076 | {0xA2C, "IFM_STRIDE_Y_HI"}, |
| 1077 | {0xA30, "IFM_STRIDE_C"}, |
| 1078 | {0xA34, "IFM_STRIDE_C_HI"}, |
| 1079 | {0xA40, "OFM_BASE0"}, |
| 1080 | {0xA44, "OFM_BASE0_HI"}, |
| 1081 | {0xA48, "OFM_BASE1"}, |
| 1082 | {0xA4C, "OFM_BASE1_HI"}, |
| 1083 | {0xA50, "OFM_BASE2"}, |
| 1084 | {0xA54, "OFM_BASE2_HI"}, |
| 1085 | {0xA58, "OFM_BASE3"}, |
| 1086 | {0xA5C, "OFM_BASE3_HI"}, |
| 1087 | {0xA60, "OFM_STRIDE_X"}, |
| 1088 | {0xA64, "OFM_STRIDE_X_HI"}, |
| 1089 | {0xA68, "OFM_STRIDE_Y"}, |
| 1090 | {0xA6C, "OFM_STRIDE_Y_HI"}, |
| 1091 | {0xA70, "OFM_STRIDE_C"}, |
| 1092 | {0xA74, "OFM_STRIDE_C_HI"}, |
| 1093 | {0xA80, "WEIGHT_BASE"}, |
| 1094 | {0xA84, "WEIGHT_BASE_HI"}, |
| 1095 | {0xA88, "WEIGHT_LENGTH"}, |
| 1096 | {0xA8C, "WEIGHT_LENGTH_HI"}, |
| 1097 | {0xA90, "SCALE_BASE"}, |
| 1098 | {0xA94, "SCALE_BASE_HI"}, |
| 1099 | {0xA98, "SCALE_LENGTH"}, |
| 1100 | {0xAA0, "OFM_SCALE"}, |
| 1101 | {0xAA4, "OFM_SCALE_SHIFT"}, |
| 1102 | {0xAA8, "OPA_SCALE "}, |
| 1103 | {0xAB0, "OPB_SCALE"}, |
| 1104 | {0xAC0, "DMA0_SRC"}, |
| 1105 | {0xAC4, "DMA0_SRC_HI"}, |
| 1106 | {0xAC8, "DMA0_DST"}, |
| 1107 | {0xACC, "DMA0_DST_HI"}, |
| 1108 | {0xAD0, "DMA0_LEN"}, |
| 1109 | {0xAD4, "DMA0_LEN_HI"}, |
| 1110 | {0xAD8, "DMA0_SKIP0"}, |
| 1111 | {0xADC, "DMA0_SKIP0_HI"}, |
| 1112 | {0xAE0, "DMA0_SKIP1"}, |
| 1113 | {0xAE4, "DMA0_SKIP1_HI"}, |
| 1114 | {0xB00, "IFM2_BASE0"}, |
| 1115 | {0xB04, "IFM2_BASE0_HI"}, |
| 1116 | {0xB08, "IFM2_BASE1"}, |
| 1117 | {0xB0C, "IFM2_BASE1_HI"}, |
| 1118 | {0xB10, "IFM2_BASE2"}, |
| 1119 | {0xB14, "IFM2_BASE2_HI"}, |
| 1120 | {0xB18, "IFM2_BASE3"}, |
| 1121 | {0xB1C, "IFM2_BASE3_HI"}, |
| 1122 | {0xB20, "IFM2_STRIDE_X"}, |
| 1123 | {0xB24, "IFM2_STRIDE_X_HI"}, |
| 1124 | {0xB28, "IFM2_STRIDE_Y"}, |
| 1125 | {0xB2C, "IFM2_STRIDE_Y_HI"}, |
| 1126 | {0xB30, "IFM2_STRIDE_C"}, |
| 1127 | {0xB34, "IFM2_STRIDE_C_HI"}, |
| 1128 | {0xB40, "WEIGHT1_BASE"}, |
| 1129 | {0xB44, "WEIGHT1_BASE_HI"}, |
| 1130 | {0xB48, "WEIGHT1_LENGTH"}, |
| 1131 | {0xB4C, "WEIGHT1_LENGTH_HI"}, |
| 1132 | {0xB50, "SCALE1_BASE"}, |
| 1133 | {0xB54, "SCALE1_BASE_HI"}, |
| 1134 | {0xB58, "SCALE1_LENGTH"}, |
| 1135 | }; |
| 1136 | |
| 1137 | static const char *lookup_name(const name_lookup_t *lookup_table, int lookup_table_count, int find) |
| 1138 | { |
| 1139 | int n; |
| 1140 | for (n = 0; n < lookup_table_count; n++) |
| 1141 | { |
| 1142 | if (lookup_table[n].number == find) |
| 1143 | { |
| 1144 | return lookup_table[n].name; |
| 1145 | } |
| 1146 | } |
| 1147 | // Not found |
| 1148 | return 0; |
| 1149 | } |
| 1150 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 1151 | static void dump_npu_register(struct ethosu_driver *drv, int npu_reg, int npu_reg_end) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 1152 | { |
| 1153 | unsigned int reg_val; |
| 1154 | const char *reg_name; |
| 1155 | int npu_reg_name_tbl_count = sizeof(npu_reg_name_tbl) / sizeof(npu_reg_name_tbl[0]); |
| 1156 | |
| 1157 | LOG_INFO("dump_register %X - %X\n", npu_reg, npu_reg_end); |
| 1158 | for (; npu_reg <= npu_reg_end; npu_reg += sizeof(int)) |
| 1159 | { |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 1160 | reg_val = ethosu_read_reg(&drv->dev, npu_reg); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 1161 | reg_name = lookup_name(npu_reg_name_tbl, npu_reg_name_tbl_count, npu_reg); |
| 1162 | LOG_INFO("[0x%.4X] 0x%.8X\t%s\n", npu_reg, reg_val, (reg_name) ? reg_name : ""); |
| 1163 | } |
| 1164 | } |
| 1165 | |
| 1166 | static const name_lookup_t cmd0_name_tbl[] = { |
| 1167 | {0x000, "NPU_OP_STOP"}, |
| 1168 | {0x001, "NPU_OP_IRQ"}, |
| 1169 | {0x002, "NPU_OP_CONV"}, |
| 1170 | {0x003, "NPU_OP_DEPTHWISE"}, |
| 1171 | {0x004, "NPU_OP_VECTOR_PROD"}, |
| 1172 | {0x005, "NPU_OP_POOL"}, |
| 1173 | {0x006, "NPU_OP_ELEMENTWISE"}, |
| 1174 | {0x010, "NPU_OP_DMA_START"}, |
| 1175 | {0x011, "NPU_OP_DMA_WAIT"}, |
| 1176 | {0x012, "NPU_OP_KERNEL_WAIT"}, |
| 1177 | {0x100, "NPU_SET_IFM_PAD_TOP"}, |
| 1178 | {0x101, "NPU_SET_IFM_PAD_LEFT"}, |
| 1179 | {0x102, "NPU_SET_IFM_PAD_RIGHT"}, |
| 1180 | {0x103, "NPU_SET_IFM_PAD_BOTTOM"}, |
| 1181 | {0x104, "NPU_SET_IFM_DEPTH_M1"}, |
| 1182 | {0x105, "NPU_SET_IFM_PRECISION"}, |
| 1183 | {0x107, "NPU_SET_IFM_UPSCALE"}, |
| 1184 | {0x109, "NPU_SET_IFM_ZERO_POINT"}, |
| 1185 | {0x10A, "NPU_SET_IFM_WIDTH0_M1"}, |
| 1186 | {0x10B, "NPU_SET_IFM_HEIGHT0_M1"}, |
| 1187 | {0x10C, "NPU_SET_IFM_HEIGHT1_M1"}, |
| 1188 | {0x10D, "NPU_SET_IFM_IB_END"}, |
| 1189 | {0x10F, "NPU_SET_IFM_REGION"}, |
| 1190 | {0x110, "NPU_SET_OFM_BATCH_SIZE_M1"}, |
| 1191 | {0x111, "NPU_SET_OFM_WIDTH_M1"}, |
| 1192 | {0x112, "NPU_SET_OFM_HEIGHT_M1"}, |
| 1193 | {0x113, "NPU_SET_OFM_DEPTH_M1"}, |
| 1194 | {0x114, "NPU_SET_OFM_PRECISION"}, |
| 1195 | {0x115, "NPU_SET_OFM_BLK_WIDTH_M1"}, |
| 1196 | {0x116, "NPU_SET_OFM_BLK_HEIGHT_M1"}, |
| 1197 | {0x117, "NPU_SET_OFM_BLK_DEPTH_M1"}, |
| 1198 | {0x118, "NPU_SET_OFM_ZERO_POINT"}, |
| 1199 | {0x11A, "NPU_SET_OFM_WIDTH0_M1"}, |
| 1200 | {0x11B, "NPU_SET_OFM_HEIGHT0_M1"}, |
| 1201 | {0x11C, "NPU_SET_OFM_HEIGHT1_M1"}, |
| 1202 | {0x11F, "NPU_SET_OFM_REGION"}, |
| 1203 | {0x120, "NPU_SET_KERNEL_WIDTH_M1"}, |
| 1204 | {0x121, "NPU_SET_KERNEL_HEIGHT_M1"}, |
| 1205 | {0x122, "NPU_SET_KERNEL_STRIDE"}, |
| 1206 | {0x124, "NPU_SET_ACC_FORMAT"}, |
| 1207 | {0x125, "NPU_SET_ACTIVATION"}, |
| 1208 | {0x126, "NPU_SET_ACTIVATION_MIN"}, |
| 1209 | {0x127, "NPU_SET_ACTIVATION_MAX"}, |
| 1210 | {0x128, "NPU_SET_WEIGHT_REGION"}, |
| 1211 | {0x129, "NPU_SET_SCALE_REGION"}, |
| 1212 | {0x12D, "NPU_SET_AB_START"}, |
| 1213 | {0x12F, "NPU_SET_BLOCKDEP"}, |
| 1214 | {0x130, "NPU_SET_DMA0_SRC_REGION"}, |
| 1215 | {0x131, "NPU_SET_DMA0_DST_REGION"}, |
| 1216 | {0x180, "NPU_SET_IFM2_BROADCAST"}, |
| 1217 | {0x181, "NPU_SET_IFM2_SCALAR"}, |
| 1218 | {0x185, "NPU_SET_IFM2_PRECISION"}, |
| 1219 | {0x189, "NPU_SET_IFM2_ZERO_POINT"}, |
| 1220 | {0x18A, "NPU_SET_IFM2_WIDTH0_M1"}, |
| 1221 | {0x18B, "NPU_SET_IFM2_HEIGHT0_M1"}, |
| 1222 | {0x18C, "NPU_SET_IFM2_HEIGHT1_M1"}, |
| 1223 | {0x18D, "NPU_SET_IFM2_IB_START"}, |
| 1224 | {0x18F, "NPU_SET_IFM2_REGION"}, |
| 1225 | }; |
| 1226 | |
| 1227 | static const name_lookup_t cmd1_name_tbl[] = { |
| 1228 | {0x000, "NPU_SET_IFM_BASE0"}, {0x001, "NPU_SET_IFM_BASE1"}, {0x002, "NPU_SET_IFM_BASE2"}, |
| 1229 | {0x003, "NPU_SET_IFM_BASE3"}, {0x004, "NPU_SET_IFM_STRIDE_X"}, {0x005, "NPU_SET_IFM_STRIDE_Y"}, |
| 1230 | {0x006, "NPU_SET_IFM_STRIDE_C"}, {0x007, "NPU_SET_IFM_STRIDE_N"}, {0x010, "NPU_SET_OFM_BASE0"}, |
| 1231 | {0x011, "NPU_SET_OFM_BASE1"}, {0x012, "NPU_SET_OFM_BASE2"}, {0x013, "NPU_SET_OFM_BASE3"}, |
| 1232 | {0x014, "NPU_SET_OFM_STRIDE_X"}, {0x015, "NPU_SET_OFM_STRIDE_Y"}, {0x016, "NPU_SET_OFM_STRIDE_C"}, |
| 1233 | {0x017, "NPU_SET_OFM_STRIDE_N"}, {0x020, "NPU_SET_WEIGHT_BASE"}, {0x021, "NPU_SET_WEIGHT_LENGTH"}, |
| 1234 | {0x022, "NPU_SET_SCALE_BASE"}, {0x023, "NPU_SET_SCALE_LENGTH"}, {0x024, "NPU_SET_OFM_SCALE"}, |
| 1235 | {0x025, "NPU_SET_OPA_SCALE"}, {0x026, "NPU_SET_OPB_SCALE"}, {0x030, "NPU_SET_DMA0_SRC"}, |
| 1236 | {0x031, "NPU_SET_DMA0_DST"}, {0x032, "NPU_SET_DMA0_LEN"}, {0x080, "NPU_SET_IFM2_BASE0"}, |
| 1237 | {0x081, "NPU_SET_IFM2_BASE1"}, {0x082, "NPU_SET_IFM2_BASE2"}, {0x083, "NPU_SET_IFM2_BASE3"}, |
| 1238 | {0x084, "NPU_SET_IFM2_STRIDE_X"}, {0x085, "NPU_SET_IFM2_STRIDE_Y"}, {0x086, "NPU_SET_IFM2_STRIDE_C"}, |
| 1239 | }; |
| 1240 | |
| 1241 | static void dump_command_stream(const uint32_t *cmd_stream, const int cms_length, int qread) |
| 1242 | { |
| 1243 | int n; |
| 1244 | int offset; |
| 1245 | uint32_t cmd_val; |
| 1246 | const uint8_t *cmd_ptr; |
| 1247 | const char *cmd_name; |
| 1248 | int cmd0_name_tbl_count = sizeof(cmd0_name_tbl) / sizeof(cmd0_name_tbl[0]); |
| 1249 | int cmd1_name_tbl_count = sizeof(cmd1_name_tbl) / sizeof(cmd1_name_tbl[0]); |
| 1250 | |
| 1251 | LOG_INFO("dump_command_stream cmd_stream = 0x%8p cms_length = %d\n", cmd_stream, cms_length); |
| 1252 | for (n = 0; n < cms_length; n++) |
| 1253 | { |
| 1254 | // Offset |
| 1255 | offset = n * sizeof(int); |
| 1256 | LOG_INFO("[%.4d] ", offset); |
| 1257 | // Command |
| 1258 | cmd_ptr = (const uint8_t *)&cmd_stream[n]; |
| 1259 | LOG_INFO("0x%.2X 0x%.2X 0x%.2X 0x%.2X ", cmd_ptr[0], cmd_ptr[1], cmd_ptr[2], cmd_ptr[3]); |
| 1260 | // Command name and payload |
| 1261 | if (cmd_stream[n] & 0x4000) |
| 1262 | { |
| 1263 | cmd_name = lookup_name(cmd1_name_tbl, cmd1_name_tbl_count, cmd_stream[n] & 0x3FF); |
| 1264 | n++; |
| 1265 | cmd_val = cmd_stream[n]; |
| 1266 | cmd_ptr = (const uint8_t *)&cmd_stream[n]; |
| 1267 | LOG_INFO("0x%.2X 0x%.2X 0x%.2X 0x%.2X ", cmd_ptr[0], cmd_ptr[1], cmd_ptr[2], cmd_ptr[3]); |
| 1268 | } |
| 1269 | else |
| 1270 | { |
| 1271 | cmd_val = cmd_stream[n] >> 16; |
| 1272 | cmd_name = lookup_name(cmd0_name_tbl, cmd0_name_tbl_count, cmd_stream[n] & 0x3FF); |
| 1273 | } |
| 1274 | if (cmd_name) |
| 1275 | { |
Per Åstrand | 14ccfee | 2020-09-25 10:40:20 +0200 | [diff] [blame] | 1276 | LOG_INFO("\t%s 0x%.8" PRIX32, cmd_name, cmd_val); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 1277 | } |
| 1278 | if (offset == qread) |
| 1279 | { |
| 1280 | LOG_INFO(" <<== QREAD\n"); |
| 1281 | } |
| 1282 | else |
| 1283 | { |
| 1284 | LOG_INFO("\n"); |
| 1285 | } |
| 1286 | } |
| 1287 | } |