Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2019-2020 Arm Limited. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: Apache-2.0 |
| 5 | * |
| 6 | * Licensed under the Apache License, Version 2.0 (the License); you may |
| 7 | * not use this file except in compliance with the License. |
| 8 | * You may obtain a copy of the License at |
| 9 | * |
| 10 | * www.apache.org/licenses/LICENSE-2.0 |
| 11 | * |
| 12 | * Unless required by applicable law or agreed to in writing, software |
| 13 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT |
| 14 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 15 | * See the License for the specific language governing permissions and |
| 16 | * limitations under the License. |
| 17 | */ |
| 18 | |
| 19 | #include "ethosu_driver.h" |
| 20 | |
| 21 | #include "ethosu_common.h" |
| 22 | #include "ethosu_device.h" |
Per Åstrand | 25d78c0 | 2020-04-21 14:19:44 +0200 | [diff] [blame] | 23 | |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 24 | #include <assert.h> |
Per Åstrand | 25d78c0 | 2020-04-21 14:19:44 +0200 | [diff] [blame] | 25 | #include <cmsis_compiler.h> |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 26 | #include <stdbool.h> |
| 27 | #include <stdint.h> |
| 28 | #include <stdio.h> |
| 29 | #include <stdlib.h> |
| 30 | |
| 31 | // Abort flag |
| 32 | static int abort_inference = false; |
| 33 | |
| 34 | // IRQ |
| 35 | static volatile bool irq_triggered = false; |
| 36 | #if defined(CPU_CORTEX_M3) || defined(CPU_CORTEX_M4) || defined(CPU_CORTEX_M7) || defined(CPU_CORTEX_M33) || \ |
| 37 | defined(CPU_CORTEX_M55) |
Per Åstrand | 25d78c0 | 2020-04-21 14:19:44 +0200 | [diff] [blame] | 38 | void ethosu_irq_handler(void) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 39 | { |
| 40 | uint8_t irq_raised = 0; |
| 41 | (void)ethosu_is_irq_raised(&irq_raised); |
| 42 | ASSERT(irq_raised == 1); |
| 43 | irq_triggered = true; |
| 44 | (void)ethosu_clear_irq_status(); |
| 45 | (void)ethosu_is_irq_raised(&irq_raised); |
| 46 | ASSERT(irq_raised == 0); |
| 47 | } |
| 48 | |
| 49 | static inline void wait_for_irq(void) |
| 50 | { |
| 51 | while (1) |
| 52 | { |
| 53 | __disable_irq(); |
| 54 | if (irq_triggered || abort_inference) |
| 55 | { |
| 56 | __enable_irq(); |
| 57 | break; |
| 58 | } |
| 59 | |
Per Åstrand | 25d78c0 | 2020-04-21 14:19:44 +0200 | [diff] [blame] | 60 | __WFI(); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 61 | |
| 62 | __enable_irq(); |
| 63 | } |
| 64 | } |
| 65 | #else |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 66 | // Just polling the status register |
| 67 | static inline void wait_for_irq(void) |
| 68 | { |
| 69 | uint8_t irq_raised = 0; |
| 70 | |
| 71 | for (int i = 0; i < 5000; ++i) |
| 72 | { |
| 73 | (void)ethosu_is_irq_raised(&irq_raised); |
| 74 | if (1 == irq_raised) |
| 75 | { |
| 76 | break; |
| 77 | } |
| 78 | } |
| 79 | ASSERT(1 == irq_raised); |
| 80 | |
| 81 | irq_triggered = true; |
| 82 | } |
| 83 | #endif |
| 84 | |
| 85 | #define MACS_PER_CYCLE_LOG2_MASK 0x000F |
| 86 | #define SHRAM_SIZE_MASK 0xFF00 |
| 87 | #define SHRAM_SIZE_RIGHT_SHIFT 8 |
| 88 | #define BYTES_IN_32_BITS 4 |
| 89 | #define CUSTOM_OPTION_LENGTH_32_BIT_WORD 1 |
| 90 | #define DRIVER_ACTION_LENGTH_32_BIT_WORD 1 |
| 91 | #define OPTIMIZER_CONFIG_LENGTH_32_BIT_WORD 2 |
| 92 | #define ETHOSU_FOURCC ('1' << 24 | 'P' << 16 | 'O' << 8 | 'C') // "Custom Operator Payload 1" |
| 93 | #define APB_START_ADDR_MASK 0x0FFF |
| 94 | #define APB_NUM_REG_BIT_SHIFT 12 |
| 95 | #define CMS_ALIGNMENT 16 |
| 96 | #define BYTES_1KB 1024 |
| 97 | |
| 98 | // Driver actions |
| 99 | enum DRIVER_ACTION_e |
| 100 | { |
| 101 | RESERVED = 0, |
| 102 | OPTIMIZER_CONFIG = 1, |
| 103 | COMMAND_STREAM = 2, |
| 104 | READ_APB_REG = 3, |
| 105 | DUMP_SHRAM = 4, |
| 106 | NOP = 5, |
| 107 | }; |
| 108 | |
| 109 | // Custom data struct |
| 110 | struct custom_data_s |
| 111 | { |
| 112 | union |
| 113 | { |
| 114 | // Driver action data |
| 115 | struct |
| 116 | { |
| 117 | // Driver action command (valid values in DRIVER_ACTION_e) |
| 118 | uint8_t driver_action_command; |
| 119 | // reserved |
| 120 | uint8_t reserved; |
| 121 | // Driver action data |
| 122 | union |
| 123 | { |
| 124 | struct |
| 125 | { // DA_CMD_OPT_CFG |
| 126 | uint16_t rel_nbr : 4; |
| 127 | uint16_t patch_nbr : 4; |
| 128 | uint16_t opt_cfg_reserved : 8; |
| 129 | }; |
| 130 | struct |
| 131 | { // DA_CMD_CMSTRM |
| 132 | uint16_t length; |
| 133 | }; |
| 134 | struct |
| 135 | { // DA_CMD_READAPB |
| 136 | uint16_t start_address : 12; |
| 137 | uint16_t nbr_reg_minus1 : 4; |
| 138 | }; |
| 139 | uint16_t driver_action_data; |
| 140 | }; |
| 141 | }; |
| 142 | uint32_t word; |
| 143 | }; |
| 144 | }; |
| 145 | |
| 146 | // optimizer config struct |
| 147 | struct opt_cfg_s |
| 148 | { |
| 149 | struct custom_data_s da_data; |
| 150 | union |
| 151 | { |
| 152 | struct |
| 153 | { |
| 154 | uint32_t macs_per_cc : 4; |
| 155 | uint32_t cmd_stream_version : 4; |
| 156 | uint32_t shram_size : 8; |
| 157 | uint32_t reserved1 : 16; |
| 158 | }; |
| 159 | uint32_t npu_cfg; |
| 160 | }; |
| 161 | union |
| 162 | { |
| 163 | struct |
| 164 | { |
| 165 | uint32_t version_status : 4; |
| 166 | uint32_t version_minor : 4; |
| 167 | uint32_t version_major : 4; |
| 168 | uint32_t product_major : 4; |
| 169 | uint32_t arch_patch_rev : 4; |
| 170 | uint32_t arch_minor_rev : 8; |
| 171 | uint32_t arch_major_rev : 4; |
| 172 | }; |
| 173 | uint32_t ethosu_id; |
| 174 | }; |
| 175 | }; |
| 176 | |
| 177 | static int handle_optimizer_config(struct opt_cfg_s *opt_cfg_p); |
| 178 | static int handle_command_stream(const uint8_t *cmd_stream, |
| 179 | const int cms_length, |
| 180 | const uint64_t *base_addr, |
| 181 | const int num_base_addr); |
| 182 | static int read_apb_reg(uint16_t); |
| 183 | static int dump_shram(); |
| 184 | static void dump_npu_register(int npu_reg, int npu_reg_end); |
| 185 | static void dump_command_stream(const uint32_t *cmd_stream, const int cms_length, int qread); |
| 186 | |
| 187 | int ethosu_init(void) |
| 188 | { |
| 189 | int return_code = 0; |
| 190 | LOG_INFO("ethosu_init calling NPU embed driver ethosu_dev_init\n"); |
| 191 | |
| 192 | #ifdef FPGA |
| 193 | ethosu_soft_reset(); |
| 194 | #endif |
| 195 | if (ETHOSU_SUCCESS != ethosu_wait_for_reset()) |
| 196 | { |
| 197 | LOG_ERR("Failed reset of Ethos-U\n"); |
| 198 | return -1; |
| 199 | } |
| 200 | |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 201 | return_code = ethosu_dev_init(); |
| 202 | |
| 203 | return return_code; |
| 204 | } |
| 205 | |
| 206 | int ethosu_get_version(struct ethosu_version *version) |
| 207 | { |
| 208 | int return_code = 0; |
| 209 | |
| 210 | if (NULL != version) |
| 211 | { |
| 212 | struct ethosu_id id; |
| 213 | struct ethosu_config cfg; |
| 214 | (void)ethosu_get_id(&id); |
| 215 | (void)ethosu_get_config(&cfg); |
| 216 | |
| 217 | version->id.version_status = id.version_status; |
| 218 | version->id.version_minor = id.version_minor; |
| 219 | version->id.version_major = id.version_major; |
| 220 | version->id.product_major = id.product_major; |
| 221 | version->id.arch_patch_rev = id.arch_patch_rev; |
| 222 | version->id.arch_minor_rev = id.arch_minor_rev; |
| 223 | version->id.arch_major_rev = id.arch_major_rev; |
| 224 | version->id.driver_patch_rev = ETHOSU_DRIVER_VERSION_PATCH; |
| 225 | version->id.driver_minor_rev = ETHOSU_DRIVER_VERSION_MINOR; |
| 226 | version->id.driver_major_rev = ETHOSU_DRIVER_VERSION_MAJOR; |
| 227 | version->cfg.macs_per_cc = cfg.macs_per_cc; |
| 228 | version->cfg.cmd_stream_version = cfg.cmd_stream_version; |
| 229 | version->cfg.shram_size = cfg.shram_size; |
| 230 | } |
| 231 | else |
| 232 | { |
| 233 | return_code = -1; |
| 234 | } |
| 235 | |
| 236 | return return_code; |
| 237 | } |
| 238 | |
| 239 | int ethosu_invoke(const void *custom_data_ptr, |
| 240 | const int custom_data_size, |
| 241 | const uint64_t *base_addr, |
| 242 | const int num_base_addr) |
| 243 | { |
| 244 | struct custom_data_s *data_start_ptr = (struct custom_data_s *)custom_data_ptr; |
| 245 | int return_code = 0; |
| 246 | |
| 247 | LOG_INFO("ethosu_invoke\n"); |
| 248 | |
| 249 | // First word in custom_data_ptr should contain "Custom Operator Payload 1" |
| 250 | if (data_start_ptr->word != ETHOSU_FOURCC) |
| 251 | { |
| 252 | LOG_ERR("Custom Operator Payload: %x is not correct, expected %x\n", data_start_ptr->word, ETHOSU_FOURCC); |
| 253 | return -1; |
| 254 | } |
| 255 | data_start_ptr += CUSTOM_OPTION_LENGTH_32_BIT_WORD; |
| 256 | struct custom_data_s *data_ptr = data_start_ptr; |
| 257 | |
| 258 | if ((custom_data_size % BYTES_IN_32_BITS) != 0) |
| 259 | { |
| 260 | LOG_ERR("ethosu_invoke ERROR custom_data_size=0x%x not a multiple of 4\n", custom_data_size); |
| 261 | return -1; |
| 262 | } |
| 263 | int custom_data_32bit_size = (custom_data_size / BYTES_IN_32_BITS - CUSTOM_OPTION_LENGTH_32_BIT_WORD); |
| 264 | |
| 265 | while (data_ptr < (data_start_ptr + custom_data_32bit_size)) |
| 266 | { |
| 267 | switch (data_ptr->driver_action_command) |
| 268 | { |
| 269 | case OPTIMIZER_CONFIG: |
| 270 | LOG_INFO("ethosu_invoke OPTIMIZER_CONFIG\n"); |
| 271 | struct opt_cfg_s *opt_cfg_p = (struct opt_cfg_s *)data_ptr; |
| 272 | |
| 273 | return_code = handle_optimizer_config(opt_cfg_p); |
| 274 | data_ptr += DRIVER_ACTION_LENGTH_32_BIT_WORD + OPTIMIZER_CONFIG_LENGTH_32_BIT_WORD; |
| 275 | break; |
| 276 | case COMMAND_STREAM: |
| 277 | LOG_INFO("ethosu_invoke COMMAND_STREAM\n"); |
| 278 | void *command_stream = (uint8_t *)(data_ptr) + sizeof(struct custom_data_s); |
| 279 | int cms_length = (data_ptr->reserved << 16) | data_ptr->length; |
| 280 | |
| 281 | abort_inference = false; |
| 282 | // It is safe to clear this flag without atomic, because npu is not running. |
| 283 | irq_triggered = false; |
| 284 | |
| 285 | return_code = handle_command_stream(command_stream, cms_length, base_addr, num_base_addr); |
| 286 | |
| 287 | if (return_code == -1 && abort_inference) |
| 288 | { |
| 289 | uint32_t qread = 0; |
| 290 | ethosu_get_qread(&qread); |
| 291 | LOG_ERR("NPU timeout\n"); |
| 292 | dump_command_stream(command_stream, cms_length, qread); |
| 293 | dump_npu_register(0x200, 0x2BF); |
| 294 | dump_npu_register(0x800, 0xB3F); |
| 295 | dump_shram(); |
| 296 | } |
| 297 | |
| 298 | data_ptr += DRIVER_ACTION_LENGTH_32_BIT_WORD + cms_length; |
| 299 | break; |
| 300 | case READ_APB_REG: |
| 301 | LOG_INFO("ethosu_invoke READ_APB_REG\n"); |
| 302 | return_code = read_apb_reg(data_ptr->driver_action_data); |
| 303 | data_ptr += DRIVER_ACTION_LENGTH_32_BIT_WORD; |
| 304 | break; |
| 305 | case DUMP_SHRAM: |
| 306 | LOG_INFO("ethosu_invoke DUMP_SHRAM\n"); |
| 307 | return_code = dump_shram(); |
| 308 | data_ptr += DRIVER_ACTION_LENGTH_32_BIT_WORD; |
| 309 | break; |
| 310 | case NOP: |
| 311 | LOG_INFO("ethosu_invoke NOP\n"); |
| 312 | data_ptr += DRIVER_ACTION_LENGTH_32_BIT_WORD; |
| 313 | break; |
| 314 | default: |
| 315 | LOG_ERR("ethosu_invoke UNSUPPORTED driver_action_command %d \n", data_ptr->driver_action_command); |
| 316 | return -1; |
| 317 | break; |
| 318 | } |
| 319 | if (return_code != 0) |
| 320 | { |
| 321 | return -1; |
| 322 | } |
| 323 | } |
| 324 | return 0; |
| 325 | } |
| 326 | |
| 327 | void ethosu_abort(void) |
| 328 | { |
| 329 | abort_inference = true; |
| 330 | } |
| 331 | |
| 332 | static int handle_optimizer_config(struct opt_cfg_s *opt_cfg_p) |
| 333 | { |
| 334 | struct ethosu_config cfg; |
| 335 | struct ethosu_id id; |
| 336 | int return_code = 0; |
| 337 | |
| 338 | LOG_INFO("handle_optimizer_config:\n"); |
| 339 | LOG_INFO("Optimizer release nbr: %d patch: %d\n", opt_cfg_p->da_data.rel_nbr, opt_cfg_p->da_data.patch_nbr); |
| 340 | LOG_INFO("Optimizer config cmd_stream_version: %d macs_per_cc: %d shram_size: %d\n", |
| 341 | opt_cfg_p->cmd_stream_version, |
| 342 | opt_cfg_p->macs_per_cc, |
| 343 | opt_cfg_p->shram_size); |
| 344 | LOG_INFO("Optimizer config Ethos-U version: %d.%d.%d\n", |
| 345 | opt_cfg_p->arch_major_rev, |
| 346 | opt_cfg_p->arch_minor_rev, |
| 347 | opt_cfg_p->arch_patch_rev); |
| 348 | |
| 349 | (void)ethosu_get_config(&cfg); |
| 350 | (void)ethosu_get_id(&id); |
| 351 | LOG_INFO("Ethos-U config cmd_stream_version: %d macs_per_cc: %d shram_size: %d\n", |
| 352 | cfg.cmd_stream_version, |
| 353 | cfg.macs_per_cc, |
| 354 | cfg.shram_size); |
| 355 | LOG_INFO("Ethos-U version: %d.%d.%d\n", id.arch_major_rev, id.arch_minor_rev, id.arch_patch_rev); |
| 356 | |
| 357 | if ((cfg.macs_per_cc != opt_cfg_p->macs_per_cc) || (cfg.shram_size != opt_cfg_p->shram_size) || |
| 358 | (cfg.cmd_stream_version != opt_cfg_p->cmd_stream_version)) |
| 359 | { |
| 360 | if (cfg.macs_per_cc != opt_cfg_p->macs_per_cc) |
| 361 | { |
| 362 | LOG_ERR("NPU config mismatch: npu.macs_per_cc=%d optimizer.macs_per_cc=%d\n", |
| 363 | cfg.macs_per_cc, |
| 364 | opt_cfg_p->macs_per_cc); |
| 365 | } |
| 366 | if (cfg.shram_size != opt_cfg_p->shram_size) |
| 367 | { |
| 368 | LOG_ERR("NPU config mismatch: npu.shram_size=%d optimizer.shram_size=%d\n", |
| 369 | cfg.shram_size, |
| 370 | opt_cfg_p->shram_size); |
| 371 | } |
| 372 | if (cfg.cmd_stream_version != opt_cfg_p->cmd_stream_version) |
| 373 | { |
| 374 | LOG_ERR("NPU config mismatch: npu.cmd_stream_version=%d optimizer.cmd_stream_version=%d\n", |
| 375 | cfg.cmd_stream_version, |
| 376 | opt_cfg_p->cmd_stream_version); |
| 377 | } |
| 378 | return_code = -1; |
| 379 | } |
| 380 | |
| 381 | if ((id.arch_major_rev != opt_cfg_p->arch_major_rev) || (id.arch_minor_rev != opt_cfg_p->arch_minor_rev) || |
| 382 | (id.arch_patch_rev != opt_cfg_p->arch_patch_rev)) |
| 383 | { |
| 384 | // fLOG_INFO(stderr, |
| 385 | // "NPU arch mismatch: npu.arch=%d.%d.%d optimizer.arch=%d.%d.%d\n", |
| 386 | // id.arch_major_rev, |
| 387 | // id.arch_minor_rev, |
| 388 | // id.arch_patch_rev, |
| 389 | // opt_cfg_p->arch_major_rev, |
| 390 | // opt_cfg_p->arch_minor_rev, |
| 391 | // opt_cfg_p->arch_patch_rev); |
| 392 | // return_code = -1; |
| 393 | } |
| 394 | |
| 395 | #if !defined(LOG_ENABLED) |
| 396 | UNUSED(opt_cfg_p); |
| 397 | #endif |
| 398 | return return_code; |
| 399 | } |
| 400 | |
| 401 | void __attribute__((weak)) npu_axi_init() |
| 402 | { |
| 403 | // TODO Power on |
| 404 | |
| 405 | // TODO Set qconfig |
| 406 | ethosu_set_qconfig(0); |
| 407 | |
| 408 | // TODO Set region config |
| 409 | ethosu_set_regioncfg(0, 0); |
| 410 | ethosu_set_regioncfg(1, 0); |
| 411 | ethosu_set_regioncfg(2, 0); |
| 412 | ethosu_set_regioncfg(3, 0); |
| 413 | ethosu_set_regioncfg(4, 0); |
| 414 | ethosu_set_regioncfg(5, 0); |
| 415 | ethosu_set_regioncfg(6, 0); |
| 416 | ethosu_set_regioncfg(7, 0); |
| 417 | } |
| 418 | |
| 419 | static int handle_command_stream(const uint8_t *cmd_stream, |
| 420 | const int cms_length, |
| 421 | const uint64_t *base_addr, |
| 422 | const int num_base_addr) |
| 423 | { |
| 424 | uint32_t qread = 0; |
| 425 | uint32_t cms_bytes = cms_length * BYTES_IN_32_BITS; |
| 426 | LOG_INFO("handle_command_stream cms_length %d\n", cms_length); |
| 427 | |
| 428 | if (((uint32_t)cmd_stream % CMS_ALIGNMENT) != 0) |
| 429 | { |
| 430 | LOG_ERR("Failure: Command stream addr %p not aligned to 16 bytes\n", cmd_stream); |
| 431 | return -1; |
| 432 | } |
| 433 | npu_axi_init(); |
| 434 | |
| 435 | ethosu_run_command_stream(cmd_stream, cms_bytes, base_addr, num_base_addr); |
| 436 | |
| 437 | wait_for_irq(); |
| 438 | |
| 439 | (void)ethosu_get_qread(&qread); |
| 440 | if (qread != cms_bytes) |
| 441 | { |
| 442 | LOG_ERR("Failure: IRQ received but qread (%d) not at end of stream (%d).\n", qread, cms_bytes); |
| 443 | return -1; |
| 444 | } |
| 445 | |
| 446 | // TODO Power off |
| 447 | return 0; |
| 448 | } |
| 449 | |
| 450 | static int read_apb_reg(uint16_t da_data) |
| 451 | { |
| 452 | uint32_t *reg_p; |
| 453 | uint32_t start_address = (uint32_t)(da_data & APB_START_ADDR_MASK); |
| 454 | uint16_t num_reg = (da_data >> APB_NUM_REG_BIT_SHIFT) + 1; |
| 455 | |
| 456 | reg_p = (uint32_t *)malloc(num_reg * sizeof(uint32_t)); |
| 457 | if (reg_p == NULL) |
| 458 | { |
| 459 | LOG_INFO("read_apb_reg, Error! memory not allocated."); |
| 460 | return -1; |
| 461 | } |
| 462 | |
| 463 | if (ETHOSU_SUCCESS == ethosu_read_apb_reg(start_address, num_reg, reg_p)) |
| 464 | { |
| 465 | for (int i = 0; i < num_reg; i++) |
| 466 | { |
| 467 | LOG_INFO("NPU_REG ADDR 0x%04x = 0x%08x\n", (start_address + (i * BYTES_IN_32_BITS)), reg_p[i]); |
| 468 | } |
| 469 | } |
| 470 | else |
| 471 | { |
| 472 | free(reg_p); |
| 473 | return -1; |
| 474 | } |
| 475 | |
| 476 | free(reg_p); |
| 477 | return 0; |
| 478 | } |
| 479 | |
| 480 | static int dump_shram() |
| 481 | { |
| 482 | struct ethosu_config cfg; |
| 483 | uint32_t *shram_p; |
| 484 | (void)ethosu_get_config(&cfg); |
| 485 | |
| 486 | LOG_INFO("dump_shram size = %d KB\n", cfg.shram_size); |
| 487 | |
| 488 | shram_p = (uint32_t *)malloc(BYTES_1KB); |
| 489 | if (shram_p == NULL) |
| 490 | { |
| 491 | LOG_ERR("read_shram, Error! memory not allocated."); |
| 492 | return -1; |
| 493 | } |
| 494 | |
| 495 | for (uint32_t i = 0; i < cfg.shram_size; i++) |
| 496 | { |
| 497 | ethosu_get_shram_data(i, (uint32_t *)shram_p); |
| 498 | // Output 1KB of SHRAM |
| 499 | LOG_INFO("***SHRAM SECTION %d***\n", i); |
| 500 | for (int j = 0; j < (BYTES_1KB / BYTES_IN_32_BITS); j++) |
| 501 | { |
| 502 | LOG_INFO("[0x%04x] %x\n", (i * 1024 + j * 4), shram_p[j]); |
| 503 | } |
| 504 | } |
| 505 | free(shram_p); |
| 506 | |
| 507 | return 0; |
| 508 | } |
| 509 | |
| 510 | typedef struct |
| 511 | { |
| 512 | int number; |
| 513 | const char *name; |
| 514 | } name_lookup_t; |
| 515 | |
| 516 | static const name_lookup_t npu_reg_name_tbl[] = { |
| 517 | {0x200, "KERNEL_X"}, |
| 518 | {0x204, "KERNEL_Y"}, |
| 519 | {0x208, "KERNEL_W_M1"}, |
| 520 | {0x20C, "KERNEL_H_M1"}, |
| 521 | {0x210, "OFM_CBLK_WIDTH_M1"}, |
| 522 | {0x214, "OFM_CBLK_HEIGHT_M1"}, |
| 523 | {0x218, "OFM_CBLK_DEPTH_M1"}, |
| 524 | {0x21c, "IFM_CBLK_DEPTH_M1"}, |
| 525 | {0x220, "OFM_X"}, |
| 526 | {0x224, "OFM_Y"}, |
| 527 | {0x228, "OFM_Z"}, |
| 528 | {0x22C, "IFM_Z"}, |
| 529 | {0x230, "PAD_TOP"}, |
| 530 | {0x234, "PAD_LEFT"}, |
| 531 | {0x238, "IFM_CBLK_WIDTH"}, |
| 532 | {0x23C, "IFM_CBLK_HEIGHT"}, |
| 533 | {0x240, "DMA_IFM_SRC"}, |
| 534 | {0x244, "DMA_IFM_SRC_HI"}, |
| 535 | {0x248, "DMA_IFM_DST"}, |
| 536 | {0x24c, "DMA_OFM_SRC"}, |
| 537 | {0x250, "DMA_OFM_DST"}, |
| 538 | {0x254, "DMA_OFM_DST_HI"}, |
| 539 | {0x258, "DMA_WEIGHT_SRC"}, |
| 540 | {0x25c, "DMA_WEIGHT_SRC_HI"}, |
| 541 | {0x260, "DMA_CMD_SRC"}, |
| 542 | {0x264, "DMA_CMD_SRC_HI"}, |
| 543 | {0x268, "DMA_CMD_SIZE"}, |
| 544 | {0x26c, "DMA_M2M_SRC"}, |
| 545 | {0x270, "DMA_M2M_SRC_HI"}, |
| 546 | {0x274, "DMA_M2M_DST"}, |
| 547 | {0x278, "DMA_M2M_DST_HI"}, |
| 548 | {0x27c, "CURRENT_QREAD"}, |
| 549 | {0x280, "DMA_SCALE_SRC"}, |
| 550 | {0x284, "DMA_SCALE_SRC_HI"}, |
| 551 | {0x2BC, "CURRENT_CMD"}, |
| 552 | {0x800, "IFM_PAD_TOP"}, |
| 553 | {0x804, "IFM_PAD_LEFT"}, |
| 554 | {0x808, "IFM_PAD_RIGHT"}, |
| 555 | {0x80C, "IFM_PAD_BOTTOM"}, |
| 556 | {0x810, "IFM_DEPTH_M1"}, |
| 557 | {0x814, "IFM_PRECISION"}, |
| 558 | {0x81C, "IFM_UPSCALE"}, |
| 559 | {0x824, "IFM_ZERO_POINT"}, |
| 560 | {0x828, "IFM_WIDTH0_M1"}, |
| 561 | {0x82C, "IFM_HEIGHT0_M1"}, |
| 562 | {0x830, "IFM_HEIGHT1_M1"}, |
| 563 | {0x834, "IFM_IB_END"}, |
| 564 | {0x83C, "IFM_REGION"}, |
| 565 | {0x844, "OFM_WIDTH_M1"}, |
| 566 | {0x848, "OFM_HEIGHT_M1"}, |
| 567 | {0x84C, "OFM_DEPTH_M1"}, |
| 568 | {0x850, "OFM_PRECISION"}, |
| 569 | {0x854, "OFM_BLK_WIDTH_M1"}, |
| 570 | {0x858, "OFM_BLK_HEIGHT_M1"}, |
| 571 | {0x85C, "OFM_BLK_DEPTH_M1"}, |
| 572 | {0x860, "OFM_ZERO_POINT"}, |
| 573 | {0x868, "OFM_WIDTH0_M1"}, |
| 574 | {0x86C, "OFM_HEIGHT0_M1"}, |
| 575 | {0x870, "OFM_HEIGHT1_M1"}, |
| 576 | {0x87C, "OFM_REGION"}, |
| 577 | {0x880, "KERNEL_WIDTH_M1"}, |
| 578 | {0x884, "KERNEL_HEIGHT_M1"}, |
| 579 | {0x888, "KERNEL_STRIDE"}, |
| 580 | {0x88C, "PARALLEL_MODE"}, |
| 581 | {0x890, "ACC_FORMAT"}, |
| 582 | {0x894, "ACTIVATION"}, |
| 583 | {0x898, "ACTIVATION_MIN"}, |
| 584 | {0x89C, "ACTIVATION_MAX"}, |
| 585 | {0x8A0, "WEIGHT_REGION"}, |
| 586 | {0x8A4, "SCALE_REGION"}, |
| 587 | {0x8B4, "AB_START"}, |
| 588 | {0x8BC, "BLOCKDEP"}, |
| 589 | {0x8C0, "DMA0_SRC_REGION"}, |
| 590 | {0x8C4, "DMA0_DST_REGION"}, |
| 591 | {0x8C8, "DMA0_SIZE0"}, |
| 592 | {0x8CC, "DMA0_SIZE1"}, |
| 593 | {0x900, "IFM2_BROADCAST"}, |
| 594 | {0x904, "IFM2_SCALAR"}, |
| 595 | {0x924, "IFM2_ZERO_POINT"}, |
| 596 | {0x928, "IFM2_WIDTH0_M1"}, |
| 597 | {0x92C, "IFM2_HEIGHT0_M1"}, |
| 598 | {0x930, "IFM2_HEIGHT1_M1"}, |
| 599 | {0x934, "IFM2_IB_START"}, |
| 600 | {0x93C, "IFM2_REGION"}, |
| 601 | {0xA00, "IFM_BASE0"}, |
| 602 | {0xA04, "IFM_BASE0_HI"}, |
| 603 | {0xA08, "IFM_BASE1"}, |
| 604 | {0xA0C, "IFM_BASE1_HI"}, |
| 605 | {0xA10, "IFM_BASE2"}, |
| 606 | {0xA14, "IFM_BASE2_HI"}, |
| 607 | {0xA18, "IFM_BASE3"}, |
| 608 | {0xA1C, "IFM_BASE3_HI"}, |
| 609 | {0xA20, "IFM_STRIDE_X"}, |
| 610 | {0xA24, "IFM_STRIDE_X_HI"}, |
| 611 | {0xA28, "IFM_STRIDE_Y"}, |
| 612 | {0xA2C, "IFM_STRIDE_Y_HI"}, |
| 613 | {0xA30, "IFM_STRIDE_C"}, |
| 614 | {0xA34, "IFM_STRIDE_C_HI"}, |
| 615 | {0xA40, "OFM_BASE0"}, |
| 616 | {0xA44, "OFM_BASE0_HI"}, |
| 617 | {0xA48, "OFM_BASE1"}, |
| 618 | {0xA4C, "OFM_BASE1_HI"}, |
| 619 | {0xA50, "OFM_BASE2"}, |
| 620 | {0xA54, "OFM_BASE2_HI"}, |
| 621 | {0xA58, "OFM_BASE3"}, |
| 622 | {0xA5C, "OFM_BASE3_HI"}, |
| 623 | {0xA60, "OFM_STRIDE_X"}, |
| 624 | {0xA64, "OFM_STRIDE_X_HI"}, |
| 625 | {0xA68, "OFM_STRIDE_Y"}, |
| 626 | {0xA6C, "OFM_STRIDE_Y_HI"}, |
| 627 | {0xA70, "OFM_STRIDE_C"}, |
| 628 | {0xA74, "OFM_STRIDE_C_HI"}, |
| 629 | {0xA80, "WEIGHT_BASE"}, |
| 630 | {0xA84, "WEIGHT_BASE_HI"}, |
| 631 | {0xA88, "WEIGHT_LENGTH"}, |
| 632 | {0xA8C, "WEIGHT_LENGTH_HI"}, |
| 633 | {0xA90, "SCALE_BASE"}, |
| 634 | {0xA94, "SCALE_BASE_HI"}, |
| 635 | {0xA98, "SCALE_LENGTH"}, |
| 636 | {0xAA0, "OFM_SCALE"}, |
| 637 | {0xAA4, "OFM_SCALE_SHIFT"}, |
| 638 | {0xAA8, "OPA_SCALE "}, |
| 639 | {0xAB0, "OPB_SCALE"}, |
| 640 | {0xAC0, "DMA0_SRC"}, |
| 641 | {0xAC4, "DMA0_SRC_HI"}, |
| 642 | {0xAC8, "DMA0_DST"}, |
| 643 | {0xACC, "DMA0_DST_HI"}, |
| 644 | {0xAD0, "DMA0_LEN"}, |
| 645 | {0xAD4, "DMA0_LEN_HI"}, |
| 646 | {0xAD8, "DMA0_SKIP0"}, |
| 647 | {0xADC, "DMA0_SKIP0_HI"}, |
| 648 | {0xAE0, "DMA0_SKIP1"}, |
| 649 | {0xAE4, "DMA0_SKIP1_HI"}, |
| 650 | {0xB00, "IFM2_BASE0"}, |
| 651 | {0xB04, "IFM2_BASE0_HI"}, |
| 652 | {0xB08, "IFM2_BASE1"}, |
| 653 | {0xB0C, "IFM2_BASE1_HI"}, |
| 654 | {0xB10, "IFM2_BASE2"}, |
| 655 | {0xB14, "IFM2_BASE2_HI"}, |
| 656 | {0xB18, "IFM2_BASE3"}, |
| 657 | {0xB1C, "IFM2_BASE3_HI"}, |
| 658 | {0xB20, "IFM2_STRIDE_X"}, |
| 659 | {0xB24, "IFM2_STRIDE_X_HI"}, |
| 660 | {0xB28, "IFM2_STRIDE_Y"}, |
| 661 | {0xB2C, "IFM2_STRIDE_Y_HI"}, |
| 662 | {0xB30, "IFM2_STRIDE_C"}, |
| 663 | {0xB34, "IFM2_STRIDE_C_HI"}, |
| 664 | {0xB40, "WEIGHT1_BASE"}, |
| 665 | {0xB44, "WEIGHT1_BASE_HI"}, |
| 666 | {0xB48, "WEIGHT1_LENGTH"}, |
| 667 | {0xB4C, "WEIGHT1_LENGTH_HI"}, |
| 668 | {0xB50, "SCALE1_BASE"}, |
| 669 | {0xB54, "SCALE1_BASE_HI"}, |
| 670 | {0xB58, "SCALE1_LENGTH"}, |
| 671 | }; |
| 672 | |
| 673 | static const char *lookup_name(const name_lookup_t *lookup_table, int lookup_table_count, int find) |
| 674 | { |
| 675 | int n; |
| 676 | for (n = 0; n < lookup_table_count; n++) |
| 677 | { |
| 678 | if (lookup_table[n].number == find) |
| 679 | { |
| 680 | return lookup_table[n].name; |
| 681 | } |
| 682 | } |
| 683 | // Not found |
| 684 | return 0; |
| 685 | } |
| 686 | |
| 687 | static void dump_npu_register(int npu_reg, int npu_reg_end) |
| 688 | { |
| 689 | unsigned int reg_val; |
| 690 | const char *reg_name; |
| 691 | int npu_reg_name_tbl_count = sizeof(npu_reg_name_tbl) / sizeof(npu_reg_name_tbl[0]); |
| 692 | |
| 693 | LOG_INFO("dump_register %X - %X\n", npu_reg, npu_reg_end); |
| 694 | for (; npu_reg <= npu_reg_end; npu_reg += sizeof(int)) |
| 695 | { |
| 696 | reg_val = read_reg(npu_reg); |
| 697 | reg_name = lookup_name(npu_reg_name_tbl, npu_reg_name_tbl_count, npu_reg); |
| 698 | LOG_INFO("[0x%.4X] 0x%.8X\t%s\n", npu_reg, reg_val, (reg_name) ? reg_name : ""); |
| 699 | } |
| 700 | } |
| 701 | |
| 702 | static const name_lookup_t cmd0_name_tbl[] = { |
| 703 | {0x000, "NPU_OP_STOP"}, |
| 704 | {0x001, "NPU_OP_IRQ"}, |
| 705 | {0x002, "NPU_OP_CONV"}, |
| 706 | {0x003, "NPU_OP_DEPTHWISE"}, |
| 707 | {0x004, "NPU_OP_VECTOR_PROD"}, |
| 708 | {0x005, "NPU_OP_POOL"}, |
| 709 | {0x006, "NPU_OP_ELEMENTWISE"}, |
| 710 | {0x010, "NPU_OP_DMA_START"}, |
| 711 | {0x011, "NPU_OP_DMA_WAIT"}, |
| 712 | {0x012, "NPU_OP_KERNEL_WAIT"}, |
| 713 | {0x100, "NPU_SET_IFM_PAD_TOP"}, |
| 714 | {0x101, "NPU_SET_IFM_PAD_LEFT"}, |
| 715 | {0x102, "NPU_SET_IFM_PAD_RIGHT"}, |
| 716 | {0x103, "NPU_SET_IFM_PAD_BOTTOM"}, |
| 717 | {0x104, "NPU_SET_IFM_DEPTH_M1"}, |
| 718 | {0x105, "NPU_SET_IFM_PRECISION"}, |
| 719 | {0x107, "NPU_SET_IFM_UPSCALE"}, |
| 720 | {0x109, "NPU_SET_IFM_ZERO_POINT"}, |
| 721 | {0x10A, "NPU_SET_IFM_WIDTH0_M1"}, |
| 722 | {0x10B, "NPU_SET_IFM_HEIGHT0_M1"}, |
| 723 | {0x10C, "NPU_SET_IFM_HEIGHT1_M1"}, |
| 724 | {0x10D, "NPU_SET_IFM_IB_END"}, |
| 725 | {0x10F, "NPU_SET_IFM_REGION"}, |
| 726 | {0x110, "NPU_SET_OFM_BATCH_SIZE_M1"}, |
| 727 | {0x111, "NPU_SET_OFM_WIDTH_M1"}, |
| 728 | {0x112, "NPU_SET_OFM_HEIGHT_M1"}, |
| 729 | {0x113, "NPU_SET_OFM_DEPTH_M1"}, |
| 730 | {0x114, "NPU_SET_OFM_PRECISION"}, |
| 731 | {0x115, "NPU_SET_OFM_BLK_WIDTH_M1"}, |
| 732 | {0x116, "NPU_SET_OFM_BLK_HEIGHT_M1"}, |
| 733 | {0x117, "NPU_SET_OFM_BLK_DEPTH_M1"}, |
| 734 | {0x118, "NPU_SET_OFM_ZERO_POINT"}, |
| 735 | {0x11A, "NPU_SET_OFM_WIDTH0_M1"}, |
| 736 | {0x11B, "NPU_SET_OFM_HEIGHT0_M1"}, |
| 737 | {0x11C, "NPU_SET_OFM_HEIGHT1_M1"}, |
| 738 | {0x11F, "NPU_SET_OFM_REGION"}, |
| 739 | {0x120, "NPU_SET_KERNEL_WIDTH_M1"}, |
| 740 | {0x121, "NPU_SET_KERNEL_HEIGHT_M1"}, |
| 741 | {0x122, "NPU_SET_KERNEL_STRIDE"}, |
| 742 | {0x124, "NPU_SET_ACC_FORMAT"}, |
| 743 | {0x125, "NPU_SET_ACTIVATION"}, |
| 744 | {0x126, "NPU_SET_ACTIVATION_MIN"}, |
| 745 | {0x127, "NPU_SET_ACTIVATION_MAX"}, |
| 746 | {0x128, "NPU_SET_WEIGHT_REGION"}, |
| 747 | {0x129, "NPU_SET_SCALE_REGION"}, |
| 748 | {0x12D, "NPU_SET_AB_START"}, |
| 749 | {0x12F, "NPU_SET_BLOCKDEP"}, |
| 750 | {0x130, "NPU_SET_DMA0_SRC_REGION"}, |
| 751 | {0x131, "NPU_SET_DMA0_DST_REGION"}, |
| 752 | {0x180, "NPU_SET_IFM2_BROADCAST"}, |
| 753 | {0x181, "NPU_SET_IFM2_SCALAR"}, |
| 754 | {0x185, "NPU_SET_IFM2_PRECISION"}, |
| 755 | {0x189, "NPU_SET_IFM2_ZERO_POINT"}, |
| 756 | {0x18A, "NPU_SET_IFM2_WIDTH0_M1"}, |
| 757 | {0x18B, "NPU_SET_IFM2_HEIGHT0_M1"}, |
| 758 | {0x18C, "NPU_SET_IFM2_HEIGHT1_M1"}, |
| 759 | {0x18D, "NPU_SET_IFM2_IB_START"}, |
| 760 | {0x18F, "NPU_SET_IFM2_REGION"}, |
| 761 | }; |
| 762 | |
| 763 | static const name_lookup_t cmd1_name_tbl[] = { |
| 764 | {0x000, "NPU_SET_IFM_BASE0"}, {0x001, "NPU_SET_IFM_BASE1"}, {0x002, "NPU_SET_IFM_BASE2"}, |
| 765 | {0x003, "NPU_SET_IFM_BASE3"}, {0x004, "NPU_SET_IFM_STRIDE_X"}, {0x005, "NPU_SET_IFM_STRIDE_Y"}, |
| 766 | {0x006, "NPU_SET_IFM_STRIDE_C"}, {0x007, "NPU_SET_IFM_STRIDE_N"}, {0x010, "NPU_SET_OFM_BASE0"}, |
| 767 | {0x011, "NPU_SET_OFM_BASE1"}, {0x012, "NPU_SET_OFM_BASE2"}, {0x013, "NPU_SET_OFM_BASE3"}, |
| 768 | {0x014, "NPU_SET_OFM_STRIDE_X"}, {0x015, "NPU_SET_OFM_STRIDE_Y"}, {0x016, "NPU_SET_OFM_STRIDE_C"}, |
| 769 | {0x017, "NPU_SET_OFM_STRIDE_N"}, {0x020, "NPU_SET_WEIGHT_BASE"}, {0x021, "NPU_SET_WEIGHT_LENGTH"}, |
| 770 | {0x022, "NPU_SET_SCALE_BASE"}, {0x023, "NPU_SET_SCALE_LENGTH"}, {0x024, "NPU_SET_OFM_SCALE"}, |
| 771 | {0x025, "NPU_SET_OPA_SCALE"}, {0x026, "NPU_SET_OPB_SCALE"}, {0x030, "NPU_SET_DMA0_SRC"}, |
| 772 | {0x031, "NPU_SET_DMA0_DST"}, {0x032, "NPU_SET_DMA0_LEN"}, {0x080, "NPU_SET_IFM2_BASE0"}, |
| 773 | {0x081, "NPU_SET_IFM2_BASE1"}, {0x082, "NPU_SET_IFM2_BASE2"}, {0x083, "NPU_SET_IFM2_BASE3"}, |
| 774 | {0x084, "NPU_SET_IFM2_STRIDE_X"}, {0x085, "NPU_SET_IFM2_STRIDE_Y"}, {0x086, "NPU_SET_IFM2_STRIDE_C"}, |
| 775 | }; |
| 776 | |
| 777 | static void dump_command_stream(const uint32_t *cmd_stream, const int cms_length, int qread) |
| 778 | { |
| 779 | int n; |
| 780 | int offset; |
| 781 | uint32_t cmd_val; |
| 782 | const uint8_t *cmd_ptr; |
| 783 | const char *cmd_name; |
| 784 | int cmd0_name_tbl_count = sizeof(cmd0_name_tbl) / sizeof(cmd0_name_tbl[0]); |
| 785 | int cmd1_name_tbl_count = sizeof(cmd1_name_tbl) / sizeof(cmd1_name_tbl[0]); |
| 786 | |
| 787 | LOG_INFO("dump_command_stream cmd_stream = 0x%8p cms_length = %d\n", cmd_stream, cms_length); |
| 788 | for (n = 0; n < cms_length; n++) |
| 789 | { |
| 790 | // Offset |
| 791 | offset = n * sizeof(int); |
| 792 | LOG_INFO("[%.4d] ", offset); |
| 793 | // Command |
| 794 | cmd_ptr = (const uint8_t *)&cmd_stream[n]; |
| 795 | LOG_INFO("0x%.2X 0x%.2X 0x%.2X 0x%.2X ", cmd_ptr[0], cmd_ptr[1], cmd_ptr[2], cmd_ptr[3]); |
| 796 | // Command name and payload |
| 797 | if (cmd_stream[n] & 0x4000) |
| 798 | { |
| 799 | cmd_name = lookup_name(cmd1_name_tbl, cmd1_name_tbl_count, cmd_stream[n] & 0x3FF); |
| 800 | n++; |
| 801 | cmd_val = cmd_stream[n]; |
| 802 | cmd_ptr = (const uint8_t *)&cmd_stream[n]; |
| 803 | LOG_INFO("0x%.2X 0x%.2X 0x%.2X 0x%.2X ", cmd_ptr[0], cmd_ptr[1], cmd_ptr[2], cmd_ptr[3]); |
| 804 | } |
| 805 | else |
| 806 | { |
| 807 | cmd_val = cmd_stream[n] >> 16; |
| 808 | cmd_name = lookup_name(cmd0_name_tbl, cmd0_name_tbl_count, cmd_stream[n] & 0x3FF); |
| 809 | } |
| 810 | if (cmd_name) |
| 811 | { |
| 812 | LOG_INFO("\t%s 0x%.8X", cmd_name, cmd_val); |
| 813 | } |
| 814 | if (offset == qread) |
| 815 | { |
| 816 | LOG_INFO(" <<== QREAD\n"); |
| 817 | } |
| 818 | else |
| 819 | { |
| 820 | LOG_INFO("\n"); |
| 821 | } |
| 822 | } |
| 823 | } |