Kristofer Jonsson | 537c71c | 2020-05-05 14:17:22 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2019-2020 Arm Limited. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: Apache-2.0 |
| 5 | * |
| 6 | * Licensed under the Apache License, Version 2.0 (the License); you may |
| 7 | * not use this file except in compliance with the License. |
| 8 | * You may obtain a copy of the License at |
| 9 | * |
| 10 | * www.apache.org/licenses/LICENSE-2.0 |
| 11 | * |
| 12 | * Unless required by applicable law or agreed to in writing, software |
| 13 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT |
| 14 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 15 | * See the License for the specific language governing permissions and |
| 16 | * limitations under the License. |
| 17 | */ |
| 18 | |
| 19 | /***************************************************************************** |
| 20 | * Includes |
| 21 | *****************************************************************************/ |
| 22 | |
| 23 | #include "ethosu55_interface.h" |
| 24 | #include "ethosu_common.h" |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 25 | #include "ethosu_driver.h" |
| 26 | #include "pmu_ethosu.h" |
| 27 | |
Kristofer Jonsson | 537c71c | 2020-05-05 14:17:22 +0200 | [diff] [blame] | 28 | #include <assert.h> |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 29 | #include <stddef.h> |
Kristofer Jonsson | 537c71c | 2020-05-05 14:17:22 +0200 | [diff] [blame] | 30 | #include <stdint.h> |
| 31 | |
| 32 | /***************************************************************************** |
| 33 | * Defines |
| 34 | *****************************************************************************/ |
| 35 | |
| 36 | #define COMMA , |
| 37 | #define SEMICOLON ; |
| 38 | |
Kristofer Jonsson | 537c71c | 2020-05-05 14:17:22 +0200 | [diff] [blame] | 39 | #define EVTYPE(A, name) \ |
| 40 | case PMU_EVENT_TYPE_##name: \ |
| 41 | return ETHOSU_PMU_##name |
| 42 | |
| 43 | #define EVID(A, name) (PMU_EVENT_TYPE_##name) |
| 44 | |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 45 | #define ETHOSU_PMCCNTR_CFG_START_STOP_EVENT_MASK (0x3FF) |
| 46 | |
| 47 | #define NPU_REG_PMEVCNTR(x) (NPU_REG_PMEVCNTR0 + ((x) * sizeof(uint32_t))) |
| 48 | #define NPU_REG_PMEVTYPER(x) (NPU_REG_PMEVTYPER0 + ((x) * sizeof(uint32_t))) |
| 49 | |
Kristofer Jonsson | 537c71c | 2020-05-05 14:17:22 +0200 | [diff] [blame] | 50 | /***************************************************************************** |
| 51 | * Variables |
| 52 | *****************************************************************************/ |
| 53 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 54 | /** |
| 55 | * NOTE: A pointer to ethosu_driver will be added to the PMU functions |
| 56 | * when multi-NPU functionality is implemented later. We shall use a |
| 57 | * shared ethosu_driver instance till then. |
| 58 | * */ |
| 59 | extern struct ethosu_driver ethosu_drv; |
| 60 | |
Kristofer Jonsson | 537c71c | 2020-05-05 14:17:22 +0200 | [diff] [blame] | 61 | static const enum pmu_event_type eventbyid[] = {EXPAND_PMU_EVENT_TYPE(EVID, COMMA)}; |
| 62 | |
| 63 | /***************************************************************************** |
| 64 | * Functions |
| 65 | *****************************************************************************/ |
| 66 | |
| 67 | enum ethosu_pmu_event_type pmu_event_type(uint32_t id) |
| 68 | { |
| 69 | switch (id) |
| 70 | { |
| 71 | EXPAND_PMU_EVENT_TYPE(EVTYPE, SEMICOLON); |
| 72 | } |
| 73 | |
| 74 | return ETHOSU_PMU_SENTINEL; |
| 75 | } |
| 76 | |
| 77 | uint32_t pmu_event_value(enum ethosu_pmu_event_type event) |
| 78 | { |
| 79 | if (!(event < ETHOSU_PMU_SENTINEL) || (event < 0)) |
| 80 | { |
| 81 | return (uint32_t)(-1); |
| 82 | } |
| 83 | |
| 84 | return eventbyid[event]; |
| 85 | } |
| 86 | |
| 87 | void ethosu_pmu_driver_init(void) |
| 88 | { |
| 89 | #ifdef PMU_AUTOINIT |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 90 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMCR, INIT_PMCR); |
| 91 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMCNTENSET, INIT_PMCNTENSET); |
| 92 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMCNTENCLR, INIT_PMCNTENCLR); |
| 93 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMOVSSET, INIT_PMOVSSET); |
| 94 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMOVSCLR, INIT_PMOVSCLR); |
| 95 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMINTSET, INIT_PMINTSET); |
| 96 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMINTCLR, INIT_PMINTCLR); |
| 97 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMCCNTR_LO, INIT_PMCCNTR); |
| 98 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMCCNTR_HI, INIT_PMCCNTR); |
| 99 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMCCNTR_CFG, INIT_PMCCNTR_CFG); |
Kristofer Jonsson | 537c71c | 2020-05-05 14:17:22 +0200 | [diff] [blame] | 100 | |
| 101 | for (int i = 0; i < ETHOSU_PMU_NCOUNTERS; i++) |
| 102 | { |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 103 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMEVCNTR(i), 0); |
| 104 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMEVTYPER(i), 0); |
Kristofer Jonsson | 537c71c | 2020-05-05 14:17:22 +0200 | [diff] [blame] | 105 | } |
| 106 | #endif |
| 107 | } |
| 108 | |
| 109 | void ethosu_pmu_driver_exit(void) {} |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 110 | |
| 111 | void ETHOSU_PMU_Enable(void) |
| 112 | { |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 113 | LOG_DEBUG("%s:\n", __FUNCTION__); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 114 | struct pmcr_r pmcr; |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 115 | pmcr.word = ethosu_drv.dev.pmcr; |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 116 | pmcr.cnt_en = 1; |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 117 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMCR, pmcr.word); |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 118 | ethosu_drv.dev.pmcr = ethosu_read_reg(ðosu_drv.dev, NPU_REG_PMCR); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 119 | } |
| 120 | |
| 121 | void ETHOSU_PMU_Disable(void) |
| 122 | { |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 123 | LOG_DEBUG("%s:\n", __FUNCTION__); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 124 | struct pmcr_r pmcr; |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 125 | pmcr.word = ethosu_drv.dev.pmcr; |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 126 | pmcr.cnt_en = 0; |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 127 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMCR, pmcr.word); |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 128 | ethosu_drv.dev.pmcr = ethosu_read_reg(ðosu_drv.dev, NPU_REG_PMCR); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 129 | } |
| 130 | |
| 131 | void ETHOSU_PMU_Set_EVTYPER(uint32_t num, enum ethosu_pmu_event_type type) |
| 132 | { |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 133 | ASSERT(num < ETHOSU_PMU_NCOUNTERS); |
| 134 | uint32_t val = pmu_event_value(type); |
| 135 | LOG_DEBUG("%s: num=%u, type=%d, val=%u\n", __FUNCTION__, num, type, val); |
| 136 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMEVTYPER(num), val); |
| 137 | ethosu_drv.dev.pmu_evtypr[num] = ethosu_read_reg(ðosu_drv.dev, NPU_REG_PMEVTYPER(num)); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 138 | } |
| 139 | |
| 140 | enum ethosu_pmu_event_type ETHOSU_PMU_Get_EVTYPER(uint32_t num) |
| 141 | { |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 142 | ASSERT(num < ETHOSU_PMU_NCOUNTERS); |
| 143 | uint32_t val = ethosu_read_reg(ðosu_drv.dev, NPU_REG_PMEVTYPER(num)); |
| 144 | enum ethosu_pmu_event_type type = pmu_event_type(val); |
| 145 | LOG_DEBUG("%s: num=%u, type=%d, val=%u\n", __FUNCTION__, num, type, val); |
| 146 | return type; |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 147 | } |
| 148 | |
| 149 | void ETHOSU_PMU_CYCCNT_Reset(void) |
| 150 | { |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 151 | LOG_DEBUG("%s:\n", __FUNCTION__); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 152 | struct pmcr_r pmcr; |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 153 | pmcr.word = ethosu_drv.dev.pmcr; |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 154 | pmcr.cycle_cnt_rst = 1; |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 155 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMCR, pmcr.word); |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 156 | ethosu_drv.dev.pmcr = ethosu_read_reg(ðosu_drv.dev, NPU_REG_PMCR); |
| 157 | ethosu_drv.dev.pmccntr_cfg = 0; |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 158 | } |
| 159 | |
| 160 | void ETHOSU_PMU_EVCNTR_ALL_Reset(void) |
| 161 | { |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 162 | LOG_DEBUG("%s:\n", __FUNCTION__); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 163 | struct pmcr_r pmcr; |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 164 | pmcr.word = ethosu_drv.dev.pmcr; |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 165 | pmcr.event_cnt_rst = 1; |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 166 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMCR, pmcr.word); |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 167 | ethosu_drv.dev.pmcr = ethosu_read_reg(ðosu_drv.dev, NPU_REG_PMCR); |
| 168 | |
| 169 | for (uint32_t i = 0; i < ETHOSU_PMU_NCOUNTERS; i++) |
| 170 | { |
| 171 | ethosu_drv.dev.pmu_evcntr[i] = 0; |
| 172 | } |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 173 | } |
| 174 | |
| 175 | void ETHOSU_PMU_CNTR_Enable(uint32_t mask) |
| 176 | { |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 177 | LOG_DEBUG("%s: mask=0x%08x\n", __FUNCTION__, mask); |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 178 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMCNTENSET, mask); |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 179 | ethosu_drv.dev.pmcnten = ethosu_read_reg(ðosu_drv.dev, NPU_REG_PMCNTENSET); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 180 | } |
| 181 | |
| 182 | void ETHOSU_PMU_CNTR_Disable(uint32_t mask) |
| 183 | { |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 184 | LOG_DEBUG("%s: mask=0x%08x\n", __FUNCTION__, mask); |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 185 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMCNTENCLR, mask); |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 186 | ethosu_drv.dev.pmcnten = ethosu_read_reg(ðosu_drv.dev, NPU_REG_PMCNTENSET); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 187 | } |
| 188 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 189 | uint32_t ETHOSU_PMU_CNTR_Status(void) |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 190 | { |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 191 | uint32_t val = ethosu_read_reg(ðosu_drv.dev, NPU_REG_PMCNTENSET); |
| 192 | LOG_DEBUG("%s: mask=0x%08x\n", __FUNCTION__, val); |
| 193 | return val; |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 194 | } |
| 195 | |
| 196 | uint64_t ETHOSU_PMU_Get_CCNTR(void) |
| 197 | { |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 198 | uint64_t val = (((uint64_t)ethosu_read_reg(ðosu_drv.dev, NPU_REG_PMCCNTR_HI)) << 32) | |
| 199 | ethosu_read_reg(ðosu_drv.dev, NPU_REG_PMCCNTR_LO); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 200 | |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 201 | LOG_DEBUG("%s: val=%llu, pmccntr=%llu\n", __FUNCTION__, val, ethosu_drv.dev.pmccntr); |
| 202 | |
| 203 | // Return the cached value in case the NPU was powered off |
| 204 | if (ethosu_drv.dev.pmccntr > val) |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 205 | { |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 206 | return ethosu_drv.dev.pmccntr; |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 207 | } |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 208 | |
| 209 | return val; |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 210 | } |
| 211 | |
| 212 | void ETHOSU_PMU_Set_CCNTR(uint64_t val) |
| 213 | { |
| 214 | uint32_t mask = ETHOSU_PMU_CNTR_Status(); |
| 215 | |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 216 | LOG_DEBUG("%s: val=%llu\n", __FUNCTION__, val); |
| 217 | |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 218 | if (mask & ETHOSU_PMU_CCNT_Msk) |
| 219 | { |
| 220 | ETHOSU_PMU_CNTR_Disable(ETHOSU_PMU_CCNT_Msk); |
| 221 | } |
| 222 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 223 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMCCNTR_LO, (val & MASK_0_31_BITS)); |
| 224 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMCCNTR_HI, (val & MASK_32_47_BITS) >> 32); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 225 | |
| 226 | if (mask & ETHOSU_PMU_CCNT_Msk) |
| 227 | { |
| 228 | ETHOSU_PMU_CNTR_Enable(ETHOSU_PMU_CCNT_Msk); |
| 229 | } |
| 230 | } |
| 231 | |
| 232 | uint32_t ETHOSU_PMU_Get_EVCNTR(uint32_t num) |
| 233 | { |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 234 | ASSERT(num < ETHOSU_PMU_NCOUNTERS); |
| 235 | uint32_t val = ethosu_read_reg(ðosu_drv.dev, NPU_REG_PMEVCNTR(num)); |
| 236 | LOG_DEBUG("%s: num=%u, val=%u, pmu_evcntr=%u\n", __FUNCTION__, num, val, ethosu_drv.dev.pmu_evcntr[num]); |
| 237 | |
| 238 | // Return the cached value in case the NPU was powered off |
| 239 | if (ethosu_drv.dev.pmu_evcntr[num] > val) |
| 240 | { |
| 241 | return ethosu_drv.dev.pmu_evcntr[num]; |
| 242 | } |
| 243 | |
| 244 | return val; |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 245 | } |
| 246 | |
| 247 | void ETHOSU_PMU_Set_EVCNTR(uint32_t num, uint32_t val) |
| 248 | { |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 249 | ASSERT(num < ETHOSU_PMU_NCOUNTERS); |
| 250 | LOG_DEBUG("%s: num=%u, val=%u\n", __FUNCTION__, num, val); |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 251 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMEVCNTR(num), val); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 252 | } |
| 253 | |
| 254 | uint32_t ETHOSU_PMU_Get_CNTR_OVS(void) |
| 255 | { |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 256 | LOG_DEBUG("%s:\n", __FUNCTION__); |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 257 | return ethosu_read_reg(ðosu_drv.dev, NPU_REG_PMOVSSET); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 258 | } |
| 259 | |
| 260 | // TODO: check if this function name match with the description & |
| 261 | // implementation. |
| 262 | void ETHOSU_PMU_Set_CNTR_OVS(uint32_t mask) |
| 263 | { |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 264 | LOG_DEBUG("%s:\n", __FUNCTION__); |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 265 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMOVSCLR, mask); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 266 | } |
| 267 | |
| 268 | void ETHOSU_PMU_Set_CNTR_IRQ_Enable(uint32_t mask) |
| 269 | { |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 270 | LOG_DEBUG("%s: mask=0x%08x\n", __FUNCTION__, mask); |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 271 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMINTSET, mask); |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 272 | ethosu_drv.dev.pmint = ethosu_read_reg(ðosu_drv.dev, NPU_REG_PMINTSET); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 273 | } |
| 274 | |
| 275 | void ETHOSU_PMU_Set_CNTR_IRQ_Disable(uint32_t mask) |
| 276 | { |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 277 | LOG_DEBUG("%s: mask=0x%08x\n", __FUNCTION__, mask); |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 278 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMINTCLR, mask); |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 279 | ethosu_drv.dev.pmint = ethosu_read_reg(ðosu_drv.dev, NPU_REG_PMINTSET); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 280 | } |
| 281 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 282 | uint32_t ETHOSU_PMU_Get_IRQ_Enable(void) |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 283 | { |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 284 | uint32_t mask = ethosu_read_reg(ðosu_drv.dev, NPU_REG_PMINTSET); |
| 285 | LOG_DEBUG("%s: mask=0x%08x\n", __FUNCTION__, mask); |
| 286 | return mask; |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 287 | } |
| 288 | |
| 289 | void ETHOSU_PMU_CNTR_Increment(uint32_t mask) |
| 290 | { |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 291 | LOG_DEBUG("%s:\n", __FUNCTION__); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 292 | uint32_t cntrs_active = ETHOSU_PMU_CNTR_Status(); |
| 293 | |
| 294 | if (mask & ETHOSU_PMU_CCNT_Msk) |
| 295 | { |
| 296 | if (mask & ETHOSU_PMU_CCNT_Msk) |
| 297 | { |
| 298 | ETHOSU_PMU_CNTR_Disable(ETHOSU_PMU_CCNT_Msk); |
| 299 | uint64_t val = ETHOSU_PMU_Get_CCNTR() + 1; |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 300 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMCCNTR_LO, (val & MASK_0_31_BITS)); |
| 301 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMCCNTR_HI, (val & MASK_32_47_BITS) >> 32); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 302 | if (cntrs_active & ETHOSU_PMU_CCNT_Msk) |
| 303 | { |
| 304 | ETHOSU_PMU_CNTR_Enable(ETHOSU_PMU_CCNT_Msk); |
| 305 | } |
| 306 | } |
| 307 | } |
| 308 | for (int i = 0; i < ETHOSU_PMU_NCOUNTERS; i++) |
| 309 | { |
| 310 | uint32_t cntr = (0x0001 << i); |
| 311 | |
| 312 | if (mask & cntr) |
| 313 | { |
| 314 | ETHOSU_PMU_CNTR_Disable(cntr); |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 315 | uint32_t val = ethosu_read_reg(ðosu_drv.dev, NPU_REG_PMEVCNTR(i)); |
| 316 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMEVCNTR(i), val + 1); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 317 | if (cntrs_active & cntr) |
| 318 | { |
| 319 | ETHOSU_PMU_CNTR_Enable(cntr); |
| 320 | } |
| 321 | } |
| 322 | } |
| 323 | } |
| 324 | |
| 325 | void ETHOSU_PMU_PMCCNTR_CFG_Set_Start_Event(uint32_t start_event) |
| 326 | { |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 327 | LOG_DEBUG("%s: start_event=%u\n", __FUNCTION__, start_event); |
| 328 | struct pmccntr_cfg_r *cfg = (struct pmccntr_cfg_r *)ðosu_drv.dev.pmccntr_cfg; |
| 329 | cfg->CYCLE_CNT_CFG_START = start_event & ETHOSU_PMCCNTR_CFG_START_STOP_EVENT_MASK; |
| 330 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMCCNTR_CFG, cfg->word); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 331 | } |
| 332 | |
| 333 | void ETHOSU_PMU_PMCCNTR_CFG_Set_Stop_Event(uint32_t stop_event) |
| 334 | { |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 335 | LOG_DEBUG("%s: stop_event=%u\n", __FUNCTION__, stop_event); |
| 336 | struct pmccntr_cfg_r *cfg = (struct pmccntr_cfg_r *)ðosu_drv.dev.pmccntr_cfg; |
| 337 | cfg->CYCLE_CNT_CFG_STOP = stop_event & ETHOSU_PMCCNTR_CFG_START_STOP_EVENT_MASK; |
| 338 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMCCNTR_CFG, cfg->word); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 339 | } |