Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2019-2020 Arm Limited. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: Apache-2.0 |
| 5 | * |
| 6 | * Licensed under the Apache License, Version 2.0 (the License); you may |
| 7 | * not use this file except in compliance with the License. |
| 8 | * You may obtain a copy of the License at |
| 9 | * |
| 10 | * www.apache.org/licenses/LICENSE-2.0 |
| 11 | * |
| 12 | * Unless required by applicable law or agreed to in writing, software |
| 13 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT |
| 14 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 15 | * See the License for the specific language governing permissions and |
| 16 | * limitations under the License. |
| 17 | */ |
| 18 | |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 19 | #ifndef PMU_ETHOSU_H |
| 20 | #define PMU_ETHOSU_H |
| 21 | |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 22 | /***************************************************************************** |
| 23 | * Includes |
| 24 | *****************************************************************************/ |
| 25 | |
Kristofer Jonsson | 537c71c | 2020-05-05 14:17:22 +0200 | [diff] [blame] | 26 | #include <stdint.h> |
| 27 | |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 28 | #include "ethosu_driver.h" |
| 29 | |
Kristofer Jonsson | 537c71c | 2020-05-05 14:17:22 +0200 | [diff] [blame] | 30 | #ifdef __cplusplus |
| 31 | extern "C" { |
| 32 | #endif |
| 33 | |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 34 | /***************************************************************************** |
| 35 | * Defines |
| 36 | *****************************************************************************/ |
| 37 | |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 38 | #define ETHOSU_PMU_NCOUNTERS 4 |
| 39 | |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 40 | #define ETHOSU_PMU_CNT1_Msk (1UL << 0) |
| 41 | #define ETHOSU_PMU_CNT2_Msk (1UL << 1) |
| 42 | #define ETHOSU_PMU_CNT3_Msk (1UL << 2) |
| 43 | #define ETHOSU_PMU_CNT4_Msk (1UL << 3) |
| 44 | #define ETHOSU_PMU_CCNT_Msk (1UL << 31) |
| 45 | |
| 46 | /***************************************************************************** |
| 47 | * Types |
| 48 | *****************************************************************************/ |
| 49 | |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 50 | /** \brief HW Supported ETHOSU PMU Events |
| 51 | * |
| 52 | * Note: These values are symbolic. Actual HW-values may change. I.e. always use API |
| 53 | * to set/get actual event-type value. |
| 54 | * */ |
| 55 | enum ethosu_pmu_event_type |
| 56 | { |
Diqing Zhong | 25e2c81 | 2020-04-27 13:47:25 +0200 | [diff] [blame] | 57 | ETHOSU_PMU_NO_EVENT = 0, |
| 58 | ETHOSU_PMU_CYCLE, |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 59 | ETHOSU_PMU_NPU_IDLE, |
Douglas Troha | f6a85da | 2020-05-11 11:45:28 +0200 | [diff] [blame] | 60 | ETHOSU_PMU_CC_STALLED_ON_BLOCKDEP, |
| 61 | ETHOSU_PMU_CC_STALLED_ON_SHRAM_RECONFIG, |
Douglas Troha | 2407e96 | 2020-06-15 14:31:45 +0200 | [diff] [blame] | 62 | ETHOSU_PMU_NPU_ACTIVE, |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 63 | ETHOSU_PMU_MAC_ACTIVE, |
| 64 | ETHOSU_PMU_MAC_ACTIVE_8BIT, |
| 65 | ETHOSU_PMU_MAC_ACTIVE_16BIT, |
| 66 | ETHOSU_PMU_MAC_DPU_ACTIVE, |
| 67 | ETHOSU_PMU_MAC_STALLED_BY_WD_ACC, |
| 68 | ETHOSU_PMU_MAC_STALLED_BY_WD, |
| 69 | ETHOSU_PMU_MAC_STALLED_BY_ACC, |
| 70 | ETHOSU_PMU_MAC_STALLED_BY_IB, |
Diqing Zhong | 25e2c81 | 2020-04-27 13:47:25 +0200 | [diff] [blame] | 71 | ETHOSU_PMU_MAC_ACTIVE_32BIT, |
Douglas Troha | f6a85da | 2020-05-11 11:45:28 +0200 | [diff] [blame] | 72 | ETHOSU_PMU_MAC_STALLED_BY_INT_W, |
| 73 | ETHOSU_PMU_MAC_STALLED_BY_INT_ACC, |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 74 | ETHOSU_PMU_AO_ACTIVE, |
| 75 | ETHOSU_PMU_AO_ACTIVE_8BIT, |
| 76 | ETHOSU_PMU_AO_ACTIVE_16BIT, |
| 77 | ETHOSU_PMU_AO_STALLED_BY_OFMP_OB, |
| 78 | ETHOSU_PMU_AO_STALLED_BY_OFMP, |
| 79 | ETHOSU_PMU_AO_STALLED_BY_OB, |
| 80 | ETHOSU_PMU_AO_STALLED_BY_ACC_IB, |
| 81 | ETHOSU_PMU_AO_STALLED_BY_ACC, |
| 82 | ETHOSU_PMU_AO_STALLED_BY_IB, |
| 83 | ETHOSU_PMU_WD_ACTIVE, |
| 84 | ETHOSU_PMU_WD_STALLED, |
| 85 | ETHOSU_PMU_WD_STALLED_BY_WS, |
| 86 | ETHOSU_PMU_WD_STALLED_BY_WD_BUF, |
| 87 | ETHOSU_PMU_WD_PARSE_ACTIVE, |
| 88 | ETHOSU_PMU_WD_PARSE_STALLED, |
| 89 | ETHOSU_PMU_WD_PARSE_STALLED_IN, |
| 90 | ETHOSU_PMU_WD_PARSE_STALLED_OUT, |
Diqing Zhong | 25e2c81 | 2020-04-27 13:47:25 +0200 | [diff] [blame] | 91 | ETHOSU_PMU_WD_TRANS_WS, |
| 92 | ETHOSU_PMU_WD_TRANS_WB, |
| 93 | ETHOSU_PMU_WD_TRANS_DW0, |
| 94 | ETHOSU_PMU_WD_TRANS_DW1, |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 95 | ETHOSU_PMU_AXI0_RD_TRANS_ACCEPTED, |
| 96 | ETHOSU_PMU_AXI0_RD_TRANS_COMPLETED, |
| 97 | ETHOSU_PMU_AXI0_RD_DATA_BEAT_RECEIVED, |
| 98 | ETHOSU_PMU_AXI0_RD_TRAN_REQ_STALLED, |
| 99 | ETHOSU_PMU_AXI0_WR_TRANS_ACCEPTED, |
| 100 | ETHOSU_PMU_AXI0_WR_TRANS_COMPLETED_M, |
| 101 | ETHOSU_PMU_AXI0_WR_TRANS_COMPLETED_S, |
| 102 | ETHOSU_PMU_AXI0_WR_DATA_BEAT_WRITTEN, |
| 103 | ETHOSU_PMU_AXI0_WR_TRAN_REQ_STALLED, |
| 104 | ETHOSU_PMU_AXI0_WR_DATA_BEAT_STALLED, |
| 105 | ETHOSU_PMU_AXI0_ENABLED_CYCLES, |
| 106 | ETHOSU_PMU_AXI0_RD_STALL_LIMIT, |
| 107 | ETHOSU_PMU_AXI0_WR_STALL_LIMIT, |
| 108 | ETHOSU_PMU_AXI1_RD_TRANS_ACCEPTED, |
| 109 | ETHOSU_PMU_AXI1_RD_TRANS_COMPLETED, |
| 110 | ETHOSU_PMU_AXI1_RD_DATA_BEAT_RECEIVED, |
| 111 | ETHOSU_PMU_AXI1_RD_TRAN_REQ_STALLED, |
| 112 | ETHOSU_PMU_AXI1_WR_TRANS_ACCEPTED, |
| 113 | ETHOSU_PMU_AXI1_WR_TRANS_COMPLETED_M, |
| 114 | ETHOSU_PMU_AXI1_WR_TRANS_COMPLETED_S, |
| 115 | ETHOSU_PMU_AXI1_WR_DATA_BEAT_WRITTEN, |
| 116 | ETHOSU_PMU_AXI1_WR_TRAN_REQ_STALLED, |
| 117 | ETHOSU_PMU_AXI1_WR_DATA_BEAT_STALLED, |
| 118 | ETHOSU_PMU_AXI1_ENABLED_CYCLES, |
| 119 | ETHOSU_PMU_AXI1_RD_STALL_LIMIT, |
| 120 | ETHOSU_PMU_AXI1_WR_STALL_LIMIT, |
| 121 | ETHOSU_PMU_AXI_LATENCY_ANY, |
| 122 | ETHOSU_PMU_AXI_LATENCY_32, |
| 123 | ETHOSU_PMU_AXI_LATENCY_64, |
| 124 | ETHOSU_PMU_AXI_LATENCY_128, |
| 125 | ETHOSU_PMU_AXI_LATENCY_256, |
| 126 | ETHOSU_PMU_AXI_LATENCY_512, |
| 127 | ETHOSU_PMU_AXI_LATENCY_1024, |
Stefan Nannesson | e2e7024 | 2020-08-19 16:01:29 +0200 | [diff] [blame] | 128 | ETHOSU_PMU_ECC_DMA, |
| 129 | ETHOSU_PMU_ECC_SB0, |
| 130 | ETHOSU_PMU_ECC_SB1, |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 131 | |
| 132 | ETHOSU_PMU_SENTINEL // End-marker (not event) |
| 133 | }; |
| 134 | |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 135 | /***************************************************************************** |
| 136 | * Functions |
| 137 | *****************************************************************************/ |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 138 | |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 139 | /** |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 140 | * \brief Enable the PMU |
| 141 | */ |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 142 | void ETHOSU_PMU_Enable_v2(struct ethosu_driver *drv); |
| 143 | |
| 144 | #define ETHOSU_PMU_Enable(void) ETHOSU_PMU_Enable_v2(ðosu_drv) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 145 | |
| 146 | /** |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 147 | * \brief Disable the PMU |
| 148 | */ |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 149 | void ETHOSU_PMU_Disable_v2(struct ethosu_driver *drv); |
| 150 | |
| 151 | #define ETHOSU_PMU_Disable(void) ETHOSU_PMU_Disable_v2(ðosu_drv) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 152 | |
| 153 | /** |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 154 | * \brief Set event to count for PMU eventer counter |
| 155 | * \param [in] num Event counter (0-ETHOSU_PMU_NCOUNTERS) to configure |
| 156 | * \param [in] type Event to count |
| 157 | */ |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 158 | void ETHOSU_PMU_Set_EVTYPER_v2(struct ethosu_driver *drv, uint32_t num, enum ethosu_pmu_event_type type); |
| 159 | |
| 160 | #define ETHOSU_PMU_Set_EVTYPER(num, type) ETHOSU_PMU_Set_EVTYPER_v2(ðosu_drv, num, type) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 161 | |
| 162 | /** |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 163 | * \brief Get event to count for PMU eventer counter |
| 164 | * \param [in] num Event counter (0-ETHOSU_PMU_NCOUNTERS) to configure |
| 165 | * \return type Event to count |
| 166 | */ |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 167 | enum ethosu_pmu_event_type ETHOSU_PMU_Get_EVTYPER_v2(struct ethosu_driver *drv, uint32_t num); |
| 168 | |
| 169 | #define ETHOSU_PMU_Get_EVTYPER(num) ETHOSU_PMU_Get_EVTYPER_v2(ðosu_drv, num) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 170 | |
| 171 | /** |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 172 | * \brief Reset cycle counter |
| 173 | */ |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 174 | void ETHOSU_PMU_CYCCNT_Reset_v2(struct ethosu_driver *drv); |
| 175 | |
| 176 | #define ETHOSU_PMU_CYCCNT_Reset(void) ETHOSU_PMU_CYCCNT_Reset_v2(ðosu_drv) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 177 | |
| 178 | /** |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 179 | * \brief Reset all event counters |
| 180 | */ |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 181 | void ETHOSU_PMU_EVCNTR_ALL_Reset_v2(struct ethosu_driver *drv); |
| 182 | |
| 183 | #define ETHOSU_PMU_EVCNTR_ALL_Reset(void) ETHOSU_PMU_EVCNTR_ALL_Reset_v2(ðosu_drv) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 184 | |
| 185 | /** |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 186 | * \brief Enable counters |
| 187 | * \param [in] mask Counters to enable |
| 188 | * \note Enables one or more of the following: |
| 189 | * - event counters (bit 0-ETHOSU_PMU_NCOUNTERS) |
| 190 | * - cycle counter (bit 31) |
| 191 | */ |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 192 | void ETHOSU_PMU_CNTR_Enable_v2(struct ethosu_driver *drv, uint32_t mask); |
| 193 | |
| 194 | #define ETHOSU_PMU_CNTR_Enable(mask) ETHOSU_PMU_CNTR_Enable_v2(ðosu_drv, mask) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 195 | |
| 196 | /** |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 197 | * \brief Disable counters |
| 198 | * \param [in] mask Counters to disable |
| 199 | * \note Disables one or more of the following: |
| 200 | * - event counters (bit 0-ETHOSU_PMU_NCOUNTERS) |
| 201 | * - cycle counter (bit 31) |
| 202 | */ |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 203 | void ETHOSU_PMU_CNTR_Disable_v2(struct ethosu_driver *drv, uint32_t mask); |
| 204 | |
| 205 | #define ETHOSU_PMU_CNTR_Disable(mask) ETHOSU_PMU_CNTR_Disable_v2(ðosu_drv, mask) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 206 | |
| 207 | /** |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 208 | * \brief Determine counters activation |
| 209 | * |
| 210 | * \return Event count |
| 211 | * \param [in] mask Counters to enable |
| 212 | * \return a bitmask where bit-set means: |
| 213 | * - event counters activated (bit 0-ETHOSU_PMU_NCOUNTERS) |
| 214 | * - cycle counter activate (bit 31) |
| 215 | * \note ETHOSU specific. Usage breaks CMSIS complience |
| 216 | */ |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 217 | uint32_t ETHOSU_PMU_CNTR_Status_v2(struct ethosu_driver *drv); |
| 218 | |
| 219 | #define ETHOSU_PMU_CNTR_Status(void) ETHOSU_PMU_CNTR_Status_v2(ðosu_drv) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 220 | |
| 221 | /** |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 222 | * \brief Read cycle counter (64 bit) |
| 223 | * \return Cycle count |
| 224 | * \note Two HW 32-bit registers that can increment independently in-between reads. |
| 225 | * To work-around raciness yet still avoid turning |
| 226 | * off the event both are read as one value twice. If the latter read |
| 227 | * is not greater than the former, it means overflow of LSW without |
| 228 | * incrementing MSW has occurred, in which case the former value is used. |
| 229 | */ |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 230 | uint64_t ETHOSU_PMU_Get_CCNTR_v2(struct ethosu_driver *drv); |
| 231 | |
| 232 | #define ETHOSU_PMU_Get_CCNTR(void) ETHOSU_PMU_Get_CCNTR_v2(ðosu_drv) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 233 | |
| 234 | /** |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 235 | * \brief Set cycle counter (64 bit) |
| 236 | * \param [in] val Conter value |
| 237 | * \note Two HW 32-bit registers that can increment independently in-between reads. |
| 238 | * To work-around raciness, counter is temporary disabled if enabled. |
| 239 | * \note ETHOSU specific. Usage breaks CMSIS complience |
| 240 | */ |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 241 | void ETHOSU_PMU_Set_CCNTR_v2(struct ethosu_driver *drv, uint64_t val); |
| 242 | |
| 243 | #define ETHOSU_PMU_Set_CCNTR(val) ETHOSU_PMU_Set_CCNTR_v2(ðosu_drv, val) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 244 | |
| 245 | /** |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 246 | * \brief Read event counter |
| 247 | * \param [in] num Event counter (0-ETHOSU_PMU_NCOUNTERS) |
| 248 | * \return Event count |
| 249 | */ |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 250 | uint32_t ETHOSU_PMU_Get_EVCNTR_v2(struct ethosu_driver *drv, uint32_t num); |
| 251 | |
| 252 | #define ETHOSU_PMU_Get_EVCNTR(num) ETHOSU_PMU_Get_EVCNTR_v2(ðosu_drv, num) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 253 | |
| 254 | /** |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 255 | * \brief Set event counter value |
| 256 | * \param [in] num Event counter (0-ETHOSU_PMU_NCOUNTERS) |
| 257 | * \param [in] val Conter value |
| 258 | * \note ETHOSU specific. Usage breaks CMSIS complience |
| 259 | */ |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 260 | void ETHOSU_PMU_Set_EVCNTR_v2(struct ethosu_driver *drv, uint32_t num, uint32_t val); |
| 261 | |
| 262 | #define ETHOSU_PMU_Set_EVCNTR(num, val) ETHOSU_PMU_Set_EVCNTR_v2(ðosu_drv, num, val) |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 263 | |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 264 | /** |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 265 | * \brief Read counter overflow status |
| 266 | * \return Counter overflow status bits for the following: |
| 267 | * - event counters (bit 0-ETHOSU_PMU_NCOUNTERS)) |
| 268 | * - cycle counter (bit 31) |
| 269 | */ |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 270 | uint32_t ETHOSU_PMU_Get_CNTR_OVS_v2(struct ethosu_driver *drv); |
| 271 | |
| 272 | #define ETHOSU_PMU_Get_CNTR_OVS(void) ETHOSU_PMU_Get_CNTR_OVS_v2(ðosu_drv) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 273 | |
| 274 | /** |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 275 | * \brief Clear counter overflow status |
| 276 | * \param [in] mask Counter overflow status bits to clear |
| 277 | * \note Clears overflow status bits for one or more of the following: |
| 278 | * - event counters (bit 0-ETHOSU_PMU_NCOUNTERS) |
| 279 | * - cycle counter (bit 31) |
| 280 | */ |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 281 | void ETHOSU_PMU_Set_CNTR_OVS_v2(struct ethosu_driver *drv, uint32_t mask); |
| 282 | |
| 283 | #define ETHOSU_PMU_Set_CNTR_OVS(mask) ETHOSU_PMU_Set_CNTR_OVS_v2(ðosu_drv, mask) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 284 | |
| 285 | /** |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 286 | * \brief Enable counter overflow interrupt request |
| 287 | * \param [in] mask Counter overflow interrupt request bits to set |
| 288 | * \note Sets overflow interrupt request bits for one or more of the following: |
| 289 | * - event counters (bit 0-ETHOSU_PMU_NCOUNTERS) |
| 290 | * - cycle counter (bit 31) |
| 291 | */ |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 292 | void ETHOSU_PMU_Set_CNTR_IRQ_Enable_v2(struct ethosu_driver *drv, uint32_t mask); |
| 293 | |
| 294 | #define ETHOSU_PMU_Set_CNTR_IRQ_Enable(mask) ETHOSU_PMU_Set_CNTR_IRQ_Enable_v2(ðosu_drv, mask) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 295 | |
| 296 | /** |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 297 | * \brief Disable counter overflow interrupt request |
| 298 | * \param [in] mask Counter overflow interrupt request bits to clear |
| 299 | * \note Clears overflow interrupt request bits for one or more of the following: |
| 300 | * - event counters (bit 0-ETHOSU_PMU_NCOUNTERS) |
| 301 | * - cycle counter (bit 31) |
| 302 | */ |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 303 | void ETHOSU_PMU_Set_CNTR_IRQ_Disable_v2(struct ethosu_driver *drv, uint32_t mask); |
| 304 | |
| 305 | #define ETHOSU_PMU_Set_CNTR_IRQ_Disable(mask) ETHOSU_PMU_Set_CNTR_IRQ_Disable_v2(ðosu_drv, mask) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 306 | |
| 307 | /** |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 308 | * \brief Get counters overflow interrupt request stiinings |
| 309 | * \return mask Counter overflow interrupt request bits |
| 310 | * \note Sets overflow interrupt request bits for one or more of the following: |
| 311 | * - event counters (bit 0-ETHOSU_PMU_NCOUNTERS) |
| 312 | * - cycle counter (bit 31) |
| 313 | * \note ETHOSU specific. Usage breaks CMSIS compliance |
| 314 | */ |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 315 | uint32_t ETHOSU_PMU_Get_IRQ_Enable_v2(struct ethosu_driver *drv); |
| 316 | |
| 317 | #define ETHOSU_PMU_Get_IRQ_Enable(void) ETHOSU_PMU_Get_IRQ_Enable_v2(ðosu_drv) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 318 | |
| 319 | /** |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 320 | * \brief Software increment event counter |
| 321 | * \param [in] mask Counters to increment |
| 322 | * - event counters (bit 0-ETHOSU_PMU_NCOUNTERS) |
| 323 | * - cycle counter (bit 31) |
| 324 | * \note Software increment bits for one or more event counters. |
| 325 | */ |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 326 | void ETHOSU_PMU_CNTR_Increment_v2(struct ethosu_driver *drv, uint32_t mask); |
| 327 | |
| 328 | #define ETHOSU_PMU_CNTR_Increment(mask) ETHOSU_PMU_CNTR_Increment_v2(ðosu_drv, mask) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 329 | |
Bhavik Patel | 4e8dbf5 | 2020-06-15 10:09:28 +0200 | [diff] [blame] | 330 | /** |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 331 | * \brief Set start event number for the cycle counter |
| 332 | * \param [in] start_event Event number |
| 333 | * - Start event (bits [9:0]) |
| 334 | * \note Sets the event number that starts the cycle counter. |
| 335 | * - Event number in the range 0..1023 |
| 336 | */ |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 337 | void ETHOSU_PMU_PMCCNTR_CFG_Set_Start_Event_v2(struct ethosu_driver *drv, uint32_t start_event); |
| 338 | |
| 339 | #define ETHOSU_PMU_PMCCNTR_CFG_Set_Start_Event(start_event) \ |
| 340 | ETHOSU_PMU_PMCCNTR_CFG_Set_Start_Event_v2(ðosu_drv, start_event) |
Bhavik Patel | 4e8dbf5 | 2020-06-15 10:09:28 +0200 | [diff] [blame] | 341 | |
| 342 | /** |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 343 | * \brief Set stop event number for the cycle counter |
| 344 | * \param [in] stop_event Event number |
| 345 | * - Stop event (bits [25:16]) |
| 346 | * \note Sets the event number that stops the cycle counter. |
| 347 | * - Event number in the range 0..1023 |
| 348 | */ |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 349 | void ETHOSU_PMU_PMCCNTR_CFG_Set_Stop_Event_v2(struct ethosu_driver *drv, uint32_t stop_event); |
| 350 | |
| 351 | #define ETHOSU_PMU_PMCCNTR_CFG_Set_Stop_Event(stop_event) \ |
| 352 | ETHOSU_PMU_PMCCNTR_CFG_Set_Stop_Event_v2(ðosu_drv, stop_event) |
Bhavik Patel | 4e8dbf5 | 2020-06-15 10:09:28 +0200 | [diff] [blame] | 353 | |
Kristofer Jonsson | 537c71c | 2020-05-05 14:17:22 +0200 | [diff] [blame] | 354 | #ifdef __cplusplus |
| 355 | } |
| 356 | #endif |
| 357 | |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 358 | #endif /* PMU_ETHOSU_H */ |