Kristofer Jonsson | 537c71c | 2020-05-05 14:17:22 +0200 | [diff] [blame] | 1 | /* |
Per Åstrand | 0fd65ce | 2021-03-11 10:25:18 +0100 | [diff] [blame] | 2 | * Copyright (c) 2019-2021 Arm Limited. All rights reserved. |
Kristofer Jonsson | 537c71c | 2020-05-05 14:17:22 +0200 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: Apache-2.0 |
| 5 | * |
| 6 | * Licensed under the Apache License, Version 2.0 (the License); you may |
| 7 | * not use this file except in compliance with the License. |
| 8 | * You may obtain a copy of the License at |
| 9 | * |
| 10 | * www.apache.org/licenses/LICENSE-2.0 |
| 11 | * |
| 12 | * Unless required by applicable law or agreed to in writing, software |
| 13 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT |
| 14 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 15 | * See the License for the specific language governing permissions and |
| 16 | * limitations under the License. |
| 17 | */ |
| 18 | |
| 19 | /***************************************************************************** |
| 20 | * Includes |
| 21 | *****************************************************************************/ |
| 22 | |
| 23 | #include "ethosu55_interface.h" |
| 24 | #include "ethosu_common.h" |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 25 | #include "ethosu_driver.h" |
Anton Moberg | 6eab40b | 2021-07-07 11:43:51 +0200 | [diff] [blame] | 26 | #include "ethosu_log.h" |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 27 | #include "pmu_ethosu.h" |
| 28 | |
Kristofer Jonsson | 537c71c | 2020-05-05 14:17:22 +0200 | [diff] [blame] | 29 | #include <assert.h> |
Per Åstrand | e07b1f9 | 2020-09-28 08:31:46 +0200 | [diff] [blame] | 30 | #include <inttypes.h> |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 31 | #include <stddef.h> |
Kristofer Jonsson | 537c71c | 2020-05-05 14:17:22 +0200 | [diff] [blame] | 32 | |
| 33 | /***************************************************************************** |
| 34 | * Defines |
| 35 | *****************************************************************************/ |
| 36 | |
| 37 | #define COMMA , |
| 38 | #define SEMICOLON ; |
| 39 | |
Kristofer Jonsson | 537c71c | 2020-05-05 14:17:22 +0200 | [diff] [blame] | 40 | #define EVTYPE(A, name) \ |
| 41 | case PMU_EVENT_TYPE_##name: \ |
| 42 | return ETHOSU_PMU_##name |
| 43 | |
| 44 | #define EVID(A, name) (PMU_EVENT_TYPE_##name) |
| 45 | |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 46 | #define NPU_REG_PMEVCNTR(x) (NPU_REG_PMEVCNTR0 + ((x) * sizeof(uint32_t))) |
| 47 | #define NPU_REG_PMEVTYPER(x) (NPU_REG_PMEVTYPER0 + ((x) * sizeof(uint32_t))) |
| 48 | |
Kristofer Jonsson | 537c71c | 2020-05-05 14:17:22 +0200 | [diff] [blame] | 49 | /***************************************************************************** |
| 50 | * Variables |
| 51 | *****************************************************************************/ |
| 52 | |
Kristofer Jonsson | 537c71c | 2020-05-05 14:17:22 +0200 | [diff] [blame] | 53 | static const enum pmu_event_type eventbyid[] = {EXPAND_PMU_EVENT_TYPE(EVID, COMMA)}; |
| 54 | |
| 55 | /***************************************************************************** |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 56 | * Static functions |
Kristofer Jonsson | 537c71c | 2020-05-05 14:17:22 +0200 | [diff] [blame] | 57 | *****************************************************************************/ |
| 58 | |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 59 | static enum ethosu_pmu_event_type pmu_event_type(uint32_t id) |
Kristofer Jonsson | 537c71c | 2020-05-05 14:17:22 +0200 | [diff] [blame] | 60 | { |
| 61 | switch (id) |
| 62 | { |
| 63 | EXPAND_PMU_EVENT_TYPE(EVTYPE, SEMICOLON); |
Per Åstrand | e07b1f9 | 2020-09-28 08:31:46 +0200 | [diff] [blame] | 64 | default: |
| 65 | LOG_ERR("Unknown PMU event id: 0x%" PRIx32 "\n", id); |
Kristofer Jonsson | 537c71c | 2020-05-05 14:17:22 +0200 | [diff] [blame] | 66 | } |
| 67 | |
| 68 | return ETHOSU_PMU_SENTINEL; |
| 69 | } |
| 70 | |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 71 | static uint32_t pmu_event_value(enum ethosu_pmu_event_type event) |
Kristofer Jonsson | 537c71c | 2020-05-05 14:17:22 +0200 | [diff] [blame] | 72 | { |
Per Åstrand | 51c18ba | 2020-09-28 11:25:36 +0200 | [diff] [blame] | 73 | int a = event; |
| 74 | if ((a < ETHOSU_PMU_SENTINEL) && (a >= ETHOSU_PMU_NO_EVENT)) |
| 75 | { |
| 76 | return eventbyid[event]; |
| 77 | } |
| 78 | else |
Kristofer Jonsson | 537c71c | 2020-05-05 14:17:22 +0200 | [diff] [blame] | 79 | { |
| 80 | return (uint32_t)(-1); |
| 81 | } |
Kristofer Jonsson | 537c71c | 2020-05-05 14:17:22 +0200 | [diff] [blame] | 82 | } |
| 83 | |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 84 | /***************************************************************************** |
| 85 | * Functions |
| 86 | *****************************************************************************/ |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 87 | |
Anton Moberg | c6fd88e | 2021-05-03 17:00:33 +0200 | [diff] [blame] | 88 | void ETHOSU_PMU_Enable(struct ethosu_driver *drv) |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 89 | { |
Anton Moberg | 6eab40b | 2021-07-07 11:43:51 +0200 | [diff] [blame] | 90 | LOG_DEBUG("Enable PMU\n"); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 91 | struct pmcr_r pmcr; |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 92 | pmcr.word = drv->dev.pmcr; |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 93 | pmcr.cnt_en = 1; |
Anton Moberg | 0a61429 | 2021-03-24 14:08:22 +0100 | [diff] [blame] | 94 | set_clock_and_power_request(drv, ETHOSU_PMU_REQUEST, ETHOSU_CLOCK_Q_DISABLE, ETHOSU_POWER_Q_DISABLE); |
Jonny Svärd | a830f17 | 2021-06-07 16:57:00 +0200 | [diff] [blame] | 95 | ethosu_dev_write_reg_shadow(&drv->dev, NPU_REG_PMCR, pmcr.word, &drv->dev.pmcr); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 96 | } |
| 97 | |
Anton Moberg | c6fd88e | 2021-05-03 17:00:33 +0200 | [diff] [blame] | 98 | void ETHOSU_PMU_Disable(struct ethosu_driver *drv) |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 99 | { |
Anton Moberg | 6eab40b | 2021-07-07 11:43:51 +0200 | [diff] [blame] | 100 | LOG_DEBUG("Disable PMU\n"); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 101 | struct pmcr_r pmcr; |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 102 | pmcr.word = drv->dev.pmcr; |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 103 | pmcr.cnt_en = 0; |
Anton Moberg | 0a61429 | 2021-03-24 14:08:22 +0100 | [diff] [blame] | 104 | set_clock_and_power_request(drv, ETHOSU_PMU_REQUEST, ETHOSU_CLOCK_Q_ENABLE, ETHOSU_POWER_Q_ENABLE); |
Jonny Svärd | a830f17 | 2021-06-07 16:57:00 +0200 | [diff] [blame] | 105 | ethosu_dev_write_reg_shadow(&drv->dev, NPU_REG_PMCR, pmcr.word, &drv->dev.pmcr); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 106 | } |
| 107 | |
Anton Moberg | c6fd88e | 2021-05-03 17:00:33 +0200 | [diff] [blame] | 108 | void ETHOSU_PMU_Set_EVTYPER(struct ethosu_driver *drv, uint32_t num, enum ethosu_pmu_event_type type) |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 109 | { |
Kristofer Jonsson | 1c893b5 | 2021-05-26 12:06:14 +0200 | [diff] [blame] | 110 | assert(num < ETHOSU_PMU_NCOUNTERS); |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 111 | uint32_t val = pmu_event_value(type); |
Anton Moberg | 6eab40b | 2021-07-07 11:43:51 +0200 | [diff] [blame] | 112 | LOG_DEBUG("num=%u, type=%d, val=%u\n", num, type, val); |
Jonny Svärd | a830f17 | 2021-06-07 16:57:00 +0200 | [diff] [blame] | 113 | ethosu_dev_write_reg_shadow(&drv->dev, NPU_REG_PMEVTYPER(num), val, &drv->dev.pmu_evtypr[num]); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 114 | } |
| 115 | |
Anton Moberg | c6fd88e | 2021-05-03 17:00:33 +0200 | [diff] [blame] | 116 | enum ethosu_pmu_event_type ETHOSU_PMU_Get_EVTYPER(struct ethosu_driver *drv, uint32_t num) |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 117 | { |
Kristofer Jonsson | 1c893b5 | 2021-05-26 12:06:14 +0200 | [diff] [blame] | 118 | assert(num < ETHOSU_PMU_NCOUNTERS); |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 119 | uint32_t val = drv->dev.pmu_evtypr[num]; |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 120 | enum ethosu_pmu_event_type type = pmu_event_type(val); |
Anton Moberg | 6eab40b | 2021-07-07 11:43:51 +0200 | [diff] [blame] | 121 | LOG_DEBUG("num=%u, type=%d, val=%u\n", num, type, val); |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 122 | return type; |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 123 | } |
| 124 | |
Anton Moberg | c6fd88e | 2021-05-03 17:00:33 +0200 | [diff] [blame] | 125 | void ETHOSU_PMU_CYCCNT_Reset(struct ethosu_driver *drv) |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 126 | { |
Anton Moberg | 6eab40b | 2021-07-07 11:43:51 +0200 | [diff] [blame] | 127 | LOG_DEBUG("Reset PMU\n"); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 128 | struct pmcr_r pmcr; |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 129 | pmcr.word = drv->dev.pmcr; |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 130 | pmcr.cycle_cnt_rst = 1; |
Jonny Svärd | a830f17 | 2021-06-07 16:57:00 +0200 | [diff] [blame] | 131 | ethosu_dev_write_reg_shadow(&drv->dev, NPU_REG_PMCR, pmcr.word, &drv->dev.pmcr); |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 132 | drv->dev.pmccntr[0] = 0; |
| 133 | drv->dev.pmccntr[1] = 0; |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 134 | } |
| 135 | |
Anton Moberg | c6fd88e | 2021-05-03 17:00:33 +0200 | [diff] [blame] | 136 | void ETHOSU_PMU_EVCNTR_ALL_Reset(struct ethosu_driver *drv) |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 137 | { |
Anton Moberg | 6eab40b | 2021-07-07 11:43:51 +0200 | [diff] [blame] | 138 | LOG_DEBUG("Reset all events\n"); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 139 | struct pmcr_r pmcr; |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 140 | pmcr.word = drv->dev.pmcr; |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 141 | pmcr.event_cnt_rst = 1; |
Jonny Svärd | a830f17 | 2021-06-07 16:57:00 +0200 | [diff] [blame] | 142 | ethosu_dev_write_reg_shadow(&drv->dev, NPU_REG_PMCR, pmcr.word, &drv->dev.pmcr); |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 143 | |
| 144 | for (uint32_t i = 0; i < ETHOSU_PMU_NCOUNTERS; i++) |
| 145 | { |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 146 | drv->dev.pmu_evcntr[i] = 0; |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 147 | } |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 148 | } |
| 149 | |
Anton Moberg | c6fd88e | 2021-05-03 17:00:33 +0200 | [diff] [blame] | 150 | void ETHOSU_PMU_CNTR_Enable(struct ethosu_driver *drv, uint32_t mask) |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 151 | { |
Anton Moberg | 6eab40b | 2021-07-07 11:43:51 +0200 | [diff] [blame] | 152 | LOG_DEBUG("mask=0x%08x\n", mask); |
Jonny Svärd | a830f17 | 2021-06-07 16:57:00 +0200 | [diff] [blame] | 153 | ethosu_dev_write_reg_shadow(&drv->dev, NPU_REG_PMCNTENSET, mask, &drv->dev.pmcnten); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 154 | } |
| 155 | |
Anton Moberg | c6fd88e | 2021-05-03 17:00:33 +0200 | [diff] [blame] | 156 | void ETHOSU_PMU_CNTR_Disable(struct ethosu_driver *drv, uint32_t mask) |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 157 | { |
Anton Moberg | 6eab40b | 2021-07-07 11:43:51 +0200 | [diff] [blame] | 158 | LOG_DEBUG("mask=0x%08x\n", mask); |
Jonny Svärd | a830f17 | 2021-06-07 16:57:00 +0200 | [diff] [blame] | 159 | ethosu_dev_write_reg_shadow(&drv->dev, NPU_REG_PMCNTENCLR, mask, &drv->dev.pmcnten); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 160 | } |
| 161 | |
Anton Moberg | c6fd88e | 2021-05-03 17:00:33 +0200 | [diff] [blame] | 162 | uint32_t ETHOSU_PMU_CNTR_Status(struct ethosu_driver *drv) |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 163 | { |
Anton Moberg | 6eab40b | 2021-07-07 11:43:51 +0200 | [diff] [blame] | 164 | LOG_DEBUG("mask=0x%08x\n", drv->dev.pmcnten); |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 165 | return drv->dev.pmcnten; |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 166 | } |
| 167 | |
Anton Moberg | c6fd88e | 2021-05-03 17:00:33 +0200 | [diff] [blame] | 168 | uint64_t ETHOSU_PMU_Get_CCNTR(struct ethosu_driver *drv) |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 169 | { |
Jonny Svärd | a830f17 | 2021-06-07 16:57:00 +0200 | [diff] [blame] | 170 | uint32_t val_lo = ethosu_dev_read_reg(&drv->dev, NPU_REG_PMCCNTR_LO); |
| 171 | uint32_t val_hi = ethosu_dev_read_reg(&drv->dev, NPU_REG_PMCCNTR_HI); |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 172 | uint64_t val = ((uint64_t)val_hi << 32) | val_lo; |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 173 | uint64_t shadow = ((uint64_t)drv->dev.pmccntr[1] << 32) | drv->dev.pmccntr[0]; |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 174 | |
Anton Moberg | 6eab40b | 2021-07-07 11:43:51 +0200 | [diff] [blame] | 175 | LOG_DEBUG("val=%" PRIu64 ", shadow=%" PRIu64 "\n", val, shadow); |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 176 | |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 177 | // Return the shadow variable in case the NPU was powered off and lost the cycle count |
| 178 | if (shadow > val) |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 179 | { |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 180 | return shadow; |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 181 | } |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 182 | |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 183 | // Update the shadow variable |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 184 | drv->dev.pmccntr[0] = val_lo; |
| 185 | drv->dev.pmccntr[1] = val_hi; |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 186 | |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 187 | return val; |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 188 | } |
| 189 | |
Anton Moberg | c6fd88e | 2021-05-03 17:00:33 +0200 | [diff] [blame] | 190 | void ETHOSU_PMU_Set_CCNTR(struct ethosu_driver *drv, uint64_t val) |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 191 | { |
Anton Moberg | c6fd88e | 2021-05-03 17:00:33 +0200 | [diff] [blame] | 192 | uint32_t active = ETHOSU_PMU_CNTR_Status(drv) & ETHOSU_PMU_CCNT_Msk; |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 193 | |
Anton Moberg | 6eab40b | 2021-07-07 11:43:51 +0200 | [diff] [blame] | 194 | LOG_DEBUG("val=%llu\n", val); |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 195 | |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 196 | if (active) |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 197 | { |
Anton Moberg | c6fd88e | 2021-05-03 17:00:33 +0200 | [diff] [blame] | 198 | ETHOSU_PMU_CNTR_Disable(drv, ETHOSU_PMU_CCNT_Msk); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 199 | } |
| 200 | |
Jonny Svärd | a830f17 | 2021-06-07 16:57:00 +0200 | [diff] [blame] | 201 | ethosu_dev_write_reg_shadow(&drv->dev, NPU_REG_PMCCNTR_LO, val & MASK_0_31_BITS, &drv->dev.pmccntr[0]); |
| 202 | ethosu_dev_write_reg_shadow(&drv->dev, NPU_REG_PMCCNTR_HI, (val & MASK_32_47_BITS) >> 32, &drv->dev.pmccntr[1]); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 203 | |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 204 | if (active) |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 205 | { |
Anton Moberg | c6fd88e | 2021-05-03 17:00:33 +0200 | [diff] [blame] | 206 | ETHOSU_PMU_CNTR_Enable(drv, ETHOSU_PMU_CCNT_Msk); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 207 | } |
| 208 | } |
| 209 | |
Anton Moberg | c6fd88e | 2021-05-03 17:00:33 +0200 | [diff] [blame] | 210 | uint32_t ETHOSU_PMU_Get_EVCNTR(struct ethosu_driver *drv, uint32_t num) |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 211 | { |
Kristofer Jonsson | 1c893b5 | 2021-05-26 12:06:14 +0200 | [diff] [blame] | 212 | assert(num < ETHOSU_PMU_NCOUNTERS); |
Jonny Svärd | a830f17 | 2021-06-07 16:57:00 +0200 | [diff] [blame] | 213 | uint32_t val = ethosu_dev_read_reg(&drv->dev, NPU_REG_PMEVCNTR(num)); |
Anton Moberg | 6eab40b | 2021-07-07 11:43:51 +0200 | [diff] [blame] | 214 | LOG_DEBUG("num=%u, val=%u, shadow=%u\n", num, val, drv->dev.pmu_evcntr[num]); |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 215 | |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 216 | // Return the shadow variable in case the NPU was powered off and lost the event count |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 217 | if (drv->dev.pmu_evcntr[num] > val) |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 218 | { |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 219 | return drv->dev.pmu_evcntr[num]; |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 220 | } |
| 221 | |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 222 | // Update the shadow variable |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 223 | drv->dev.pmu_evcntr[num] = val; |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 224 | |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 225 | return val; |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 226 | } |
| 227 | |
Anton Moberg | c6fd88e | 2021-05-03 17:00:33 +0200 | [diff] [blame] | 228 | void ETHOSU_PMU_Set_EVCNTR(struct ethosu_driver *drv, uint32_t num, uint32_t val) |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 229 | { |
Kristofer Jonsson | 1c893b5 | 2021-05-26 12:06:14 +0200 | [diff] [blame] | 230 | assert(num < ETHOSU_PMU_NCOUNTERS); |
Anton Moberg | 6eab40b | 2021-07-07 11:43:51 +0200 | [diff] [blame] | 231 | LOG_DEBUG("num=%u, val=%u\n", num, val); |
Jonny Svärd | a830f17 | 2021-06-07 16:57:00 +0200 | [diff] [blame] | 232 | ethosu_dev_write_reg(&drv->dev, NPU_REG_PMEVCNTR(num), val); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 233 | } |
| 234 | |
Anton Moberg | c6fd88e | 2021-05-03 17:00:33 +0200 | [diff] [blame] | 235 | uint32_t ETHOSU_PMU_Get_CNTR_OVS(struct ethosu_driver *drv) |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 236 | { |
Anton Moberg | 6eab40b | 2021-07-07 11:43:51 +0200 | [diff] [blame] | 237 | LOG_DEBUG(""); |
Jonny Svärd | a830f17 | 2021-06-07 16:57:00 +0200 | [diff] [blame] | 238 | return ethosu_dev_read_reg(&drv->dev, NPU_REG_PMOVSSET); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 239 | } |
| 240 | |
Anton Moberg | c6fd88e | 2021-05-03 17:00:33 +0200 | [diff] [blame] | 241 | void ETHOSU_PMU_Set_CNTR_OVS(struct ethosu_driver *drv, uint32_t mask) |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 242 | { |
Anton Moberg | 6eab40b | 2021-07-07 11:43:51 +0200 | [diff] [blame] | 243 | LOG_DEBUG(""); |
Jonny Svärd | a830f17 | 2021-06-07 16:57:00 +0200 | [diff] [blame] | 244 | ethosu_dev_write_reg(&drv->dev, NPU_REG_PMOVSCLR, mask); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 245 | } |
| 246 | |
Anton Moberg | c6fd88e | 2021-05-03 17:00:33 +0200 | [diff] [blame] | 247 | void ETHOSU_PMU_Set_CNTR_IRQ_Enable(struct ethosu_driver *drv, uint32_t mask) |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 248 | { |
Anton Moberg | 6eab40b | 2021-07-07 11:43:51 +0200 | [diff] [blame] | 249 | LOG_DEBUG("mask=0x%08x\n", mask); |
Jonny Svärd | a830f17 | 2021-06-07 16:57:00 +0200 | [diff] [blame] | 250 | ethosu_dev_write_reg_shadow(&drv->dev, NPU_REG_PMINTSET, mask, &drv->dev.pmint); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 251 | } |
| 252 | |
Anton Moberg | c6fd88e | 2021-05-03 17:00:33 +0200 | [diff] [blame] | 253 | void ETHOSU_PMU_Set_CNTR_IRQ_Disable(struct ethosu_driver *drv, uint32_t mask) |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 254 | { |
Anton Moberg | 6eab40b | 2021-07-07 11:43:51 +0200 | [diff] [blame] | 255 | LOG_DEBUG("mask=0x%08x\n", mask); |
Jonny Svärd | a830f17 | 2021-06-07 16:57:00 +0200 | [diff] [blame] | 256 | ethosu_dev_write_reg_shadow(&drv->dev, NPU_REG_PMINTCLR, mask, &drv->dev.pmint); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 257 | } |
| 258 | |
Anton Moberg | c6fd88e | 2021-05-03 17:00:33 +0200 | [diff] [blame] | 259 | uint32_t ETHOSU_PMU_Get_IRQ_Enable(struct ethosu_driver *drv) |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 260 | { |
Anton Moberg | 6eab40b | 2021-07-07 11:43:51 +0200 | [diff] [blame] | 261 | LOG_DEBUG("mask=0x%08x\n", drv->dev.pmint); |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 262 | return drv->dev.pmint; |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 263 | } |
| 264 | |
Anton Moberg | c6fd88e | 2021-05-03 17:00:33 +0200 | [diff] [blame] | 265 | void ETHOSU_PMU_CNTR_Increment(struct ethosu_driver *drv, uint32_t mask) |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 266 | { |
Anton Moberg | 6eab40b | 2021-07-07 11:43:51 +0200 | [diff] [blame] | 267 | LOG_DEBUG(""); |
Anton Moberg | c6fd88e | 2021-05-03 17:00:33 +0200 | [diff] [blame] | 268 | uint32_t cntrs_active = ETHOSU_PMU_CNTR_Status(drv); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 269 | |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 270 | // Disable counters |
Anton Moberg | c6fd88e | 2021-05-03 17:00:33 +0200 | [diff] [blame] | 271 | ETHOSU_PMU_CNTR_Disable(drv, mask); |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 272 | |
| 273 | // Increment cycle counter |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 274 | if (mask & ETHOSU_PMU_CCNT_Msk) |
| 275 | { |
Anton Moberg | c6fd88e | 2021-05-03 17:00:33 +0200 | [diff] [blame] | 276 | uint64_t val = ETHOSU_PMU_Get_CCNTR(drv) + 1; |
Jonny Svärd | a830f17 | 2021-06-07 16:57:00 +0200 | [diff] [blame] | 277 | ethosu_dev_write_reg_shadow(&drv->dev, NPU_REG_PMCCNTR_LO, val & MASK_0_31_BITS, &drv->dev.pmccntr[0]); |
| 278 | ethosu_dev_write_reg_shadow(&drv->dev, NPU_REG_PMCCNTR_HI, (val & MASK_32_47_BITS) >> 32, &drv->dev.pmccntr[1]); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 279 | } |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 280 | |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 281 | for (int i = 0; i < ETHOSU_PMU_NCOUNTERS; i++) |
| 282 | { |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 283 | if (mask & (1 << i)) |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 284 | { |
Anton Moberg | c6fd88e | 2021-05-03 17:00:33 +0200 | [diff] [blame] | 285 | uint32_t val = ETHOSU_PMU_Get_EVCNTR(drv, i); |
Jonny Svärd | a830f17 | 2021-06-07 16:57:00 +0200 | [diff] [blame] | 286 | ethosu_dev_write_reg_shadow(&drv->dev, NPU_REG_PMEVCNTR(i), val + 1, &drv->dev.pmu_evcntr[i]); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 287 | } |
| 288 | } |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 289 | |
| 290 | // Reenable the active counters |
Anton Moberg | c6fd88e | 2021-05-03 17:00:33 +0200 | [diff] [blame] | 291 | ETHOSU_PMU_CNTR_Enable(drv, cntrs_active); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 292 | } |
| 293 | |
Anton Moberg | c6fd88e | 2021-05-03 17:00:33 +0200 | [diff] [blame] | 294 | void ETHOSU_PMU_PMCCNTR_CFG_Set_Start_Event(struct ethosu_driver *drv, enum ethosu_pmu_event_type start_event) |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 295 | { |
Anton Moberg | 6eab40b | 2021-07-07 11:43:51 +0200 | [diff] [blame] | 296 | LOG_DEBUG("start_event=%u\n", start_event); |
Per Åstrand | 0fd65ce | 2021-03-11 10:25:18 +0100 | [diff] [blame] | 297 | uint32_t val = pmu_event_value(start_event); |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 298 | struct pmccntr_cfg_r cfg; |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 299 | cfg.word = drv->dev.pmccntr_cfg; |
Per Åstrand | 0fd65ce | 2021-03-11 10:25:18 +0100 | [diff] [blame] | 300 | cfg.CYCLE_CNT_CFG_START = val; |
Jonny Svärd | a830f17 | 2021-06-07 16:57:00 +0200 | [diff] [blame] | 301 | ethosu_dev_write_reg_shadow(&drv->dev, NPU_REG_PMCCNTR_CFG, cfg.word, &drv->dev.pmccntr_cfg); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 302 | } |
| 303 | |
Anton Moberg | c6fd88e | 2021-05-03 17:00:33 +0200 | [diff] [blame] | 304 | void ETHOSU_PMU_PMCCNTR_CFG_Set_Stop_Event(struct ethosu_driver *drv, enum ethosu_pmu_event_type stop_event) |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 305 | { |
Anton Moberg | 6eab40b | 2021-07-07 11:43:51 +0200 | [diff] [blame] | 306 | LOG_DEBUG("stop_event=%u\n", stop_event); |
Per Åstrand | 0fd65ce | 2021-03-11 10:25:18 +0100 | [diff] [blame] | 307 | uint32_t val = pmu_event_value(stop_event); |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 308 | struct pmccntr_cfg_r cfg; |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 309 | cfg.word = drv->dev.pmccntr_cfg; |
Per Åstrand | 0fd65ce | 2021-03-11 10:25:18 +0100 | [diff] [blame] | 310 | cfg.CYCLE_CNT_CFG_STOP = val; |
Jonny Svärd | a830f17 | 2021-06-07 16:57:00 +0200 | [diff] [blame] | 311 | ethosu_dev_write_reg_shadow(&drv->dev, NPU_REG_PMCCNTR_CFG, cfg.word, &drv->dev.pmccntr_cfg); |
Anton Moberg | 6eab40b | 2021-07-07 11:43:51 +0200 | [diff] [blame] | 312 | } |