diff --git a/targets/corstone-300/platform.ld b/targets/corstone-300/platform.ld
index a1cdb0e..091a117 100644
--- a/targets/corstone-300/platform.ld
+++ b/targets/corstone-300/platform.ld
@@ -57,6 +57,15 @@
 __HEAP_SIZE  = 0x00008000;
 
 /*--------------------- Embedded RAM Configuration ----------------------------
+  <h> BRAM Configuration
+    <o0> BRAM Base Address    <0x0-0xFFFFFFFF:8>
+    <o1> BRAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
+  </h>
+ -----------------------------------------------------------------------------*/
+__BRAM_BASE = 0x11000000;
+__BRAM_SIZE = 0x00200000;
+
+/*--------------------- Embedded RAM Configuration ----------------------------
   <h> DDR Configuration
     <o0> DDR Base Address    <0x0-0xFFFFFFFF:8>
     <o1> DDR Size (in Bytes) <0x0-0xFFFFFFFF:8>
@@ -74,6 +83,7 @@
   ITCM  (rx)  : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE
   DTCM  (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE
   SRAM  (rwx) : ORIGIN = __SRAM_BASE, LENGTH = __SRAM_SIZE
+  BRAM  (rwx) : ORIGIN = __BRAM_BASE, LENGTH = __BRAM_SIZE
   DDR   (rwx) : ORIGIN = __DDR_BASE, LENGTH = __DDR_SIZE
 }
 
@@ -141,7 +151,7 @@
   /*
    * SG veneers:
    * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address
-   * must be set, either with the command line option �--section-start� or in a linker script,
+   * must be set, either with the command line option '--section-start' or in a linker script,
    * to indicate where to place these veneers in memory.
    */
 /*
@@ -169,6 +179,7 @@
     LONG (__etext)
     LONG (__data_start__)
     LONG (__data_end__ - __data_start__)
+
     /* Add each additional data section here */
     __copy_table_end__ = .;
   } > ITCM
@@ -212,7 +223,6 @@
     KEEP(*(.init_array))
     PROVIDE_HIDDEN (__init_array_end = .);
 
-
     . = ALIGN(4);
     /* finit data */
     PROVIDE_HIDDEN (__fini_array_start = .);
@@ -249,28 +259,34 @@
   } > RAM2
 */
 
-#ifndef ETHOSU_FAST_MEMORY_SIZE
   .sram :
   {
     . = ALIGN(16);
-    *(.bss.tensor_arena)
-    . = ALIGN(16);
-  } > SRAM AT > SRAM
-#else
-  .sram :
-  {
-    . = ALIGN(16);
+#ifdef ETHOSU_FAST_MEMORY_SIZE
     *(.bss.ethosu_scratch);
-    . = ALIGN(16);
-  } > SRAM AT > SRAM
+#else
+    *(.bss.tensor_arena)
+#endif
 
-  .bss.tensor_arena :
+    . = ALIGN(16);
+    *(.sram.data)
+  } > BRAM AT > BRAM
+
+  .ddr :
   {
     . = ALIGN(16);
+#ifdef ETHOSU_FAST_MEMORY_SIZE
     *(.bss.tensor_arena)
-    . = ALIGN(16);
-  } > DDR AT > DDR
 #endif
+    . = ALIGN(16);
+    *(input_data_sec)
+
+    . = ALIGN(16);
+    *(network_model_sec)
+
+    . = ALIGN (16);
+    *(expected_output_data_sec)
+  } > DDR AT > DDR
 
   .bss :
   {
@@ -283,7 +299,6 @@
     __bss_end__ = .;
   } > DTCM AT > DTCM
 
-
   /*
    * Secondary bss section, optional
    *
@@ -303,18 +318,6 @@
   } > RAM2 AT > RAM2
 */
 
-  .ddr :
-  {
-    /* __attribute__((aligned(16))) is not handled by the cmsis startup code.
-     * Force the alignement here as a workaround */
-    . = ALIGN(4);
-    *(input_data_sec)
-    . = ALIGN(16);
-    *(network_model_sec)
-    *(expected_output_data_sec)
-    . = ALIGN (16);
-  } > DDR
-
   .heap (COPY) :
   {
     . = ALIGN(8);
diff --git a/targets/corstone-300/platform.scatter b/targets/corstone-300/platform.scatter
index dc8f57b..fe63d01 100644
--- a/targets/corstone-300/platform.scatter
+++ b/targets/corstone-300/platform.scatter
@@ -18,6 +18,55 @@
  * limitations under the License.
  */
 
+/*
+ * This is a simplified picture of the Corstone-300 memory system.
+ * Please refer to the Corstone SSE-300 Technical Reference Manual for
+ * further information.
+ *
+ * https://developer.arm.com/ip-products/subsystem/corstone/corstone-300
+ *
+ * +---------------+   +---------------+  +------+
+ * | Ethos-U55     |   | Cortex-M55    +--+ ITCM |
+ * |               |   |               |  +------+
+ * |               |   |               |
+ * |               |   |               |  +------+
+ * |  M1      M0   |   |               +--+ DTCM |
+ * +---+-------+---+   +-------+-------+  +------+
+ *     |       |               |
+ *     |   +---+---------------+-----+
+ *     |   | AMBA AXI NIC-400-Lite   |
+ *     |   +---+-----------------+---+
+ *     |       |                 |
+ * +---+-------+------------+ +--+-------+
+ * | AMBA AXI NIC-400       | | SSE-300  |
+ * +---+--------+--------+--+ | SRAM     |
+ *     |        |        |    +----------+
+ * +---+---+ +--+---+ +--+--+
+ * | Flash | | BRAM | | DDR |
+ * +-------+ +------+ +-----+
+ *
+ * +-----------------------+-------------+-------------+----+--------------------------------------+
+ * |  Memory region name   | Base addr   |    Size     |IDAU|  MCC load address + remarks          |
+ * +-----------------------+-------------+-------------+----+--------------------------------------+
+ * | ITCM                  | 0x0000_0000 | 0x0008_0000 | NS | 0x0000_0000; 512 kiB                 |
+ * | ITCM                  | 0x1000_0000 | 0x0008_0000 | S  | Secure alias for NS ITCM             |
+ * | FPGA Data SRAM; BRAM  | 0x0100_0000 | 0x0020_0000 | NS | 0x0100_0000; 2 MiB                   |
+ * | FPGA data SRAM; BRAM  | 0x1100_0000 | 0x0020_0000 | S  | Secure alias for NS BRAM             |
+ * | DTCM                  | 0x2000_0000 | 0x0008_0000 | NS | 512 kiB; 4 banks of 128k each        |
+ * | DTCM                  | 0x3000_0000 | 0x0008_0000 | S  | Secure alias for NS DTCM             |
+ * | SSE-300 internal SRAM | 0x2100_0000 | 0x0040_0000 | NS | 2 banks of 2 MiB each; 3cc latency)  |
+ * | SSE-300 internal SRAM | 0x3100_0000 | 0x0040_0000 | S  | Secure alias for NS internal SRAM    |
+ * | DDR                   | 0x6000_0000 | 0x1000_0000 | NS | 0x0800_0000; 256 MiB bank            |
+ * | DDR                   | 0x7000_0000 | 0x1000_0000 | S  | 0x0C00_0000; 256 MiB bank            |
+ * +-----------------------+-------------+-------------+----+--------------------------------------+
+ *
+ *  Note: Ethos-U55 can access BRAM, internal SRAM and the DDR sections => activation buffers and
+ *        the model should only be placed in those regions.
+ *
+ *  Note: Alias regions means that secure and non-secure addresses are mapped to the same physical
+ *        memory banks.
+ */
+
 #ifndef STACK_SIZE
 #define STACK_SIZE 0x8000
 #endif
@@ -85,8 +134,9 @@
 #if defined(USE_TRUSTZONE) && defined(TRUSTZONE_SECURE)
     ; MPS3 BRAM
     ; Shared between Cortex-M and the NPU
-    BRAM BRAM_START UNINIT (BRAM_SIZE - TZ_NSC_SIZE)
+    BRAM BRAM_START (BRAM_SIZE - TZ_NSC_SIZE)
     {
+        * (.sram.data)
     }
 
     ROM_NSC TZ_NSC_START TZ_NSC_SIZE
@@ -95,8 +145,9 @@
     }
 #else
     ; MPS3 BRAM
-    BRAM BRAM_START UNINIT BRAM_SIZE
+    BRAM BRAM_START BRAM_SIZE
     {
+        * (.sram.data)
     }
 #endif