Build system refactoring
The source tree is configured for a specific target as defined in the
targets directory.
The common target components are defined in targets/common. Targets
for real platform should include this directory to get the default
target libraries setup.
Change-Id: I7fced4bfacec97432cbbd4125bd5b4cdd21122e3
diff --git a/targets/corstone-300/platform.scatter b/targets/corstone-300/platform.scatter
index e3037a7..2ab371f 100644
--- a/targets/corstone-300/platform.scatter
+++ b/targets/corstone-300/platform.scatter
@@ -26,22 +26,90 @@
#define HEAP_SIZE 0x8000
#endif
-APP_IMAGE 0x00000000 0x01000000
+#if defined(TRUSTZONE_BUILD) && !defined(ETHOSU_TEST)
+/*
+ * Include trustzone.h with common addresses and sizes.
+ * The build configuration sets whether TRUSTZONE_SECURE is set or
+ * TRUSTZONE_NONSECURE which sets the memory start addresses and sizes.
+ */
+
+#include "trustzone.h"
+#define USE_TRUSTZONE
+
+#else //TRUSTZONE_BUILD
+
+#define LR_START 0x10000000
+#define LR_SIZE 0x01000000
+
+#define ITCM_START 0x10000000
+#define ITCM_SIZE 0x00080000
+
+#define BRAM_START 0x11000000
+#define BRAM_SIZE 0x00200000
+
+#define DTCM_START 0x30000000
+#define DTCM_SIZE 0x00080000
+
+#define SRAM_START 0x31000000
+#define SRAM_SIZE 0x00200000
+
+#define DDR_START 0x70000000
+#define DDR_SIZE 0x02000000
+
+#define STACK_HEAP 0x30080000
+
+#endif //TRUSTZONE_BUILD
+
+/* ----------------------------------------------------------------------------
+ Stack seal size definition
+ *----------------------------------------------------------------------------*/
+#if defined(USE_TRUSTZONE) && defined(TRUSTZONE_SECURE)
+#define __STACKSEAL_SIZE ( 8 )
+#else
+#define __STACKSEAL_SIZE ( 0 )
+#endif
+
+APP_IMAGE LR_START LR_SIZE
{
; ITCM 512kB
- rom_exec 0x00000000 0x00080000
+ rom_exec ITCM_START ITCM_SIZE
{
*.o (RESET, +First)
*(InRoot$$Sections)
+ ; Make sure reset_handler ends up in root segment, when split across
+ ; ITCM and DTCM
+ startup_ARMCM55.o
.ANY (+RO)
}
+#if defined(USE_TRUSTZONE) && defined(TRUSTZONE_SECURE)
+ ; MPS3 BRAM
; Shared between Cortex-M and the NPU
- DATA_SRAM 0x01000000 UNINIT 0x00200000 {}
+ BRAM BRAM_START UNINIT (BRAM_SIZE - TZ_NSC_SIZE)
+ {
+ }
+
+ ROM_NSC TZ_NSC_START TZ_NSC_SIZE
+ {
+ *(Veneer$$CMSE)
+ }
+#else
+ ; MPS3 BRAM
+ BRAM BRAM_START UNINIT BRAM_SIZE
+ {
+ }
+#endif
+
+ ; DTCM 512kB
+ ; Only accessible from the Cortex-M
+ DTCM DTCM_START (DTCM_SIZE - STACK_SIZE - HEAP_SIZE - __STACKSEAL_SIZE)
+ {
+ .ANY1 (+RW +ZI)
+ }
; SSE-300 SRAM (3 cycles read latency) from M55/U55
; 2x2MB - only first part mapped
- SRAM 0x21000000 UNINIT 0x00200000
+ SRAM SRAM_START UNINIT SRAM_SIZE
{
#ifndef ETHOSU_FAST_MEMORY_SIZE
; Place tensor arena in SRAM if we do not have a fast memory area
@@ -51,25 +119,29 @@
#endif
}
- ; DTCM 512kB
- ; Only accessible from the Cortex-M
- DTCM 0x20000000 (0x00080000 - STACK_SIZE - HEAP_SIZE)
- {
- .ANY (+RW +ZI)
- }
+ ARM_LIB_HEAP (STACK_HEAP - STACK_SIZE - __STACKSEAL_SIZE - HEAP_SIZE) EMPTY ALIGN 8 HEAP_SIZE {}
+ ARM_LIB_STACK (STACK_HEAP - STACK_SIZE - __STACKSEAL_SIZE) EMPTY ALIGN 8 STACK_SIZE {}
- ARM_LIB_HEAP (0x20080000 - STACK_SIZE - HEAP_SIZE) EMPTY ALIGN 8 HEAP_SIZE {}
- ARM_LIB_STACK (0x20080000 - STACK_SIZE) EMPTY ALIGN 8 STACK_SIZE {}
+#if defined(USE_TRUSTZONE) && defined(TRUSTZONE_SECURE)
+ STACKSEAL +0 EMPTY __STACKSEAL_SIZE {
+ ; Reserve empty region for stack seal immediately after stack
+ }
+#endif
}
-LOAD_REGION_1 0x60000000 0x02000000
+LOAD_REGION_1 DDR_START DDR_SIZE
{
; 2GB DDR4 available
- rom_dram 0x60000000 0x02000000
+ rom_dram DDR_START
+#if defined(USE_TRUSTZONE) && defined(TRUSTZONE_NONSECURE)
+ {
+ }
+#else //trustzone secure or non-trustzone
{
* (network_model_sec)
* (input_data_sec)
* (expected_output_data_sec)
+ * (output_data_sec)
}
#ifdef ETHOSU_FAST_MEMORY_SIZE
@@ -79,4 +151,5 @@
* (.bss.NoInit) ; Tensor Arena
}
#endif
+#endif
}