| /* |
| * Copyright (c) 2009-2021 Arm Limited. All rights reserved. |
| * |
| * SPDX-License-Identifier: Apache-2.0 |
| * |
| * Licensed under the Apache License, Version 2.0 (the License); you may |
| * not use this file except in compliance with the License. |
| * You may obtain a copy of the License at |
| * |
| * www.apache.org/licenses/LICENSE-2.0 |
| * |
| * Unless required by applicable law or agreed to in writing, software |
| * distributed under the License is distributed on an AS IS BASIS, WITHOUT |
| * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| * See the License for the specific language governing permissions and |
| * limitations under the License. |
| */ |
| |
| __STACK_SIZE = 0x00008000; |
| __HEAP_SIZE = 0x00008000; |
| |
| MEMORY |
| { |
| ITCM (rx) : ORIGIN = 0x10000000, LENGTH = 0x00080000 |
| SRAM (rw) : ORIGIN = 0x11000000, LENGTH = 0x01000000 |
| DTCM (rw) : ORIGIN = 0x30000000, LENGTH = 0x00080000 |
| DDR (rwx) : ORIGIN = 0x70000000, LENGTH = 0x60000000 |
| } |
| |
| PHDRS |
| { |
| rom_exec PT_LOAD; |
| rom_dram PT_LOAD; |
| null PT_NULL; |
| } |
| |
| /* Linker script to place sections and symbol values. Should be used together |
| * with other linker script that defines memory regions ITCM and RAM. |
| * It references following symbols, which must be defined in code: |
| * Reset_Handler : Entry of reset handler |
| * |
| * It defines following symbols, which code can use without definition: |
| * __exidx_start |
| * __exidx_end |
| * __copy_table_start__ |
| * __copy_table_end__ |
| * __zero_table_start__ |
| * __zero_table_end__ |
| * __etext |
| * __data_start__ |
| * __preinit_array_start |
| * __preinit_array_end |
| * __init_array_start |
| * __init_array_end |
| * __fini_array_start |
| * __fini_array_end |
| * __data_end__ |
| * __bss_start__ |
| * __bss_end__ |
| * __end__ |
| * end |
| * __HeapLimit |
| * __StackLimit |
| * __StackTop |
| * __stack |
| */ |
| |
| ENTRY(Reset_Handler) |
| |
| SECTIONS |
| { |
| .text : |
| { |
| KEEP(*(.vectors)) |
| *(.text*) |
| |
| KEEP(*(.init)) |
| KEEP(*(.fini)) |
| |
| /* .ctors */ |
| *crtbegin.o(.ctors) |
| *crtbegin?.o(.ctors) |
| *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) |
| *(SORT(.ctors.*)) |
| *(.ctors) |
| |
| /* .dtors */ |
| *crtbegin.o(.dtors) |
| *crtbegin?.o(.dtors) |
| *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) |
| *(SORT(.dtors.*)) |
| *(.dtors) |
| |
| *(.rodata*) |
| |
| KEEP(*(.eh_frame*)) |
| } > ITCM :rom_exec |
| |
| /* |
| * SG veneers: |
| * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address |
| * must be set, either with the command line option '--section-start' or in a linker script, |
| * to indicate where to place these veneers in memory. |
| */ |
| /* |
| .gnu.sgstubs : |
| { |
| . = ALIGN(32); |
| } > ITCM :rom_exec |
| */ |
| .ARM.extab : |
| { |
| *(.ARM.extab* .gnu.linkonce.armextab.*) |
| } > ITCM :rom_exec |
| |
| .ARM.exidx : |
| { |
| __exidx_start = .; |
| *(.ARM.exidx* .gnu.linkonce.armexidx.*) |
| __exidx_end = .; |
| } > ITCM :rom_exec |
| |
| .copy.table : |
| { |
| . = ALIGN(4); |
| __copy_table_start__ = .; |
| LONG (__etext) |
| LONG (__data_start__) |
| LONG (__data_end__ - __data_start__) |
| |
| LONG (__eddr_data) |
| LONG (__sram_data_start__) |
| LONG (__sram_data_end__ - __sram_data_start__ ) |
| |
| __copy_table_end__ = .; |
| } > ITCM :rom_exec |
| |
| .zero.table : |
| { |
| . = ALIGN(4); |
| __zero_table_start__ = .; |
| LONG (__bss_start__) |
| LONG (__bss_end__ - __bss_start__) |
| __zero_table_end__ = .; |
| |
| /** |
| * Location counter can end up 2byte aligned with narrow Thumb code but |
| * __etext is assumed by startup code to be the LMA of a section in DTCM |
| * which must be 4byte aligned |
| */ |
| __etext = ALIGN (4); |
| |
| } > ITCM :rom_exec |
| |
| .data : AT(__etext) |
| { |
| __data_start__ = .; |
| *(vtable) |
| *(.data) |
| *(.data.*) |
| |
| . = ALIGN(4); |
| /* preinit data */ |
| PROVIDE_HIDDEN (__preinit_array_start = .); |
| KEEP(*(.preinit_array)) |
| PROVIDE_HIDDEN (__preinit_array_end = .); |
| |
| . = ALIGN(4); |
| /* init data */ |
| PROVIDE_HIDDEN (__init_array_start = .); |
| KEEP(*(SORT(.init_array.*))) |
| KEEP(*(.init_array)) |
| PROVIDE_HIDDEN (__init_array_end = .); |
| |
| . = ALIGN(4); |
| /* finit data */ |
| PROVIDE_HIDDEN (__fini_array_start = .); |
| KEEP(*(SORT(.fini_array.*))) |
| KEEP(*(.fini_array)) |
| PROVIDE_HIDDEN (__fini_array_end = .); |
| |
| KEEP(*(.jcr*)) |
| . = ALIGN(4); |
| /* All data end */ |
| __data_end__ = .; |
| |
| } > DTCM :rom_exec |
| |
| .sram.bss : |
| { |
| . = ALIGN(16); |
| #ifdef ETHOSU_FAST_MEMORY_SIZE |
| *(.bss.ethosu_scratch); |
| #else |
| *(.bss.tensor_arena) |
| #endif |
| *.(output_data_sec) |
| } > SRAM :null |
| |
| .ddr : |
| { |
| #ifdef ETHOSU_FAST_MEMORY_SIZE |
| . = ALIGN(16); |
| *(.bss.tensor_arena) |
| #endif |
| . = ALIGN(4); |
| *(input_data_sec) |
| . = ALIGN(16); |
| *(network_model_sec) |
| *(expected_output_data_sec) |
| } > DDR :rom_dram |
| |
| __eddr_data = ALIGN (16) ; |
| .sram.data : { |
| __sram_data_start__ = .; |
| *(.sram.data) |
| __sram_data_end__ = .; |
| } > SRAM AT >DDR :rom_dram |
| |
| .bss : |
| { |
| . = ALIGN(4); |
| __bss_start__ = .; |
| *(.bss) |
| *(.bss.*) |
| *(COMMON) |
| . = ALIGN(4); |
| __bss_end__ = .; |
| } > DTCM :null |
| |
| .heap (COPY) : |
| { |
| . = ALIGN(8); |
| __end__ = .; |
| PROVIDE(end = .); |
| . = . + __HEAP_SIZE; |
| . = ALIGN(8); |
| __HeapLimit = .; |
| } > DTCM :null |
| |
| .stack (ORIGIN(DTCM) + LENGTH(DTCM) - __STACK_SIZE) (COPY) : |
| { |
| . = ALIGN(8); |
| __StackLimit = .; |
| . = . + __STACK_SIZE; |
| . = ALIGN(8); |
| __StackTop = .; |
| } > DTCM :null |
| PROVIDE(__stack = __StackTop); |
| |
| /* Check if data + heap + stack exceeds DTCM limit */ |
| ASSERT(__StackLimit >= __HeapLimit, "region DTCM overflowed with stack") |
| } |