Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 1 | #! cpp |
| 2 | |
| 3 | /* |
Jonny Svärd | f521be9 | 2021-03-01 14:35:49 +0100 | [diff] [blame] | 4 | * Copyright (c) 2019-2021 Arm Limited. All rights reserved. |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 5 | * |
| 6 | * SPDX-License-Identifier: Apache-2.0 |
| 7 | * |
| 8 | * Licensed under the Apache License, Version 2.0 (the License); you may |
| 9 | * not use this file except in compliance with the License. |
| 10 | * You may obtain a copy of the License at |
| 11 | * |
| 12 | * www.apache.org/licenses/LICENSE-2.0 |
| 13 | * |
| 14 | * Unless required by applicable law or agreed to in writing, software |
| 15 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT |
| 16 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 17 | * See the License for the specific language governing permissions and |
| 18 | * limitations under the License. |
| 19 | */ |
| 20 | |
Kristofer Jonsson | b5f7cfe | 2021-03-10 17:13:52 +0100 | [diff] [blame^] | 21 | /* |
| 22 | * This is a simplified picture of the Corstone-300 memory system. |
| 23 | * Please refer to the Corstone SSE-300 Technical Reference Manual for |
| 24 | * further information. |
| 25 | * |
| 26 | * https://developer.arm.com/ip-products/subsystem/corstone/corstone-300 |
| 27 | * |
| 28 | * +---------------+ +---------------+ +------+ |
| 29 | * | Ethos-U55 | | Cortex-M55 +--+ ITCM | |
| 30 | * | | | | +------+ |
| 31 | * | | | | |
| 32 | * | | | | +------+ |
| 33 | * | M1 M0 | | +--+ DTCM | |
| 34 | * +---+-------+---+ +-------+-------+ +------+ |
| 35 | * | | | |
| 36 | * | +---+---------------+-----+ |
| 37 | * | | AMBA AXI NIC-400-Lite | |
| 38 | * | +---+-----------------+---+ |
| 39 | * | | | |
| 40 | * +---+-------+------------+ +--+-------+ |
| 41 | * | AMBA AXI NIC-400 | | SSE-300 | |
| 42 | * +---+--------+--------+--+ | SRAM | |
| 43 | * | | | +----------+ |
| 44 | * +---+---+ +--+---+ +--+--+ |
| 45 | * | Flash | | BRAM | | DDR | |
| 46 | * +-------+ +------+ +-----+ |
| 47 | * |
| 48 | * +-----------------------+-------------+-------------+----+--------------------------------------+ |
| 49 | * | Memory region name | Base addr | Size |IDAU| MCC load address + remarks | |
| 50 | * +-----------------------+-------------+-------------+----+--------------------------------------+ |
| 51 | * | ITCM | 0x0000_0000 | 0x0008_0000 | NS | 0x0000_0000; 512 kiB | |
| 52 | * | ITCM | 0x1000_0000 | 0x0008_0000 | S | Secure alias for NS ITCM | |
| 53 | * | FPGA Data SRAM; BRAM | 0x0100_0000 | 0x0020_0000 | NS | 0x0100_0000; 2 MiB | |
| 54 | * | FPGA data SRAM; BRAM | 0x1100_0000 | 0x0020_0000 | S | Secure alias for NS BRAM | |
| 55 | * | DTCM | 0x2000_0000 | 0x0008_0000 | NS | 512 kiB; 4 banks of 128k each | |
| 56 | * | DTCM | 0x3000_0000 | 0x0008_0000 | S | Secure alias for NS DTCM | |
| 57 | * | SSE-300 internal SRAM | 0x2100_0000 | 0x0040_0000 | NS | 2 banks of 2 MiB each; 3cc latency) | |
| 58 | * | SSE-300 internal SRAM | 0x3100_0000 | 0x0040_0000 | S | Secure alias for NS internal SRAM | |
| 59 | * | DDR | 0x6000_0000 | 0x1000_0000 | NS | 0x0800_0000; 256 MiB bank | |
| 60 | * | DDR | 0x7000_0000 | 0x1000_0000 | S | 0x0C00_0000; 256 MiB bank | |
| 61 | * +-----------------------+-------------+-------------+----+--------------------------------------+ |
| 62 | * |
| 63 | * Note: Ethos-U55 can access BRAM, internal SRAM and the DDR sections => activation buffers and |
| 64 | * the model should only be placed in those regions. |
| 65 | * |
| 66 | * Note: Alias regions means that secure and non-secure addresses are mapped to the same physical |
| 67 | * memory banks. |
| 68 | */ |
| 69 | |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 70 | #ifndef STACK_SIZE |
| 71 | #define STACK_SIZE 0x8000 |
| 72 | #endif |
| 73 | |
| 74 | #ifndef HEAP_SIZE |
| 75 | #define HEAP_SIZE 0x8000 |
| 76 | #endif |
| 77 | |
Kristofer Jonsson | f62c3d7 | 2021-01-21 17:39:03 +0100 | [diff] [blame] | 78 | #if defined(TRUSTZONE_BUILD) && !defined(ETHOSU_TEST) |
| 79 | /* |
| 80 | * Include trustzone.h with common addresses and sizes. |
| 81 | * The build configuration sets whether TRUSTZONE_SECURE is set or |
| 82 | * TRUSTZONE_NONSECURE which sets the memory start addresses and sizes. |
| 83 | */ |
| 84 | |
| 85 | #include "trustzone.h" |
| 86 | #define USE_TRUSTZONE |
| 87 | |
| 88 | #else //TRUSTZONE_BUILD |
| 89 | |
| 90 | #define LR_START 0x10000000 |
Per Åstrand | 79929ff | 2021-01-26 14:42:43 +0100 | [diff] [blame] | 91 | #define LR_SIZE 0x00080000 |
Kristofer Jonsson | f62c3d7 | 2021-01-21 17:39:03 +0100 | [diff] [blame] | 92 | |
| 93 | #define ITCM_START 0x10000000 |
| 94 | #define ITCM_SIZE 0x00080000 |
| 95 | |
| 96 | #define BRAM_START 0x11000000 |
| 97 | #define BRAM_SIZE 0x00200000 |
| 98 | |
| 99 | #define DTCM_START 0x30000000 |
| 100 | #define DTCM_SIZE 0x00080000 |
| 101 | |
| 102 | #define SRAM_START 0x31000000 |
| 103 | #define SRAM_SIZE 0x00200000 |
| 104 | |
| 105 | #define DDR_START 0x70000000 |
| 106 | #define DDR_SIZE 0x02000000 |
| 107 | |
| 108 | #define STACK_HEAP 0x30080000 |
| 109 | |
| 110 | #endif //TRUSTZONE_BUILD |
| 111 | |
| 112 | /* ---------------------------------------------------------------------------- |
| 113 | Stack seal size definition |
| 114 | *----------------------------------------------------------------------------*/ |
| 115 | #if defined(USE_TRUSTZONE) && defined(TRUSTZONE_SECURE) |
| 116 | #define __STACKSEAL_SIZE ( 8 ) |
| 117 | #else |
| 118 | #define __STACKSEAL_SIZE ( 0 ) |
| 119 | #endif |
| 120 | |
| 121 | APP_IMAGE LR_START LR_SIZE |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 122 | { |
| 123 | ; ITCM 512kB |
Kristofer Jonsson | f62c3d7 | 2021-01-21 17:39:03 +0100 | [diff] [blame] | 124 | rom_exec ITCM_START ITCM_SIZE |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 125 | { |
| 126 | *.o (RESET, +First) |
| 127 | *(InRoot$$Sections) |
Kristofer Jonsson | f62c3d7 | 2021-01-21 17:39:03 +0100 | [diff] [blame] | 128 | ; Make sure reset_handler ends up in root segment, when split across |
| 129 | ; ITCM and DTCM |
| 130 | startup_ARMCM55.o |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 131 | .ANY (+RO) |
| 132 | } |
| 133 | |
Kristofer Jonsson | f62c3d7 | 2021-01-21 17:39:03 +0100 | [diff] [blame] | 134 | #if defined(USE_TRUSTZONE) && defined(TRUSTZONE_SECURE) |
| 135 | ; MPS3 BRAM |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 136 | ; Shared between Cortex-M and the NPU |
Kristofer Jonsson | b5f7cfe | 2021-03-10 17:13:52 +0100 | [diff] [blame^] | 137 | BRAM BRAM_START (BRAM_SIZE - TZ_NSC_SIZE) |
Kristofer Jonsson | f62c3d7 | 2021-01-21 17:39:03 +0100 | [diff] [blame] | 138 | { |
Kristofer Jonsson | b5f7cfe | 2021-03-10 17:13:52 +0100 | [diff] [blame^] | 139 | * (.sram.data) |
Kristofer Jonsson | f62c3d7 | 2021-01-21 17:39:03 +0100 | [diff] [blame] | 140 | } |
| 141 | |
| 142 | ROM_NSC TZ_NSC_START TZ_NSC_SIZE |
| 143 | { |
| 144 | *(Veneer$$CMSE) |
| 145 | } |
| 146 | #else |
| 147 | ; MPS3 BRAM |
Kristofer Jonsson | b5f7cfe | 2021-03-10 17:13:52 +0100 | [diff] [blame^] | 148 | BRAM BRAM_START BRAM_SIZE |
Kristofer Jonsson | f62c3d7 | 2021-01-21 17:39:03 +0100 | [diff] [blame] | 149 | { |
Kristofer Jonsson | b5f7cfe | 2021-03-10 17:13:52 +0100 | [diff] [blame^] | 150 | * (.sram.data) |
Kristofer Jonsson | f62c3d7 | 2021-01-21 17:39:03 +0100 | [diff] [blame] | 151 | } |
| 152 | #endif |
| 153 | |
| 154 | ; DTCM 512kB |
| 155 | ; Only accessible from the Cortex-M |
| 156 | DTCM DTCM_START (DTCM_SIZE - STACK_SIZE - HEAP_SIZE - __STACKSEAL_SIZE) |
| 157 | { |
| 158 | .ANY1 (+RW +ZI) |
| 159 | } |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 160 | |
| 161 | ; SSE-300 SRAM (3 cycles read latency) from M55/U55 |
| 162 | ; 2x2MB - only first part mapped |
Kristofer Jonsson | f62c3d7 | 2021-01-21 17:39:03 +0100 | [diff] [blame] | 163 | SRAM SRAM_START UNINIT SRAM_SIZE |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 164 | { |
| 165 | #ifndef ETHOSU_FAST_MEMORY_SIZE |
| 166 | ; Place tensor arena in SRAM if we do not have a fast memory area |
Jonny Svärd | f521be9 | 2021-03-01 14:35:49 +0100 | [diff] [blame] | 167 | * (.bss.tensor_arena) |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 168 | #else |
| 169 | * (.bss.ethosu_scratch) |
| 170 | #endif |
| 171 | } |
| 172 | |
Kristofer Jonsson | f62c3d7 | 2021-01-21 17:39:03 +0100 | [diff] [blame] | 173 | ARM_LIB_HEAP (STACK_HEAP - STACK_SIZE - __STACKSEAL_SIZE - HEAP_SIZE) EMPTY ALIGN 8 HEAP_SIZE {} |
| 174 | ARM_LIB_STACK (STACK_HEAP - STACK_SIZE - __STACKSEAL_SIZE) EMPTY ALIGN 8 STACK_SIZE {} |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 175 | |
Kristofer Jonsson | f62c3d7 | 2021-01-21 17:39:03 +0100 | [diff] [blame] | 176 | #if defined(USE_TRUSTZONE) && defined(TRUSTZONE_SECURE) |
| 177 | STACKSEAL +0 EMPTY __STACKSEAL_SIZE { |
| 178 | ; Reserve empty region for stack seal immediately after stack |
| 179 | } |
| 180 | #endif |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 181 | } |
| 182 | |
Kristofer Jonsson | f62c3d7 | 2021-01-21 17:39:03 +0100 | [diff] [blame] | 183 | LOAD_REGION_1 DDR_START DDR_SIZE |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 184 | { |
| 185 | ; 2GB DDR4 available |
Kristofer Jonsson | f62c3d7 | 2021-01-21 17:39:03 +0100 | [diff] [blame] | 186 | rom_dram DDR_START |
| 187 | #if defined(USE_TRUSTZONE) && defined(TRUSTZONE_NONSECURE) |
| 188 | { |
| 189 | } |
| 190 | #else //trustzone secure or non-trustzone |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 191 | { |
| 192 | * (network_model_sec) |
| 193 | * (input_data_sec) |
| 194 | * (expected_output_data_sec) |
Kristofer Jonsson | f62c3d7 | 2021-01-21 17:39:03 +0100 | [diff] [blame] | 195 | * (output_data_sec) |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 196 | } |
| 197 | |
| 198 | #ifdef ETHOSU_FAST_MEMORY_SIZE |
| 199 | ; Place tensor arena in DRAM if we have a fast memory area |
| 200 | ARENA +0 UNINIT ALIGN 16 |
| 201 | { |
Jonny Svärd | f521be9 | 2021-03-01 14:35:49 +0100 | [diff] [blame] | 202 | * (.bss.tensor_arena) |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 203 | } |
| 204 | #endif |
Kristofer Jonsson | f62c3d7 | 2021-01-21 17:39:03 +0100 | [diff] [blame] | 205 | #endif |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 206 | } |