diff --git a/targets/corstone-310/target.cpp b/targets/corstone-310/target.cpp
index ea20077..f946a74 100644
--- a/targets/corstone-310/target.cpp
+++ b/targets/corstone-310/target.cpp
@@ -1,6 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright 2020-2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
- *
+ * SPDX-FileCopyrightText: Copyright 2020-2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
  * SPDX-License-Identifier: Apache-2.0
  *
  * Licensed under the Apache License, Version 2.0 (the License); you may
@@ -24,7 +23,6 @@
 
 #ifdef ETHOSU
 #include <ethosu_driver.h>
-#include <timing_adapter.h>
 #endif
 
 #include "mpu.hpp"
@@ -45,9 +43,6 @@
 #define ETHOSU_IRQ          16
 #define ETHOSU_IRQ_PRIORITY 5
 
-#define ETHOSU0_TA0_BASE_ADDRESS 0x58103000
-#define ETHOSU0_TA1_BASE_ADDRESS 0x58103200
-
 /****************************************************************************
  * Variables
  ****************************************************************************/
@@ -64,152 +59,6 @@
 #endif
 
 /****************************************************************************
- * Timing Adapters
- ****************************************************************************/
-
-#ifdef ETHOSU
-
-#ifndef ETHOSU_TA_MAXR_0
-#define ETHOSU_TA_MAXR_0 0
-#endif
-
-#ifndef ETHOSU_TA_MAXW_0
-#define ETHOSU_TA_MAXW_0 0
-#endif
-
-#ifndef ETHOSU_TA_MAXRW_0
-#define ETHOSU_TA_MAXRW_0 0
-#endif
-
-#ifndef ETHOSU_TA_RLATENCY_0
-#define ETHOSU_TA_RLATENCY_0 0
-#endif
-
-#ifndef ETHOSU_TA_WLATENCY_0
-#define ETHOSU_TA_WLATENCY_0 0
-#endif
-
-#ifndef ETHOSU_TA_PULSE_ON_0
-#define ETHOSU_TA_PULSE_ON_0 0
-#endif
-
-#ifndef ETHOSU_TA_PULSE_OFF_0
-#define ETHOSU_TA_PULSE_OFF_0 0
-#endif
-
-#ifndef ETHOSU_TA_BWCAP_0
-#define ETHOSU_TA_BWCAP_0 0
-#endif
-
-#ifndef ETHOSU_TA_PERFCTRL_0
-#define ETHOSU_TA_PERFCTRL_0 0
-#endif
-
-#ifndef ETHOSU_TA_PERFCNT_0
-#define ETHOSU_TA_PERFCNT_0 0
-#endif
-
-#ifndef ETHOSU_TA_MODE_0
-#define ETHOSU_TA_MODE_0 1
-#endif
-
-#ifndef ETHOSU_TA_HISTBIN_0
-#define ETHOSU_TA_HISTBIN_0 0
-#endif
-
-#ifndef ETHOSU_TA_HISTCNT_0
-#define ETHOSU_TA_HISTCNT_0 0
-#endif
-
-#ifndef ETHOSU_TA_MAXR_1
-#define ETHOSU_TA_MAXR_1 0
-#endif
-
-#ifndef ETHOSU_TA_MAXW_1
-#define ETHOSU_TA_MAXW_1 0
-#endif
-
-#ifndef ETHOSU_TA_MAXRW_1
-#define ETHOSU_TA_MAXRW_1 0
-#endif
-
-#ifndef ETHOSU_TA_RLATENCY_1
-#define ETHOSU_TA_RLATENCY_1 0
-#endif
-
-#ifndef ETHOSU_TA_WLATENCY_1
-#define ETHOSU_TA_WLATENCY_1 0
-#endif
-
-#ifndef ETHOSU_TA_PULSE_ON_1
-#define ETHOSU_TA_PULSE_ON_1 0
-#endif
-
-#ifndef ETHOSU_TA_PULSE_OFF_1
-#define ETHOSU_TA_PULSE_OFF_1 0
-#endif
-
-#ifndef ETHOSU_TA_BWCAP_1
-#define ETHOSU_TA_BWCAP_1 0
-#endif
-
-#ifndef ETHOSU_TA_PERFCTRL_1
-#define ETHOSU_TA_PERFCTRL_1 0
-#endif
-
-#ifndef ETHOSU_TA_PERFCNT_1
-#define ETHOSU_TA_PERFCNT_1 0
-#endif
-
-#ifndef ETHOSU_TA_MODE_1
-#define ETHOSU_TA_MODE_1 1
-#endif
-
-#ifndef ETHOSU_TA_HISTBIN_1
-#define ETHOSU_TA_HISTBIN_1 0
-#endif
-
-#ifndef ETHOSU_TA_HISTCNT_1
-#define ETHOSU_TA_HISTCNT_1 0
-#endif
-
-#if defined(ETHOSU_TARGET_NPU_TA_COUNT) && ETHOSU_TARGET_NPU_TA_COUNT >= 2
-static uintptr_t ethosu_ta_base_addrs[ETHOSU_NPU_COUNT][ETHOSU_NPU_TA_COUNT] = {
-    {ETHOSU0_TA0_BASE_ADDRESS, ETHOSU0_TA1_BASE_ADDRESS}};
-struct timing_adapter ethosu_ta[ETHOSU_NPU_COUNT][ETHOSU_NPU_TA_COUNT];
-struct timing_adapter_settings ethosu_ta_settings[ETHOSU_NPU_TA_COUNT] = {{ETHOSU_TA_MAXR_0,
-                                                                           ETHOSU_TA_MAXW_0,
-                                                                           ETHOSU_TA_MAXRW_0,
-                                                                           ETHOSU_TA_RLATENCY_0,
-                                                                           ETHOSU_TA_WLATENCY_0,
-                                                                           ETHOSU_TA_PULSE_ON_0,
-                                                                           ETHOSU_TA_PULSE_OFF_0,
-                                                                           ETHOSU_TA_BWCAP_0,
-                                                                           ETHOSU_TA_PERFCTRL_0,
-                                                                           ETHOSU_TA_PERFCNT_0,
-                                                                           ETHOSU_TA_MODE_0,
-                                                                           0, // Read only register
-                                                                           ETHOSU_TA_HISTBIN_0,
-                                                                           ETHOSU_TA_HISTCNT_0},
-                                                                          {ETHOSU_TA_MAXR_1,
-                                                                           ETHOSU_TA_MAXW_1,
-                                                                           ETHOSU_TA_MAXRW_1,
-                                                                           ETHOSU_TA_RLATENCY_1,
-                                                                           ETHOSU_TA_WLATENCY_1,
-                                                                           ETHOSU_TA_PULSE_ON_1,
-                                                                           ETHOSU_TA_PULSE_OFF_1,
-                                                                           ETHOSU_TA_BWCAP_1,
-                                                                           ETHOSU_TA_PERFCTRL_1,
-                                                                           ETHOSU_TA_PERFCNT_1,
-                                                                           ETHOSU_TA_MODE_1,
-                                                                           0, // Read only register
-                                                                           ETHOSU_TA_HISTBIN_1,
-                                                                           ETHOSU_TA_HISTCNT_1}};
-#endif
-
-#endif
-
-/****************************************************************************
  * Cache maintenance
  ****************************************************************************/
 
@@ -290,20 +139,6 @@
     UartStdOutInit();
 
 #ifdef ETHOSU
-    // Initialize timing adapter(s)
-    for (int i = 0; i < ETHOSU_NPU_COUNT; i++) {
-#if defined(ETHOSU_TARGET_NPU_TA_COUNT) && ETHOSU_TARGET_NPU_TA_COUNT >= 2
-        for (int j = 0; j < ETHOSU_NPU_TA_COUNT; j++) {
-            if (ta_init(&ethosu_ta[i][j], ethosu_ta_base_addrs[i][j])) {
-                printf("Failed to initialize timing-adapter %d for NPU %d\n", j, i);
-            } else {
-                // Set the updated configuration
-                ta_set_all(&ethosu_ta[i][j], &ethosu_ta_settings[j]);
-            }
-        }
-#endif
-    }
-
     // Initialize Ethos-U NPU driver
     if (ethosu_init(&ethosu0_driver,
                     reinterpret_cast<void *>(ETHOSU_BASE_ADDRESS),