commit 991af2bd8fb6c79dfb317837353857f34a727b17
author Jonny Svärd <jonny.svaerd@arm.com> Thu Apr 15 17:31:01 2021 +0200
committer Jonny Svärd <jonny.svaerd@arm.com> Thu Apr 22 15:26:46 2021 +0200
tree 2c6a99f938eb5842e65561dcb1d6bac82f6b4483
parent 908a07c61db978679a11a0f4ee023dc3c6aabffd

Enable MPU and CPU cache for Corstone-300

- Enable CPU instruction- and data cache by default.
- Add a CMake option to turn CPU cache on/off.

- Add basic MPU configuration for memory areas. Make the code
  segment RO (NS address' are reachable from secure state,
  hence MPU config entries for both S and NS address of ITCM).

- Target latest NPU API version
Change-Id: Ie9bf2f02e5ad534375d146804fdc66b9f2f6770f

Change-Id: I9def430d1e61d18e521798db4f48ed0a8c58380e

targets/corstone-300/target.cpp

diff --git a/targets/corstone-300/target.cpp b/targets/corstone-300/target.cpp
index e5f4680..a44c12f 100644
--- a/targets/corstone-300/target.cpp
+++ b/targets/corstone-300/target.cpp
@@ -26,6 +26,7 @@
 #include <ethosu_driver.h>
 #endif
 
+#include "mpu.hpp"
 #include <timing_adapter.h>
 
 #include "uart.h"
@@ -33,6 +34,7 @@
 #include <inttypes.h>
 #include <stdio.h>
 #include <stdlib.h>
+#include <vector>
 
 using namespace EthosU;
 
@@ -57,6 +59,10 @@
 #define ETHOSU_FAST_MEMORY_SIZE 0
 #endif
 
+#ifdef ETHOSU
+struct ethosu_driver *ethosu0_driver = &ethosu_drv;
+#endif
+
 static uintptr_t ethosu_ta_base_addrs[ETHOSU_NPU_COUNT][ETHOSU_NPU_TA_COUNT] = {
     {ETHOSU0_TA0_BASE_ADDRESS, ETHOSU0_TA1_BASE_ADDRESS}};
 struct timing_adapter ethosu_ta[ETHOSU_NPU_COUNT][ETHOSU_NPU_TA_COUNT];
@@ -152,15 +158,90 @@
 
 #ifdef ETHOSU
     // Initialize Ethos-U NPU driver
-    if (ethosu_init_v3(reinterpret_cast<void *>(ETHOSU_BASE_ADDRESS), ethosu_scratch, ETHOSU_FAST_MEMORY_SIZE, 1, 1)) {
+    if (ethosu_init_v4(ethosu0_driver,
+                       reinterpret_cast<void *>(ETHOSU_BASE_ADDRESS),
+                       ethosu_scratch,
+                       ETHOSU_FAST_MEMORY_SIZE,
+                       1,
+                       1)) {
         printf("Failed to initialize NPU.\n");
         return;
     }
 
-    /* Assumes SCB->VTOR point to RW memory */
+    // Assumes SCB->VTOR point to RW memory
     NVIC_SetVector(static_cast<IRQn_Type>(ETHOSU_IRQ), (uint32_t)&ethosuIrqHandler);
     NVIC_EnableIRQ(static_cast<IRQn_Type>(ETHOSU_IRQ));
 #endif
+
+    // MPU setup
+    const std::vector<ARM_MPU_Region_t> mpuConfig = {
+        {
+            // ITCM
+            ARM_MPU_RBAR(0x00000000,      // Base
+                         ARM_MPU_SH_NON,  // Non-shareable
+                         1,               // Read-Only
+                         1,               // Non-Privileged
+                         0),              // eXecute Never disabled
+            ARM_MPU_RLAR(0x0007ffff,      // Limit
+                         Mpu::WTRA_index) // Attribute index - Write-Through, Read-allocate
+        },
+        {
+            // ITCM
+            ARM_MPU_RBAR(0x10000000,      // Base
+                         ARM_MPU_SH_NON,  // Non-shareable
+                         1,               // Read-Only
+                         1,               // Non-Privileged
+                         0),              // eXecute Never disabled
+            ARM_MPU_RLAR(0x1007ffff,      // Limit
+                         Mpu::WTRA_index) // Attribute index - Write-Through, Read-allocate
+        },
+        {
+            // FPGA DATA SRAM; BRAM
+            ARM_MPU_RBAR(0x11000000,        // Base
+                         ARM_MPU_SH_NON,    // Non-shareable
+                         0,                 // Read-Write
+                         1,                 // Non-Privileged
+                         0),                // eXecute Never disabled
+            ARM_MPU_RLAR(0x111fffff,        // Limit
+                         Mpu::WBWARA_index) // Attribute index - Write-Back, Write-Allocate, Read-allocate
+        },
+        {
+            // DTCM
+            ARM_MPU_RBAR(0x30000000,        // Base
+                         ARM_MPU_SH_NON,    // Non-shareable
+                         0,                 // Read-Write
+                         1,                 // Non-Privileged
+                         1),                // eXecute Never enabled
+            ARM_MPU_RLAR(0x3007ffff,        // Limit
+                         Mpu::WBWARA_index) // Attribute index - Write-Back, Write-Allocate, Read-allocate
+        },
+        {
+            // SSE-300 internal SRAM
+            ARM_MPU_RBAR(0x31000000,        // Base
+                         ARM_MPU_SH_NON,    // Non-shareable
+                         0,                 // Read-Write
+                         1,                 // Non-Privileged
+                         1),                // eXecute Never enabled
+            ARM_MPU_RLAR(0x313fffff,        // Limit
+                         Mpu::WBWARA_index) // Attribute index - Write-Back, Write-Allocate, Read-allocate
+        },
+        {
+            ARM_MPU_RBAR(0x70000000,        // Base
+                         ARM_MPU_SH_NON,    // Non-shareable
+                         0,                 // Read-Write
+                         1,                 // Non-Privileged
+                         1),                // eXecute Never enabled
+            ARM_MPU_RLAR(0x7fffffff,        // Limit
+                         Mpu::WBWARA_index) // Attribute index - Write-Back, Write-Allocate, Read-allocate
+        }};
+
+    // Setup MPU configuration
+    Mpu::loadAndEnableConfig(&mpuConfig[0], mpuConfig.size());
+
+#if defined(CPU_CACHE_ENABLE) && defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    SCB_EnableICache();
+    SCB_EnableDCache();
+#endif
 }
 
 } // namespace EthosU