Add negative testing to message_handler
Also restructure the scatter file to not be constrained of the
artificial 512k size limit of the APP_IMAGE region.
Add missing sections in DDR for both scatter file and linker script.
Change-Id: I3d9bc8aeae1b1c11ab994276be64a2850cc23f8e
diff --git a/targets/corstone-300/platform.scatter b/targets/corstone-300/platform.scatter
index 55e21b7..d683100 100644
--- a/targets/corstone-300/platform.scatter
+++ b/targets/corstone-300/platform.scatter
@@ -144,6 +144,25 @@
.ANY (+RO)
}
+ ; DTCM 512kB
+ ; Only accessible from the Cortex-M
+ DTCM DTCM_START (DTCM_SIZE - STACK_SIZE - HEAP_SIZE - __STACKSEAL_SIZE)
+ {
+ .ANY1 (+RW +ZI)
+ }
+
+ ARM_LIB_HEAP (STACK_HEAP - STACK_SIZE - __STACKSEAL_SIZE - HEAP_SIZE) EMPTY ALIGN 8 HEAP_SIZE {}
+ ARM_LIB_STACK (STACK_HEAP - STACK_SIZE - __STACKSEAL_SIZE) EMPTY ALIGN 8 STACK_SIZE {}
+
+#if defined(USE_TRUSTZONE) && defined(TRUSTZONE_SECURE)
+ STACKSEAL +0 EMPTY __STACKSEAL_SIZE {
+ ; Reserve empty region for stack seal immediately after stack
+ }
+#endif
+}
+
+LOAD_REGION_BRAM BRAM_START BRAM_SIZE
+{
#if defined(USE_TRUSTZONE) && defined(TRUSTZONE_SECURE)
; MPS3 BRAM
; Shared between Cortex-M and the NPU
@@ -163,14 +182,10 @@
* (.sram.data)
}
#endif
+}
- ; DTCM 512kB
- ; Only accessible from the Cortex-M
- DTCM DTCM_START (DTCM_SIZE - STACK_SIZE - HEAP_SIZE - __STACKSEAL_SIZE)
- {
- .ANY1 (+RW +ZI)
- }
-
+LOAD_REGION_SRAM SRAM_START SRAM_SIZE
+{
; 2MB SSE-300 SRAM (3 cycles read latency) from M55/U55
SRAM SRAM_START SRAM_SIZE
{
@@ -187,15 +202,6 @@
; Place scratch buffer in SRAM
* (.bss.ethosu_scratch)
}
-
- ARM_LIB_HEAP (STACK_HEAP - STACK_SIZE - __STACKSEAL_SIZE - HEAP_SIZE) EMPTY ALIGN 8 HEAP_SIZE {}
- ARM_LIB_STACK (STACK_HEAP - STACK_SIZE - __STACKSEAL_SIZE) EMPTY ALIGN 8 STACK_SIZE {}
-
-#if defined(USE_TRUSTZONE) && defined(TRUSTZONE_SECURE)
- STACKSEAL +0 EMPTY __STACKSEAL_SIZE {
- ; Reserve empty region for stack seal immediately after stack
- }
-#endif
}
LOAD_REGION_1 DDR_START DDR_SIZE
@@ -215,6 +221,9 @@
* (expected_output_data_sec)
* (output_data_sec)
* (sec_command_stream, sec_weight_data, sec_input_data)
+
+ * (ethosu_core_in_queue)
+ * (ethosu_core_out_queue)
}
#if (ETHOSU_ARENA == 1)