Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 1 | /* |
Mikael Olsson | ad5b6f2 | 2024-01-22 14:48:28 +0100 | [diff] [blame] | 2 | * SPDX-FileCopyrightText: Copyright 2009-2024 Arm Limited and/or its affiliates <open-source-office@arm.com> |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: Apache-2.0 |
| 5 | * |
| 6 | * Licensed under the Apache License, Version 2.0 (the License); you may |
| 7 | * not use this file except in compliance with the License. |
| 8 | * You may obtain a copy of the License at |
| 9 | * |
| 10 | * www.apache.org/licenses/LICENSE-2.0 |
| 11 | * |
| 12 | * Unless required by applicable law or agreed to in writing, software |
| 13 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT |
| 14 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 15 | * See the License for the specific language governing permissions and |
| 16 | * limitations under the License. |
| 17 | */ |
| 18 | |
Nir Ekhauz | 3adfbc1 | 2021-05-24 13:16:52 +0300 | [diff] [blame] | 19 | /* |
| 20 | * This is a simplified picture of the Corstone-300 memory system. |
| 21 | * Please refer to the Corstone SSE-300 Technical Reference Manual for |
| 22 | * further information. |
| 23 | * |
| 24 | * https://developer.arm.com/ip-products/subsystem/corstone/corstone-300 |
| 25 | * |
| 26 | * +---------------+ +---------------+ +------+ |
| 27 | * | Ethos-U55 | | Cortex-M55 +--+ ITCM | |
| 28 | * | | | | +------+ |
| 29 | * | | | | |
| 30 | * | | | | +------+ |
| 31 | * | M1 M0 | | +--+ DTCM | |
| 32 | * +---+-------+---+ +-------+-------+ +------+ |
| 33 | * | | | |
| 34 | * | +---+---------------+-----+ |
| 35 | * | | AMBA AXI NIC-400-Lite | |
| 36 | * | +---+-----------------+---+ |
| 37 | * | | | |
| 38 | * +---+-------+------------+ +--+-------+ |
| 39 | * | AMBA AXI NIC-400 | | SSE-300 | |
| 40 | * +---+--------+--------+--+ | SRAM | |
| 41 | * | | | +----------+ |
| 42 | * +---+---+ +--+---+ +--+--+ |
| 43 | * | Flash | | BRAM | | DDR | |
| 44 | * +-------+ +------+ +-----+ |
| 45 | * |
| 46 | * +-----------------------+-------------+-------------+----+--------------------------------------+ |
| 47 | * | Memory region name | Base addr | Size |IDAU| MCC load address + remarks | |
| 48 | * +-----------------------+-------------+-------------+----+--------------------------------------+ |
| 49 | * | ITCM | 0x0000_0000 | 0x0008_0000 | NS | 0x0000_0000; 512 kiB | |
| 50 | * | ITCM | 0x1000_0000 | 0x0008_0000 | S | Secure alias for NS ITCM | |
Nir Ekhauz | 1a96939 | 2021-10-21 15:42:22 +0300 | [diff] [blame] | 51 | * | FPGA Data SRAM; BRAM | 0x0100_0000 | 0x0010_0000 | NS | 0x0100_0000; 1 MiB | |
| 52 | * | FPGA data SRAM; BRAM | 0x1100_0000 | 0x0010_0000 | S | Secure alias for NS BRAM | |
Nir Ekhauz | 3adfbc1 | 2021-05-24 13:16:52 +0300 | [diff] [blame] | 53 | * | DTCM | 0x2000_0000 | 0x0008_0000 | NS | 512 kiB; 4 banks of 128k each | |
| 54 | * | DTCM | 0x3000_0000 | 0x0008_0000 | S | Secure alias for NS DTCM | |
| 55 | * | SSE-300 internal SRAM | 0x2100_0000 | 0x0020_0000 | NS | 1 bank of 2 MiB; 3cc latency) | |
| 56 | * | SSE-300 internal SRAM | 0x3100_0000 | 0x0020_0000 | S | Secure alias for NS internal SRAM | |
Nir Ekhauz | 1a96939 | 2021-10-21 15:42:22 +0300 | [diff] [blame] | 57 | * | QSPI external flash | 0x2800_0000 | 0x0080_0000 | NS | 8MB | |
| 58 | * | QSPI external flash | 0x3800_0000 | 0x0080_0000 | S | 8MB | |
Nir Ekhauz | 3adfbc1 | 2021-05-24 13:16:52 +0300 | [diff] [blame] | 59 | * | DDR | 0x6000_0000 | 0x1000_0000 | NS | 0x0800_0000; 256 MiB bank | |
| 60 | * | DDR | 0x7000_0000 | 0x1000_0000 | S | 0x0C00_0000; 256 MiB bank | |
| 61 | * +-----------------------+-------------+-------------+----+--------------------------------------+ |
| 62 | * |
| 63 | * Note: Ethos-U55 can access BRAM, internal SRAM and the DDR sections => activation buffers and |
| 64 | * the model should only be placed in those regions. |
| 65 | * |
| 66 | * Note: Alias regions means that secure and non-secure addresses are mapped to the same physical |
| 67 | * memory banks. |
| 68 | */ |
| 69 | |
Nir Ekhauz | 3c505ca | 2021-06-06 14:57:50 +0300 | [diff] [blame] | 70 | #ifndef ETHOSU_MODEL |
| 71 | /* default value - '1', for DRAM */ |
| 72 | #define ETHOSU_MODEL 1 |
| 73 | #endif |
| 74 | |
| 75 | #ifndef ETHOSU_ARENA |
| 76 | /* default value - '1', for DRAM */ |
| 77 | #define ETHOSU_ARENA 1 |
| 78 | #endif |
| 79 | |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 80 | __STACK_SIZE = 0x00008000; |
| 81 | __HEAP_SIZE = 0x00008000; |
| 82 | |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 83 | MEMORY |
| 84 | { |
Per Åstrand | 0b7bbb4 | 2021-03-25 12:34:24 +0100 | [diff] [blame] | 85 | ITCM (rx) : ORIGIN = 0x10000000, LENGTH = 0x00080000 |
Nir Ekhauz | 1a96939 | 2021-10-21 15:42:22 +0300 | [diff] [blame] | 86 | BRAM (rw) : ORIGIN = 0x11000000, LENGTH = 0x00100000 |
Per Åstrand | 0b7bbb4 | 2021-03-25 12:34:24 +0100 | [diff] [blame] | 87 | DTCM (rw) : ORIGIN = 0x30000000, LENGTH = 0x00080000 |
Nir Ekhauz | 3adfbc1 | 2021-05-24 13:16:52 +0300 | [diff] [blame] | 88 | SRAM (rw) : ORIGIN = 0x31000000, LENGTH = 0x00200000 |
Nir Ekhauz | 1a96939 | 2021-10-21 15:42:22 +0300 | [diff] [blame] | 89 | QSPI (rw) : ORIGIN = 0x38000000, LENGTH = 0x00800000 |
Per Åstrand | 0b7bbb4 | 2021-03-25 12:34:24 +0100 | [diff] [blame] | 90 | DDR (rwx) : ORIGIN = 0x70000000, LENGTH = 0x60000000 |
| 91 | } |
| 92 | |
| 93 | PHDRS |
| 94 | { |
| 95 | rom_exec PT_LOAD; |
| 96 | rom_dram PT_LOAD; |
| 97 | null PT_NULL; |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 98 | } |
| 99 | |
| 100 | /* Linker script to place sections and symbol values. Should be used together |
| 101 | * with other linker script that defines memory regions ITCM and RAM. |
| 102 | * It references following symbols, which must be defined in code: |
| 103 | * Reset_Handler : Entry of reset handler |
| 104 | * |
| 105 | * It defines following symbols, which code can use without definition: |
| 106 | * __exidx_start |
| 107 | * __exidx_end |
| 108 | * __copy_table_start__ |
| 109 | * __copy_table_end__ |
| 110 | * __zero_table_start__ |
| 111 | * __zero_table_end__ |
| 112 | * __etext |
| 113 | * __data_start__ |
| 114 | * __preinit_array_start |
| 115 | * __preinit_array_end |
| 116 | * __init_array_start |
| 117 | * __init_array_end |
| 118 | * __fini_array_start |
| 119 | * __fini_array_end |
| 120 | * __data_end__ |
| 121 | * __bss_start__ |
| 122 | * __bss_end__ |
| 123 | * __end__ |
| 124 | * end |
| 125 | * __HeapLimit |
| 126 | * __StackLimit |
| 127 | * __StackTop |
| 128 | * __stack |
| 129 | */ |
Per Åstrand | 0b7bbb4 | 2021-03-25 12:34:24 +0100 | [diff] [blame] | 130 | |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 131 | ENTRY(Reset_Handler) |
| 132 | |
| 133 | SECTIONS |
| 134 | { |
| 135 | .text : |
| 136 | { |
Mikael Olsson | ad5b6f2 | 2024-01-22 14:48:28 +0100 | [diff] [blame] | 137 | _vectors = .; |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 138 | KEEP(*(.vectors)) |
Jonny Svärd | 9197443 | 2023-04-28 16:08:12 +0200 | [diff] [blame] | 139 | *(.text*) |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 140 | |
| 141 | KEEP(*(.init)) |
| 142 | KEEP(*(.fini)) |
| 143 | |
| 144 | /* .ctors */ |
| 145 | *crtbegin.o(.ctors) |
| 146 | *crtbegin?.o(.ctors) |
| 147 | *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) |
| 148 | *(SORT(.ctors.*)) |
| 149 | *(.ctors) |
| 150 | |
| 151 | /* .dtors */ |
| 152 | *crtbegin.o(.dtors) |
| 153 | *crtbegin?.o(.dtors) |
| 154 | *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) |
| 155 | *(SORT(.dtors.*)) |
| 156 | *(.dtors) |
| 157 | |
| 158 | *(.rodata*) |
| 159 | |
| 160 | KEEP(*(.eh_frame*)) |
Per Åstrand | 0b7bbb4 | 2021-03-25 12:34:24 +0100 | [diff] [blame] | 161 | } > ITCM :rom_exec |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 162 | |
| 163 | /* |
| 164 | * SG veneers: |
| 165 | * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address |
Kristofer Jonsson | b5f7cfe | 2021-03-10 17:13:52 +0100 | [diff] [blame] | 166 | * must be set, either with the command line option '--section-start' or in a linker script, |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 167 | * to indicate where to place these veneers in memory. |
| 168 | */ |
| 169 | /* |
| 170 | .gnu.sgstubs : |
| 171 | { |
| 172 | . = ALIGN(32); |
Per Åstrand | 0b7bbb4 | 2021-03-25 12:34:24 +0100 | [diff] [blame] | 173 | } > ITCM :rom_exec |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 174 | */ |
| 175 | .ARM.extab : |
| 176 | { |
| 177 | *(.ARM.extab* .gnu.linkonce.armextab.*) |
Per Åstrand | 0b7bbb4 | 2021-03-25 12:34:24 +0100 | [diff] [blame] | 178 | } > ITCM :rom_exec |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 179 | |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 180 | .ARM.exidx : |
| 181 | { |
Per Åstrand | 0b7bbb4 | 2021-03-25 12:34:24 +0100 | [diff] [blame] | 182 | __exidx_start = .; |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 183 | *(.ARM.exidx* .gnu.linkonce.armexidx.*) |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 184 | __exidx_end = .; |
Per Åstrand | 0b7bbb4 | 2021-03-25 12:34:24 +0100 | [diff] [blame] | 185 | } > ITCM :rom_exec |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 186 | |
| 187 | .copy.table : |
| 188 | { |
| 189 | . = ALIGN(4); |
| 190 | __copy_table_start__ = .; |
| 191 | LONG (__etext) |
| 192 | LONG (__data_start__) |
Davide Grohmann | 8b53aad | 2022-05-05 17:15:19 +0200 | [diff] [blame] | 193 | LONG ((__data_end__ - __data_start__) / 4) |
Kristofer Jonsson | b5f7cfe | 2021-03-10 17:13:52 +0100 | [diff] [blame] | 194 | |
Per Åstrand | 0b7bbb4 | 2021-03-25 12:34:24 +0100 | [diff] [blame] | 195 | LONG (__eddr_data) |
| 196 | LONG (__sram_data_start__) |
Davide Grohmann | 8b53aad | 2022-05-05 17:15:19 +0200 | [diff] [blame] | 197 | LONG ((__sram_data_end__ - __sram_data_start__) / 4) |
Per Åstrand | 0b7bbb4 | 2021-03-25 12:34:24 +0100 | [diff] [blame] | 198 | |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 199 | __copy_table_end__ = .; |
Per Åstrand | 0b7bbb4 | 2021-03-25 12:34:24 +0100 | [diff] [blame] | 200 | } > ITCM :rom_exec |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 201 | |
| 202 | .zero.table : |
| 203 | { |
| 204 | . = ALIGN(4); |
| 205 | __zero_table_start__ = .; |
Per Åstrand | 0b7bbb4 | 2021-03-25 12:34:24 +0100 | [diff] [blame] | 206 | LONG (__bss_start__) |
Davide Grohmann | 8b53aad | 2022-05-05 17:15:19 +0200 | [diff] [blame] | 207 | LONG ((__bss_end__ - __bss_start__) / 4) |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 208 | __zero_table_end__ = .; |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 209 | |
| 210 | /** |
| 211 | * Location counter can end up 2byte aligned with narrow Thumb code but |
| 212 | * __etext is assumed by startup code to be the LMA of a section in DTCM |
| 213 | * which must be 4byte aligned |
| 214 | */ |
| 215 | __etext = ALIGN (4); |
| 216 | |
Per Åstrand | 0b7bbb4 | 2021-03-25 12:34:24 +0100 | [diff] [blame] | 217 | } > ITCM :rom_exec |
| 218 | |
| 219 | .data : AT(__etext) |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 220 | { |
| 221 | __data_start__ = .; |
| 222 | *(vtable) |
Jonny Svärd | 9197443 | 2023-04-28 16:08:12 +0200 | [diff] [blame] | 223 | *(.data) |
| 224 | *(.data.*) |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 225 | |
| 226 | . = ALIGN(4); |
| 227 | /* preinit data */ |
| 228 | PROVIDE_HIDDEN (__preinit_array_start = .); |
| 229 | KEEP(*(.preinit_array)) |
| 230 | PROVIDE_HIDDEN (__preinit_array_end = .); |
| 231 | |
| 232 | . = ALIGN(4); |
| 233 | /* init data */ |
| 234 | PROVIDE_HIDDEN (__init_array_start = .); |
| 235 | KEEP(*(SORT(.init_array.*))) |
| 236 | KEEP(*(.init_array)) |
| 237 | PROVIDE_HIDDEN (__init_array_end = .); |
| 238 | |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 239 | . = ALIGN(4); |
| 240 | /* finit data */ |
| 241 | PROVIDE_HIDDEN (__fini_array_start = .); |
| 242 | KEEP(*(SORT(.fini_array.*))) |
| 243 | KEEP(*(.fini_array)) |
| 244 | PROVIDE_HIDDEN (__fini_array_end = .); |
| 245 | |
| 246 | KEEP(*(.jcr*)) |
| 247 | . = ALIGN(4); |
| 248 | /* All data end */ |
| 249 | __data_end__ = .; |
| 250 | |
Per Åstrand | 0b7bbb4 | 2021-03-25 12:34:24 +0100 | [diff] [blame] | 251 | } > DTCM :rom_exec |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 252 | |
Per Åstrand | 0b7bbb4 | 2021-03-25 12:34:24 +0100 | [diff] [blame] | 253 | .sram.bss : |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 254 | { |
| 255 | . = ALIGN(16); |
Nir Ekhauz | 3c505ca | 2021-06-06 14:57:50 +0300 | [diff] [blame] | 256 | #if (ETHOSU_MODEL == 0) |
| 257 | * (network_model_sec) |
| 258 | #endif |
| 259 | |
| 260 | #if (ETHOSU_ARENA == 0) |
Kristofer Jonsson | b5f7cfe | 2021-03-10 17:13:52 +0100 | [diff] [blame] | 261 | *(.bss.tensor_arena) |
| 262 | #endif |
Nir Ekhauz | 3c505ca | 2021-06-06 14:57:50 +0300 | [diff] [blame] | 263 | |
| 264 | *(.bss.ethosu_scratch); |
Per Åstrand | 0b7bbb4 | 2021-03-25 12:34:24 +0100 | [diff] [blame] | 265 | *.(output_data_sec) |
| 266 | } > SRAM :null |
Kristofer Jonsson | b5f7cfe | 2021-03-10 17:13:52 +0100 | [diff] [blame] | 267 | |
| 268 | .ddr : |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 269 | { |
Nir Ekhauz | 3c505ca | 2021-06-06 14:57:50 +0300 | [diff] [blame] | 270 | #if (ETHOSU_ARENA == 1) |
Per Åstrand | 0b7bbb4 | 2021-03-25 12:34:24 +0100 | [diff] [blame] | 271 | . = ALIGN(16); |
Jonny Svärd | f521be9 | 2021-03-01 14:35:49 +0100 | [diff] [blame] | 272 | *(.bss.tensor_arena) |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 273 | #endif |
Nir Ekhauz | 3c505ca | 2021-06-06 14:57:50 +0300 | [diff] [blame] | 274 | |
Per Åstrand | 0b7bbb4 | 2021-03-25 12:34:24 +0100 | [diff] [blame] | 275 | . = ALIGN(4); |
Kristofer Jonsson | b5f7cfe | 2021-03-10 17:13:52 +0100 | [diff] [blame] | 276 | *(input_data_sec) |
Kristofer Jonsson | b5f7cfe | 2021-03-10 17:13:52 +0100 | [diff] [blame] | 277 | . = ALIGN(16); |
Nir Ekhauz | 3c505ca | 2021-06-06 14:57:50 +0300 | [diff] [blame] | 278 | #if (ETHOSU_MODEL == 1) |
Kristofer Jonsson | b5f7cfe | 2021-03-10 17:13:52 +0100 | [diff] [blame] | 279 | *(network_model_sec) |
Nir Ekhauz | 3c505ca | 2021-06-06 14:57:50 +0300 | [diff] [blame] | 280 | #endif |
| 281 | * (expected_output_data_sec) |
Davide Grohmann | f4379e9 | 2022-06-15 11:20:41 +0200 | [diff] [blame] | 282 | * (sec_command_stream, sec_weight_data, sec_input_data) |
| 283 | |
| 284 | * (ethosu_core_in_queue) |
| 285 | * (ethosu_core_out_queue) |
Johan Alfvén | d188e90 | 2022-03-03 09:07:51 +0100 | [diff] [blame] | 286 | . = ALIGN(4); |
Per Åstrand | 0b7bbb4 | 2021-03-25 12:34:24 +0100 | [diff] [blame] | 287 | } > DDR :rom_dram |
| 288 | |
Johan Alfvén | d188e90 | 2022-03-03 09:07:51 +0100 | [diff] [blame] | 289 | __eddr_data = ALIGN (4) ; |
Per Åstrand | 0b7bbb4 | 2021-03-25 12:34:24 +0100 | [diff] [blame] | 290 | .sram.data : { |
| 291 | __sram_data_start__ = .; |
| 292 | *(.sram.data) |
| 293 | __sram_data_end__ = .; |
Nir Ekhauz | 3adfbc1 | 2021-05-24 13:16:52 +0300 | [diff] [blame] | 294 | } > BRAM AT >DDR :rom_dram |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 295 | |
| 296 | .bss : |
| 297 | { |
| 298 | . = ALIGN(4); |
| 299 | __bss_start__ = .; |
| 300 | *(.bss) |
| 301 | *(.bss.*) |
| 302 | *(COMMON) |
| 303 | . = ALIGN(4); |
| 304 | __bss_end__ = .; |
Per Åstrand | 0b7bbb4 | 2021-03-25 12:34:24 +0100 | [diff] [blame] | 305 | } > DTCM :null |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 306 | |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 307 | .heap (COPY) : |
| 308 | { |
| 309 | . = ALIGN(8); |
| 310 | __end__ = .; |
| 311 | PROVIDE(end = .); |
| 312 | . = . + __HEAP_SIZE; |
| 313 | . = ALIGN(8); |
| 314 | __HeapLimit = .; |
Per Åstrand | 0b7bbb4 | 2021-03-25 12:34:24 +0100 | [diff] [blame] | 315 | } > DTCM :null |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 316 | |
| 317 | .stack (ORIGIN(DTCM) + LENGTH(DTCM) - __STACK_SIZE) (COPY) : |
| 318 | { |
| 319 | . = ALIGN(8); |
| 320 | __StackLimit = .; |
| 321 | . = . + __STACK_SIZE; |
| 322 | . = ALIGN(8); |
| 323 | __StackTop = .; |
Per Åstrand | 0b7bbb4 | 2021-03-25 12:34:24 +0100 | [diff] [blame] | 324 | } > DTCM :null |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 325 | PROVIDE(__stack = __StackTop); |
| 326 | |
Mikael Olsson | ad5b6f2 | 2024-01-22 14:48:28 +0100 | [diff] [blame] | 327 | __RAM_segment_used_end__ = .; |
| 328 | |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 329 | /* Check if data + heap + stack exceeds DTCM limit */ |
| 330 | ASSERT(__StackLimit >= __HeapLimit, "region DTCM overflowed with stack") |
| 331 | } |