Kristofer Jonsson | f62c3d7 | 2021-01-21 17:39:03 +0100 | [diff] [blame] | 1 | /* |
Jonny Svärd | 3629310 | 2024-06-17 13:16:38 +0200 | [diff] [blame] | 2 | * SPDX-FileCopyrightText: Copyright 2020-2021, 2023-2024 Arm Limited and/or its affiliates <open-source-office@arm.com> |
Kristofer Jonsson | f62c3d7 | 2021-01-21 17:39:03 +0100 | [diff] [blame] | 3 | * SPDX-License-Identifier: Apache-2.0 |
| 4 | * |
| 5 | * Licensed under the Apache License, Version 2.0 (the License); you may |
| 6 | * not use this file except in compliance with the License. |
| 7 | * You may obtain a copy of the License at |
| 8 | * |
| 9 | * www.apache.org/licenses/LICENSE-2.0 |
| 10 | * |
| 11 | * Unless required by applicable law or agreed to in writing, software |
| 12 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT |
| 13 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 14 | * See the License for the specific language governing permissions and |
| 15 | * limitations under the License. |
| 16 | */ |
| 17 | |
| 18 | /**************************************************************************** |
| 19 | * Includes |
| 20 | ****************************************************************************/ |
| 21 | |
| 22 | #include "target.hpp" |
| 23 | |
| 24 | #ifdef ETHOSU |
| 25 | #include <ethosu_driver.h> |
Kristofer Jonsson | 7b8fa5e | 2021-12-16 14:02:56 +0100 | [diff] [blame] | 26 | #include <timing_adapter.h> |
Kristofer Jonsson | f62c3d7 | 2021-01-21 17:39:03 +0100 | [diff] [blame] | 27 | #endif |
| 28 | |
Jonny Svärd | 991af2b | 2021-04-15 17:31:01 +0200 | [diff] [blame] | 29 | #include "mpu.hpp" |
Yulia Garbovich | e9cdc63 | 2021-11-23 20:00:04 +0200 | [diff] [blame] | 30 | #include "uart_stdout.h" |
Kristofer Jonsson | f62c3d7 | 2021-01-21 17:39:03 +0100 | [diff] [blame] | 31 | |
Jonny Svärd | d667090 | 2021-03-18 15:49:27 +0100 | [diff] [blame] | 32 | #include <inttypes.h> |
Kristofer Jonsson | f62c3d7 | 2021-01-21 17:39:03 +0100 | [diff] [blame] | 33 | #include <stdio.h> |
Per Åstrand | 174e98d | 2021-02-09 17:48:53 +0100 | [diff] [blame] | 34 | #include <stdlib.h> |
Jonny Svärd | 991af2b | 2021-04-15 17:31:01 +0200 | [diff] [blame] | 35 | #include <vector> |
Kristofer Jonsson | f62c3d7 | 2021-01-21 17:39:03 +0100 | [diff] [blame] | 36 | |
| 37 | using namespace EthosU; |
| 38 | |
| 39 | /**************************************************************************** |
| 40 | * Defines |
| 41 | ****************************************************************************/ |
| 42 | |
| 43 | #define ETHOSU_BASE_ADDRESS 0x48102000 |
Jonny Svärd | d667090 | 2021-03-18 15:49:27 +0100 | [diff] [blame] | 44 | #define ETHOSU_IRQ 56 |
Jonny Svärd | 4db21c9 | 2023-05-15 11:44:05 +0200 | [diff] [blame] | 45 | #define ETHOSU_IRQ_PRIORITY 5 |
Kristofer Jonsson | f62c3d7 | 2021-01-21 17:39:03 +0100 | [diff] [blame] | 46 | |
Jonny Svärd | 3629310 | 2024-06-17 13:16:38 +0200 | [diff] [blame] | 47 | #define ETHOSU_TA0_BASE_ADDRESS 0x48103000 |
| 48 | #define ETHOSU_TA1_BASE_ADDRESS 0x48103200 |
| 49 | |
| 50 | #define ETHOSU_NUM_TA 2 |
Kristofer Jonsson | f62c3d7 | 2021-01-21 17:39:03 +0100 | [diff] [blame] | 51 | |
| 52 | /**************************************************************************** |
| 53 | * Variables |
| 54 | ****************************************************************************/ |
| 55 | |
| 56 | #if defined(ETHOSU_FAST_MEMORY_SIZE) && ETHOSU_FAST_MEMORY_SIZE > 0 |
| 57 | __attribute__((aligned(16), section(".bss.ethosu_scratch"))) uint8_t ethosu_scratch[ETHOSU_FAST_MEMORY_SIZE]; |
| 58 | #else |
| 59 | #define ethosu_scratch 0 |
| 60 | #define ETHOSU_FAST_MEMORY_SIZE 0 |
| 61 | #endif |
| 62 | |
Jonny Svärd | 991af2b | 2021-04-15 17:31:01 +0200 | [diff] [blame] | 63 | #ifdef ETHOSU |
Jonny Svärd | c5941c4 | 2021-06-01 18:40:45 +0200 | [diff] [blame] | 64 | struct ethosu_driver ethosu0_driver; |
Jonny Svärd | 991af2b | 2021-04-15 17:31:01 +0200 | [diff] [blame] | 65 | #endif |
| 66 | |
Nir Ekhauz | a58edd8 | 2021-10-04 12:21:17 +0300 | [diff] [blame] | 67 | /**************************************************************************** |
| 68 | * Timing Adapters |
| 69 | ****************************************************************************/ |
| 70 | |
Kristofer Jonsson | 7b8fa5e | 2021-12-16 14:02:56 +0100 | [diff] [blame] | 71 | #ifdef ETHOSU |
| 72 | |
Kristofer Jonsson | 64f37cd | 2021-10-19 10:54:47 +0200 | [diff] [blame] | 73 | #ifndef ETHOSU_TA_MAXR_0 |
Nir Ekhauz | a58edd8 | 2021-10-04 12:21:17 +0300 | [diff] [blame] | 74 | #define ETHOSU_TA_MAXR_0 0 |
| 75 | #endif |
Kristofer Jonsson | 64f37cd | 2021-10-19 10:54:47 +0200 | [diff] [blame] | 76 | |
| 77 | #ifndef ETHOSU_TA_MAXW_0 |
Nir Ekhauz | a58edd8 | 2021-10-04 12:21:17 +0300 | [diff] [blame] | 78 | #define ETHOSU_TA_MAXW_0 0 |
| 79 | #endif |
Kristofer Jonsson | 64f37cd | 2021-10-19 10:54:47 +0200 | [diff] [blame] | 80 | |
| 81 | #ifndef ETHOSU_TA_MAXRW_0 |
Nir Ekhauz | a58edd8 | 2021-10-04 12:21:17 +0300 | [diff] [blame] | 82 | #define ETHOSU_TA_MAXRW_0 0 |
| 83 | #endif |
Kristofer Jonsson | 64f37cd | 2021-10-19 10:54:47 +0200 | [diff] [blame] | 84 | |
| 85 | #ifndef ETHOSU_TA_RLATENCY_0 |
Nir Ekhauz | a58edd8 | 2021-10-04 12:21:17 +0300 | [diff] [blame] | 86 | #define ETHOSU_TA_RLATENCY_0 0 |
| 87 | #endif |
Kristofer Jonsson | 64f37cd | 2021-10-19 10:54:47 +0200 | [diff] [blame] | 88 | |
| 89 | #ifndef ETHOSU_TA_WLATENCY_0 |
Nir Ekhauz | a58edd8 | 2021-10-04 12:21:17 +0300 | [diff] [blame] | 90 | #define ETHOSU_TA_WLATENCY_0 0 |
| 91 | #endif |
Kristofer Jonsson | 64f37cd | 2021-10-19 10:54:47 +0200 | [diff] [blame] | 92 | |
| 93 | #ifndef ETHOSU_TA_PULSE_ON_0 |
Nir Ekhauz | a58edd8 | 2021-10-04 12:21:17 +0300 | [diff] [blame] | 94 | #define ETHOSU_TA_PULSE_ON_0 0 |
| 95 | #endif |
Kristofer Jonsson | 64f37cd | 2021-10-19 10:54:47 +0200 | [diff] [blame] | 96 | |
| 97 | #ifndef ETHOSU_TA_PULSE_OFF_0 |
Nir Ekhauz | a58edd8 | 2021-10-04 12:21:17 +0300 | [diff] [blame] | 98 | #define ETHOSU_TA_PULSE_OFF_0 0 |
| 99 | #endif |
Kristofer Jonsson | 64f37cd | 2021-10-19 10:54:47 +0200 | [diff] [blame] | 100 | |
| 101 | #ifndef ETHOSU_TA_BWCAP_0 |
Nir Ekhauz | a58edd8 | 2021-10-04 12:21:17 +0300 | [diff] [blame] | 102 | #define ETHOSU_TA_BWCAP_0 0 |
| 103 | #endif |
Kristofer Jonsson | 64f37cd | 2021-10-19 10:54:47 +0200 | [diff] [blame] | 104 | |
| 105 | #ifndef ETHOSU_TA_PERFCTRL_0 |
Nir Ekhauz | a58edd8 | 2021-10-04 12:21:17 +0300 | [diff] [blame] | 106 | #define ETHOSU_TA_PERFCTRL_0 0 |
| 107 | #endif |
Kristofer Jonsson | 64f37cd | 2021-10-19 10:54:47 +0200 | [diff] [blame] | 108 | |
| 109 | #ifndef ETHOSU_TA_PERFCNT_0 |
Nir Ekhauz | a58edd8 | 2021-10-04 12:21:17 +0300 | [diff] [blame] | 110 | #define ETHOSU_TA_PERFCNT_0 0 |
| 111 | #endif |
Kristofer Jonsson | 64f37cd | 2021-10-19 10:54:47 +0200 | [diff] [blame] | 112 | |
| 113 | #ifndef ETHOSU_TA_MODE_0 |
| 114 | #define ETHOSU_TA_MODE_0 1 |
Nir Ekhauz | a58edd8 | 2021-10-04 12:21:17 +0300 | [diff] [blame] | 115 | #endif |
Kristofer Jonsson | 64f37cd | 2021-10-19 10:54:47 +0200 | [diff] [blame] | 116 | |
| 117 | #ifndef ETHOSU_TA_HISTBIN_0 |
Nir Ekhauz | a58edd8 | 2021-10-04 12:21:17 +0300 | [diff] [blame] | 118 | #define ETHOSU_TA_HISTBIN_0 0 |
| 119 | #endif |
Kristofer Jonsson | 64f37cd | 2021-10-19 10:54:47 +0200 | [diff] [blame] | 120 | |
| 121 | #ifndef ETHOSU_TA_HISTCNT_0 |
Nir Ekhauz | a58edd8 | 2021-10-04 12:21:17 +0300 | [diff] [blame] | 122 | #define ETHOSU_TA_HISTCNT_0 0 |
| 123 | #endif |
| 124 | |
Kristofer Jonsson | 64f37cd | 2021-10-19 10:54:47 +0200 | [diff] [blame] | 125 | #ifndef ETHOSU_TA_MAXR_1 |
Nir Ekhauz | a58edd8 | 2021-10-04 12:21:17 +0300 | [diff] [blame] | 126 | #define ETHOSU_TA_MAXR_1 0 |
| 127 | #endif |
Kristofer Jonsson | 64f37cd | 2021-10-19 10:54:47 +0200 | [diff] [blame] | 128 | |
| 129 | #ifndef ETHOSU_TA_MAXW_1 |
Nir Ekhauz | a58edd8 | 2021-10-04 12:21:17 +0300 | [diff] [blame] | 130 | #define ETHOSU_TA_MAXW_1 0 |
| 131 | #endif |
Kristofer Jonsson | 64f37cd | 2021-10-19 10:54:47 +0200 | [diff] [blame] | 132 | |
| 133 | #ifndef ETHOSU_TA_MAXRW_1 |
Nir Ekhauz | a58edd8 | 2021-10-04 12:21:17 +0300 | [diff] [blame] | 134 | #define ETHOSU_TA_MAXRW_1 0 |
| 135 | #endif |
Kristofer Jonsson | 64f37cd | 2021-10-19 10:54:47 +0200 | [diff] [blame] | 136 | |
| 137 | #ifndef ETHOSU_TA_RLATENCY_1 |
Nir Ekhauz | a58edd8 | 2021-10-04 12:21:17 +0300 | [diff] [blame] | 138 | #define ETHOSU_TA_RLATENCY_1 0 |
| 139 | #endif |
Kristofer Jonsson | 64f37cd | 2021-10-19 10:54:47 +0200 | [diff] [blame] | 140 | |
| 141 | #ifndef ETHOSU_TA_WLATENCY_1 |
Nir Ekhauz | a58edd8 | 2021-10-04 12:21:17 +0300 | [diff] [blame] | 142 | #define ETHOSU_TA_WLATENCY_1 0 |
| 143 | #endif |
Kristofer Jonsson | 64f37cd | 2021-10-19 10:54:47 +0200 | [diff] [blame] | 144 | |
| 145 | #ifndef ETHOSU_TA_PULSE_ON_1 |
Nir Ekhauz | a58edd8 | 2021-10-04 12:21:17 +0300 | [diff] [blame] | 146 | #define ETHOSU_TA_PULSE_ON_1 0 |
| 147 | #endif |
Kristofer Jonsson | 64f37cd | 2021-10-19 10:54:47 +0200 | [diff] [blame] | 148 | |
| 149 | #ifndef ETHOSU_TA_PULSE_OFF_1 |
Nir Ekhauz | a58edd8 | 2021-10-04 12:21:17 +0300 | [diff] [blame] | 150 | #define ETHOSU_TA_PULSE_OFF_1 0 |
| 151 | #endif |
Kristofer Jonsson | 64f37cd | 2021-10-19 10:54:47 +0200 | [diff] [blame] | 152 | |
| 153 | #ifndef ETHOSU_TA_BWCAP_1 |
Nir Ekhauz | a58edd8 | 2021-10-04 12:21:17 +0300 | [diff] [blame] | 154 | #define ETHOSU_TA_BWCAP_1 0 |
| 155 | #endif |
Kristofer Jonsson | 64f37cd | 2021-10-19 10:54:47 +0200 | [diff] [blame] | 156 | |
| 157 | #ifndef ETHOSU_TA_PERFCTRL_1 |
Nir Ekhauz | a58edd8 | 2021-10-04 12:21:17 +0300 | [diff] [blame] | 158 | #define ETHOSU_TA_PERFCTRL_1 0 |
| 159 | #endif |
Kristofer Jonsson | 64f37cd | 2021-10-19 10:54:47 +0200 | [diff] [blame] | 160 | |
| 161 | #ifndef ETHOSU_TA_PERFCNT_1 |
Nir Ekhauz | a58edd8 | 2021-10-04 12:21:17 +0300 | [diff] [blame] | 162 | #define ETHOSU_TA_PERFCNT_1 0 |
| 163 | #endif |
Kristofer Jonsson | 64f37cd | 2021-10-19 10:54:47 +0200 | [diff] [blame] | 164 | |
| 165 | #ifndef ETHOSU_TA_MODE_1 |
| 166 | #define ETHOSU_TA_MODE_1 1 |
Nir Ekhauz | a58edd8 | 2021-10-04 12:21:17 +0300 | [diff] [blame] | 167 | #endif |
Kristofer Jonsson | 64f37cd | 2021-10-19 10:54:47 +0200 | [diff] [blame] | 168 | |
| 169 | #ifndef ETHOSU_TA_HISTBIN_1 |
Nir Ekhauz | a58edd8 | 2021-10-04 12:21:17 +0300 | [diff] [blame] | 170 | #define ETHOSU_TA_HISTBIN_1 0 |
| 171 | #endif |
Kristofer Jonsson | 64f37cd | 2021-10-19 10:54:47 +0200 | [diff] [blame] | 172 | |
| 173 | #ifndef ETHOSU_TA_HISTCNT_1 |
Nir Ekhauz | a58edd8 | 2021-10-04 12:21:17 +0300 | [diff] [blame] | 174 | #define ETHOSU_TA_HISTCNT_1 0 |
| 175 | #endif |
| 176 | |
Jonny Svärd | 3629310 | 2024-06-17 13:16:38 +0200 | [diff] [blame] | 177 | static uintptr_t ethosu_ta_base_addrs[ETHOSU_NUM_TA] = {ETHOSU_TA0_BASE_ADDRESS, ETHOSU_TA1_BASE_ADDRESS}; |
| 178 | struct timing_adapter ethosu_ta[ETHOSU_NUM_TA]; |
| 179 | struct timing_adapter_settings ethosu_ta_settings[ETHOSU_NUM_TA] = {{ETHOSU_TA_MAXR_0, |
| 180 | ETHOSU_TA_MAXW_0, |
| 181 | ETHOSU_TA_MAXRW_0, |
| 182 | ETHOSU_TA_RLATENCY_0, |
| 183 | ETHOSU_TA_WLATENCY_0, |
| 184 | ETHOSU_TA_PULSE_ON_0, |
| 185 | ETHOSU_TA_PULSE_OFF_0, |
| 186 | ETHOSU_TA_BWCAP_0, |
| 187 | ETHOSU_TA_PERFCTRL_0, |
| 188 | ETHOSU_TA_PERFCNT_0, |
| 189 | ETHOSU_TA_MODE_0, |
| 190 | 0, // Read only register |
| 191 | ETHOSU_TA_HISTBIN_0, |
| 192 | ETHOSU_TA_HISTCNT_0}, |
| 193 | {ETHOSU_TA_MAXR_1, |
| 194 | ETHOSU_TA_MAXW_1, |
| 195 | ETHOSU_TA_MAXRW_1, |
| 196 | ETHOSU_TA_RLATENCY_1, |
| 197 | ETHOSU_TA_WLATENCY_1, |
| 198 | ETHOSU_TA_PULSE_ON_1, |
| 199 | ETHOSU_TA_PULSE_OFF_1, |
| 200 | ETHOSU_TA_BWCAP_1, |
| 201 | ETHOSU_TA_PERFCTRL_1, |
| 202 | ETHOSU_TA_PERFCNT_1, |
| 203 | ETHOSU_TA_MODE_1, |
| 204 | 0, // Read only register |
| 205 | ETHOSU_TA_HISTBIN_1, |
| 206 | ETHOSU_TA_HISTCNT_1}}; |
Kristofer Jonsson | 29467e0 | 2021-11-26 16:10:43 +0100 | [diff] [blame] | 207 | |
Kristofer Jonsson | 7b8fa5e | 2021-12-16 14:02:56 +0100 | [diff] [blame] | 208 | #endif |
| 209 | |
Kristofer Jonsson | f62c3d7 | 2021-01-21 17:39:03 +0100 | [diff] [blame] | 210 | /**************************************************************************** |
| 211 | * Cache maintenance |
| 212 | ****************************************************************************/ |
| 213 | |
| 214 | #if defined(CPU_CACHE_ENABLE) && defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) |
| 215 | extern "C" { |
| 216 | void ethosu_flush_dcache(uint32_t *p, size_t bytes) { |
| 217 | if (p) |
| 218 | SCB_CleanDCache_by_Addr(p, bytes); |
| 219 | else |
| 220 | SCB_CleanDCache(); |
| 221 | } |
| 222 | |
| 223 | void ethosu_invalidate_dcache(uint32_t *p, size_t bytes) { |
| 224 | if (p) |
| 225 | SCB_InvalidateDCache_by_Addr(p, bytes); |
| 226 | else |
| 227 | SCB_InvalidateDCache(); |
| 228 | } |
| 229 | } |
| 230 | #endif |
| 231 | |
| 232 | /**************************************************************************** |
| 233 | * Init |
| 234 | ****************************************************************************/ |
| 235 | |
| 236 | namespace { |
| 237 | |
Per Åstrand | 174e98d | 2021-02-09 17:48:53 +0100 | [diff] [blame] | 238 | extern "C" { |
| 239 | struct ExcContext { |
| 240 | uint32_t r0; |
| 241 | uint32_t r1; |
| 242 | uint32_t r2; |
| 243 | uint32_t r3; |
| 244 | uint32_t r12; |
| 245 | uint32_t lr; |
| 246 | uint32_t pc; |
| 247 | uint32_t xPsr; |
| 248 | }; |
| 249 | |
| 250 | void HardFault_Handler() { |
| 251 | int irq; |
| 252 | struct ExcContext *e; |
| 253 | uint32_t sp; |
| 254 | |
Ledion Daja | 204210b | 2023-08-15 13:32:07 +0200 | [diff] [blame] | 255 | asm volatile("mrs %0, ipsr \n" // Read IPSR (Exception number) |
Per Åstrand | 174e98d | 2021-02-09 17:48:53 +0100 | [diff] [blame] | 256 | "sub %0, #16 \n" // Get it into IRQn_Type range |
| 257 | "tst lr, #4 \n" // Select the stack which was in use |
| 258 | "ite eq \n" |
| 259 | "mrseq %1, msp \n" |
| 260 | "mrsne %1, psp \n" |
| 261 | "mov %2, sp \n" |
| 262 | : "=r"(irq), "=r"(e), "=r"(sp)); |
| 263 | |
| 264 | printf("Hard fault. irq=%d, pc=0x%08" PRIx32 ", lr=0x%08" PRIx32 ", xpsr=0x%08" PRIx32 ", sp=0x%08" PRIx32 "\n", |
| 265 | irq, |
| 266 | e->pc, |
| 267 | e->lr, |
| 268 | e->xPsr, |
| 269 | sp); |
| 270 | printf( |
| 271 | "%11s cfsr=0x%08" PRIx32 " bfar=0x%08" PRIx32 " mmfar=0x%08" PRIx32 "\n", "", SCB->CFSR, SCB->BFAR, SCB->MMFAR); |
| 272 | exit(1); |
| 273 | } |
| 274 | } |
| 275 | |
Kristofer Jonsson | f62c3d7 | 2021-01-21 17:39:03 +0100 | [diff] [blame] | 276 | #ifdef ETHOSU |
| 277 | void ethosuIrqHandler() { |
Jonny Svärd | c5941c4 | 2021-06-01 18:40:45 +0200 | [diff] [blame] | 278 | ethosu_irq_handler(ðosu0_driver); |
Kristofer Jonsson | f62c3d7 | 2021-01-21 17:39:03 +0100 | [diff] [blame] | 279 | } |
| 280 | #endif |
| 281 | |
| 282 | } // namespace |
| 283 | |
| 284 | namespace EthosU { |
| 285 | |
| 286 | void targetSetup() { |
| 287 | // Initialize UART driver |
Yulia Garbovich | e9cdc63 | 2021-11-23 20:00:04 +0200 | [diff] [blame] | 288 | UartStdOutInit(); |
Kristofer Jonsson | f62c3d7 | 2021-01-21 17:39:03 +0100 | [diff] [blame] | 289 | |
Kristofer Jonsson | 7b8fa5e | 2021-12-16 14:02:56 +0100 | [diff] [blame] | 290 | #ifdef ETHOSU |
Jonny Svärd | d667090 | 2021-03-18 15:49:27 +0100 | [diff] [blame] | 291 | // Initialize timing adapter(s) |
Jonny Svärd | 3629310 | 2024-06-17 13:16:38 +0200 | [diff] [blame] | 292 | for (int i = 0; i < ETHOSU_NUM_TA; i++) { |
| 293 | if (ta_init(ðosu_ta[i], ethosu_ta_base_addrs[i])) { |
| 294 | printf("Failed to initialize M%d timing-adapter\n", i); |
| 295 | } else { |
| 296 | // Set the updated configuration |
| 297 | ta_set_all(ðosu_ta[i], ðosu_ta_settings[i]); |
Jonny Svärd | d667090 | 2021-03-18 15:49:27 +0100 | [diff] [blame] | 298 | } |
| 299 | } |
| 300 | |
Kristofer Jonsson | f62c3d7 | 2021-01-21 17:39:03 +0100 | [diff] [blame] | 301 | // Initialize Ethos-U NPU driver |
Jonny Svärd | c5941c4 | 2021-06-01 18:40:45 +0200 | [diff] [blame] | 302 | if (ethosu_init(ðosu0_driver, |
Anton Moberg | ebe9a15 | 2021-05-03 09:28:52 +0200 | [diff] [blame] | 303 | reinterpret_cast<void *>(ETHOSU_BASE_ADDRESS), |
| 304 | ethosu_scratch, |
| 305 | ETHOSU_FAST_MEMORY_SIZE, |
| 306 | 1, |
| 307 | 1)) { |
Kristofer Jonsson | f62c3d7 | 2021-01-21 17:39:03 +0100 | [diff] [blame] | 308 | printf("Failed to initialize NPU.\n"); |
| 309 | return; |
| 310 | } |
| 311 | |
Jonny Svärd | 991af2b | 2021-04-15 17:31:01 +0200 | [diff] [blame] | 312 | // Assumes SCB->VTOR point to RW memory |
Kristofer Jonsson | f62c3d7 | 2021-01-21 17:39:03 +0100 | [diff] [blame] | 313 | NVIC_SetVector(static_cast<IRQn_Type>(ETHOSU_IRQ), (uint32_t)ðosuIrqHandler); |
Jonny Svärd | 4db21c9 | 2023-05-15 11:44:05 +0200 | [diff] [blame] | 314 | NVIC_SetPriority(static_cast<IRQn_Type>(ETHOSU_IRQ), ETHOSU_IRQ_PRIORITY); |
Kristofer Jonsson | f62c3d7 | 2021-01-21 17:39:03 +0100 | [diff] [blame] | 315 | NVIC_EnableIRQ(static_cast<IRQn_Type>(ETHOSU_IRQ)); |
| 316 | #endif |
Jonny Svärd | 991af2b | 2021-04-15 17:31:01 +0200 | [diff] [blame] | 317 | |
| 318 | // MPU setup |
| 319 | const std::vector<ARM_MPU_Region_t> mpuConfig = { |
| 320 | { |
Jonny Svärd | e3b6b96 | 2021-04-27 11:32:31 +0200 | [diff] [blame] | 321 | // ITCM (NS) |
Jonny Svärd | 991af2b | 2021-04-15 17:31:01 +0200 | [diff] [blame] | 322 | ARM_MPU_RBAR(0x00000000, // Base |
| 323 | ARM_MPU_SH_NON, // Non-shareable |
| 324 | 1, // Read-Only |
| 325 | 1, // Non-Privileged |
| 326 | 0), // eXecute Never disabled |
| 327 | ARM_MPU_RLAR(0x0007ffff, // Limit |
| 328 | Mpu::WTRA_index) // Attribute index - Write-Through, Read-allocate |
| 329 | }, |
| 330 | { |
Jonny Svärd | e3b6b96 | 2021-04-27 11:32:31 +0200 | [diff] [blame] | 331 | // ITCM (S) |
Jonny Svärd | 991af2b | 2021-04-15 17:31:01 +0200 | [diff] [blame] | 332 | ARM_MPU_RBAR(0x10000000, // Base |
| 333 | ARM_MPU_SH_NON, // Non-shareable |
| 334 | 1, // Read-Only |
| 335 | 1, // Non-Privileged |
| 336 | 0), // eXecute Never disabled |
| 337 | ARM_MPU_RLAR(0x1007ffff, // Limit |
| 338 | Mpu::WTRA_index) // Attribute index - Write-Through, Read-allocate |
| 339 | }, |
| 340 | { |
Jonny Svärd | e3b6b96 | 2021-04-27 11:32:31 +0200 | [diff] [blame] | 341 | // FPGA DATA SRAM; BRAM (NS) |
| 342 | ARM_MPU_RBAR(0x01000000, // Base |
| 343 | ARM_MPU_SH_NON, // Non-shareable |
| 344 | 0, // Read-Write |
| 345 | 1, // Non-Privileged |
| 346 | 0), // eXecute Never disabled |
| 347 | ARM_MPU_RLAR(0x011fffff, // Limit |
| 348 | Mpu::WBWARA_index) // Attribute index - Write-Back, Write-Allocate, Read-allocate |
| 349 | }, |
| 350 | { |
| 351 | // FPGA DATA SRAM; BRAM (S) |
Jonny Svärd | 991af2b | 2021-04-15 17:31:01 +0200 | [diff] [blame] | 352 | ARM_MPU_RBAR(0x11000000, // Base |
| 353 | ARM_MPU_SH_NON, // Non-shareable |
| 354 | 0, // Read-Write |
| 355 | 1, // Non-Privileged |
| 356 | 0), // eXecute Never disabled |
| 357 | ARM_MPU_RLAR(0x111fffff, // Limit |
| 358 | Mpu::WBWARA_index) // Attribute index - Write-Back, Write-Allocate, Read-allocate |
| 359 | }, |
| 360 | { |
Jonny Svärd | e3b6b96 | 2021-04-27 11:32:31 +0200 | [diff] [blame] | 361 | // DTCM (NS) |
| 362 | ARM_MPU_RBAR(0x20000000, // Base |
| 363 | ARM_MPU_SH_NON, // Non-shareable |
| 364 | 0, // Read-Write |
| 365 | 1, // Non-Privileged |
| 366 | 1), // eXecute Never enabled |
| 367 | ARM_MPU_RLAR(0x2007ffff, // Limit |
| 368 | Mpu::WBWARA_index) // Attribute index - Write-Back, Write-Allocate, Read-allocate |
| 369 | }, |
| 370 | { |
| 371 | // DTCM (S) |
Jonny Svärd | 991af2b | 2021-04-15 17:31:01 +0200 | [diff] [blame] | 372 | ARM_MPU_RBAR(0x30000000, // Base |
| 373 | ARM_MPU_SH_NON, // Non-shareable |
| 374 | 0, // Read-Write |
| 375 | 1, // Non-Privileged |
| 376 | 1), // eXecute Never enabled |
| 377 | ARM_MPU_RLAR(0x3007ffff, // Limit |
| 378 | Mpu::WBWARA_index) // Attribute index - Write-Back, Write-Allocate, Read-allocate |
| 379 | }, |
| 380 | { |
Jonny Svärd | e3b6b96 | 2021-04-27 11:32:31 +0200 | [diff] [blame] | 381 | // SSE-300 internal SRAM (NS) |
| 382 | ARM_MPU_RBAR(0x21000000, // Base |
| 383 | ARM_MPU_SH_NON, // Non-shareable |
| 384 | 0, // Read-Write |
| 385 | 1, // Non-Privileged |
| 386 | 1), // eXecute Never enabled |
| 387 | ARM_MPU_RLAR(0x213fffff, // Limit |
| 388 | Mpu::WBWARA_index) // Attribute index - Write-Back, Write-Allocate, Read-allocate |
| 389 | }, |
| 390 | { |
| 391 | // SSE-300 internal SRAM (S) |
Jonny Svärd | 991af2b | 2021-04-15 17:31:01 +0200 | [diff] [blame] | 392 | ARM_MPU_RBAR(0x31000000, // Base |
| 393 | ARM_MPU_SH_NON, // Non-shareable |
| 394 | 0, // Read-Write |
| 395 | 1, // Non-Privileged |
| 396 | 1), // eXecute Never enabled |
| 397 | ARM_MPU_RLAR(0x313fffff, // Limit |
| 398 | Mpu::WBWARA_index) // Attribute index - Write-Back, Write-Allocate, Read-allocate |
| 399 | }, |
| 400 | { |
Jonny Svärd | e3b6b96 | 2021-04-27 11:32:31 +0200 | [diff] [blame] | 401 | // DDR (NS) |
| 402 | ARM_MPU_RBAR(0x60000000, // Base |
| 403 | ARM_MPU_SH_NON, // Non-shareable |
| 404 | 0, // Read-Write |
| 405 | 1, // Non-Privileged |
| 406 | 1), // eXecute Never enabled |
| 407 | ARM_MPU_RLAR(0x6fffffff, // Limit |
| 408 | Mpu::WBWARA_index) // Attribute index - Write-Back, Write-Allocate, Read-allocate |
| 409 | }, |
| 410 | { |
| 411 | // DDR (S) |
Jonny Svärd | 991af2b | 2021-04-15 17:31:01 +0200 | [diff] [blame] | 412 | ARM_MPU_RBAR(0x70000000, // Base |
| 413 | ARM_MPU_SH_NON, // Non-shareable |
| 414 | 0, // Read-Write |
| 415 | 1, // Non-Privileged |
| 416 | 1), // eXecute Never enabled |
| 417 | ARM_MPU_RLAR(0x7fffffff, // Limit |
| 418 | Mpu::WBWARA_index) // Attribute index - Write-Back, Write-Allocate, Read-allocate |
| 419 | }}; |
| 420 | |
| 421 | // Setup MPU configuration |
| 422 | Mpu::loadAndEnableConfig(&mpuConfig[0], mpuConfig.size()); |
| 423 | |
| 424 | #if defined(CPU_CACHE_ENABLE) && defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) |
| 425 | SCB_EnableICache(); |
| 426 | SCB_EnableDCache(); |
| 427 | #endif |
Kristofer Jonsson | f62c3d7 | 2021-01-21 17:39:03 +0100 | [diff] [blame] | 428 | } |
| 429 | |
| 430 | } // namespace EthosU |