Kristofer Jonsson | 9317581 | 2022-04-21 19:27:11 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2019-2022 Arm Limited. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: Apache-2.0 |
| 5 | * |
| 6 | * Licensed under the Apache License, Version 2.0 (the License); you may |
| 7 | * not use this file except in compliance with the License. |
| 8 | * You may obtain a copy of the License at |
| 9 | * |
| 10 | * www.apache.org/licenses/LICENSE-2.0 |
| 11 | * |
| 12 | * Unless required by applicable law or agreed to in writing, software |
| 13 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT |
| 14 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 15 | * See the License for the specific language governing permissions and |
| 16 | * limitations under the License. |
| 17 | */ |
| 18 | |
| 19 | /* |
| 20 | * Corstone-310 is the next generation Corstone-300 where the CPU |
| 21 | * has been upgraded to Cortex-M85. |
| 22 | * |
| 23 | * This is a simplified picture of the Corstone-310 memory system. |
| 24 | * Please refer to the Corstone SSE-310 Technical Reference Manual for |
| 25 | * further information. |
| 26 | * |
| 27 | * https://developer.arm.com/ip-products/subsystem/corstone/corstone-300 |
| 28 | * |
| 29 | * +---------------+ +---------------+ +------+ |
| 30 | * | Ethos-U55 | | Cortex-M85 +--+ ITCM | |
| 31 | * | | | | +------+ |
| 32 | * | | | | |
| 33 | * | | | | +------+ |
| 34 | * | M1 M0 | | +--+ DTCM | |
| 35 | * +---+-------+---+ +-------+-------+ +------+ |
| 36 | * | | | |
| 37 | * | +---+---------------+-----+ |
| 38 | * | | AMBA AXI NIC-400-Lite | |
| 39 | * | +---+-----------------+---+ |
| 40 | * | | | |
| 41 | * +---+-------+------------+ +--+-------+ |
| 42 | * | AMBA AXI NIC-400 | | SSE-300 | |
| 43 | * +---+--------+--------+--+ | SRAM | |
| 44 | * | | | +----------+ |
| 45 | * +---+---+ +--+---+ +--+--+ |
| 46 | * | Flash | | BRAM | | DDR | |
| 47 | * +-------+ +------+ +-----+ |
| 48 | * |
| 49 | * +-----------------------+-------------+-------------+----+--------------------------------------+ |
| 50 | * | Memory region name | Base addr | Size |IDAU| MCC load address + remarks | |
| 51 | * +-----------------------+-------------+-------------+----+--------------------------------------+ |
| 52 | * | ITCM | 0x0000_0000 | 0x0000_8000 | NS | 32 kiB | |
| 53 | * | ITCM | 0x1000_0000 | 0x0000_8000 | S | Secure alias for NS ITCM | |
| 54 | * | FPGA Data SRAM; BRAM | 0x0100_0000 | 0x0020_0000 | NS | 2 MiB | |
| 55 | * | FPGA data SRAM; BRAM | 0x1100_0000 | 0x0020_0000 | S | Secure alias for NS BRAM | |
| 56 | * | DTCM | 0x2000_0000 | 0x0000_8000 | NS | 32 kiB | |
| 57 | * | DTCM | 0x3000_0000 | 0x0000_8000 | S | Secure alias for NS DTCM | |
| 58 | * | SSE-300 internal SRAM | 0x2100_0000 | 0x0040_0000 | NS | 2 banks of 2 MiB; 3 cycles latency | |
| 59 | * | SSE-300 internal SRAM | 0x3100_0000 | 0x0040_0000 | S | Secure alias for NS internal SRAM | |
| 60 | * | DDR | 0x6000_0000 | 0x1000_0000 | NS | 256 MB bank | |
| 61 | * | DDR | 0x7000_0000 | 0x1000_0000 | S | Secure alias for NS DDR | |
| 62 | * +-----------------------+-------------+-------------+----+--------------------------------------+ |
| 63 | * |
| 64 | * Note: Ethos-U55 can access BRAM, internal SRAM and the DDR sections => activation buffers and |
| 65 | * the model should only be placed in those regions. |
| 66 | * |
| 67 | * Note: Alias regions means that secure and non-secure addresses are mapped to the same physical |
| 68 | * memory banks. |
| 69 | */ |
| 70 | |
| 71 | /* default value - '1', for DRAM */ |
| 72 | #ifndef ETHOSU_MODEL |
| 73 | #define ETHOSU_MODEL 1 |
| 74 | #endif |
| 75 | |
| 76 | /* default value - '1', for DRAM */ |
| 77 | #ifndef ETHOSU_ARENA |
| 78 | #define ETHOSU_ARENA 1 |
| 79 | #endif |
| 80 | |
| 81 | #ifndef STACK_SIZE |
| 82 | #define STACK_SIZE 0x8000 |
| 83 | #endif |
| 84 | |
| 85 | #ifndef HEAP_SIZE |
| 86 | #define HEAP_SIZE 0x10000 |
| 87 | #endif |
| 88 | |
| 89 | #define ITCM_START 0x10000000 |
| 90 | #define ITCM_SIZE 0x00008000 |
| 91 | |
| 92 | #define DTCM_START 0x30000000 |
| 93 | #define DTCM_SIZE 0x00008000 |
| 94 | |
| 95 | #define BRAM_START 0x11000000 |
| 96 | #define BRAM_SIZE 0x00200000 |
| 97 | |
| 98 | #define SRAM_START 0x31000000 |
| 99 | #define SRAM_SIZE 0x00400000 |
| 100 | |
| 101 | #define DDR_START 0x70000000 |
| 102 | #define DDR_SIZE 0x10000000 |
| 103 | |
| 104 | #if STACK_SIZE > DTCM_SIZE |
| 105 | #error Stack size larger than DTCM size |
| 106 | #endif |
| 107 | |
| 108 | /* ---------------------------------------------------------------------------- |
| 109 | Stack seal size definition |
| 110 | *----------------------------------------------------------------------------*/ |
| 111 | |
| 112 | APP_IMAGE BRAM_START BRAM_SIZE |
| 113 | { |
| 114 | rom_exec BRAM_START BRAM_SIZE |
| 115 | { |
| 116 | *.o (RESET, +First) |
| 117 | *(InRoot$$Sections) |
Davide Grohmann | a8832cc | 2022-05-06 16:35:16 +0200 | [diff] [blame] | 118 | startup_ARMCM85.o |
| 119 | system_ARMCM85.o |
Kristofer Jonsson | 9317581 | 2022-04-21 19:27:11 +0200 | [diff] [blame] | 120 | target.o |
| 121 | .ANY1 (+RO +RW +ZI) |
| 122 | } |
| 123 | |
| 124 | ARM_LIB_HEAP +0 EMPTY ALIGN 8 HEAP_SIZE {} |
| 125 | ARM_LIB_STACK DTCM_START EMPTY ALIGN 8 STACK_SIZE {} |
| 126 | } |
| 127 | |
| 128 | ; Place all SRAM and DDR execution regions in DDR. We have plenty of DDR |
| 129 | ; and can perform scatter loading from here. |
| 130 | LOAD_REGION_DDR DDR_START DDR_SIZE |
| 131 | { |
| 132 | ; Place model and its affiliates in DRAM |
| 133 | rom_dram DDR_START |
| 134 | { |
| 135 | #if (ETHOSU_MODEL == 1) |
| 136 | * (network_model_sec) |
| 137 | #endif |
| 138 | * (input_data_sec) |
| 139 | * (expected_output_data_sec) |
| 140 | * (output_data_sec) |
| 141 | } |
| 142 | |
| 143 | #if (ETHOSU_ARENA == 1) |
| 144 | ; Place tensor arena in DRAM if we have a fast memory area |
| 145 | ARENA +0 UNINIT ALIGN 16 |
| 146 | { |
| 147 | * (.bss.tensor_arena) |
| 148 | } |
| 149 | #endif |
| 150 | |
| 151 | SRAM SRAM_START ALIGN 16 SRAM_SIZE |
| 152 | { |
| 153 | #if (ETHOSU_MODEL == 0) |
| 154 | ; Place network model in SRAM |
| 155 | * (network_model_sec) |
| 156 | #endif |
| 157 | |
| 158 | #if (ETHOSU_ARENA == 0) |
| 159 | ; Place tensor arena in SRAM |
| 160 | * (.bss.tensor_arena) |
| 161 | #endif |
| 162 | |
| 163 | ; Place scratch buffer in SRAM |
| 164 | * (.bss.ethosu_scratch) |
| 165 | |
| 166 | ; SRAM data |
| 167 | * (.sram.data) |
| 168 | } |
| 169 | } |