Kristofer Jonsson | 9317581 | 2022-04-21 19:27:11 +0200 | [diff] [blame] | 1 | /* |
Jonny Svärd | 3629310 | 2024-06-17 13:16:38 +0200 | [diff] [blame] | 2 | * SPDX-FileCopyrightText: Copyright 2020-2024 Arm Limited and/or its affiliates <open-source-office@arm.com> |
Kristofer Jonsson | 9317581 | 2022-04-21 19:27:11 +0200 | [diff] [blame] | 3 | * SPDX-License-Identifier: Apache-2.0 |
| 4 | * |
| 5 | * Licensed under the Apache License, Version 2.0 (the License); you may |
| 6 | * not use this file except in compliance with the License. |
| 7 | * You may obtain a copy of the License at |
| 8 | * |
| 9 | * www.apache.org/licenses/LICENSE-2.0 |
| 10 | * |
| 11 | * Unless required by applicable law or agreed to in writing, software |
| 12 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT |
| 13 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 14 | * See the License for the specific language governing permissions and |
| 15 | * limitations under the License. |
| 16 | */ |
| 17 | |
| 18 | /**************************************************************************** |
| 19 | * Includes |
| 20 | ****************************************************************************/ |
| 21 | |
| 22 | #include "target.hpp" |
| 23 | |
| 24 | #ifdef ETHOSU |
| 25 | #include <ethosu_driver.h> |
Kristofer Jonsson | 9317581 | 2022-04-21 19:27:11 +0200 | [diff] [blame] | 26 | #endif |
| 27 | |
| 28 | #include "mpu.hpp" |
| 29 | #include "uart_stdout.h" |
| 30 | |
| 31 | #include <inttypes.h> |
| 32 | #include <stdio.h> |
| 33 | #include <stdlib.h> |
| 34 | #include <vector> |
| 35 | |
| 36 | using namespace EthosU; |
| 37 | |
| 38 | /**************************************************************************** |
| 39 | * Defines |
| 40 | ****************************************************************************/ |
| 41 | |
| 42 | #define ETHOSU_BASE_ADDRESS 0x50004000 |
| 43 | #define ETHOSU_IRQ 16 |
Jonny Svärd | 4db21c9 | 2023-05-15 11:44:05 +0200 | [diff] [blame] | 44 | #define ETHOSU_IRQ_PRIORITY 5 |
Kristofer Jonsson | 9317581 | 2022-04-21 19:27:11 +0200 | [diff] [blame] | 45 | |
Kristofer Jonsson | 9317581 | 2022-04-21 19:27:11 +0200 | [diff] [blame] | 46 | /**************************************************************************** |
| 47 | * Variables |
| 48 | ****************************************************************************/ |
| 49 | |
| 50 | #if defined(ETHOSU_FAST_MEMORY_SIZE) && ETHOSU_FAST_MEMORY_SIZE > 0 |
| 51 | __attribute__((aligned(16), section(".bss.ethosu_scratch"))) uint8_t ethosu_scratch[ETHOSU_FAST_MEMORY_SIZE]; |
| 52 | #else |
| 53 | #define ethosu_scratch 0 |
| 54 | #define ETHOSU_FAST_MEMORY_SIZE 0 |
| 55 | #endif |
| 56 | |
| 57 | #ifdef ETHOSU |
| 58 | struct ethosu_driver ethosu0_driver; |
| 59 | #endif |
| 60 | |
| 61 | /**************************************************************************** |
Kristofer Jonsson | 9317581 | 2022-04-21 19:27:11 +0200 | [diff] [blame] | 62 | * Cache maintenance |
| 63 | ****************************************************************************/ |
| 64 | |
| 65 | #if defined(CPU_CACHE_ENABLE) && defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) |
| 66 | extern "C" { |
| 67 | void ethosu_flush_dcache(uint32_t *p, size_t bytes) { |
| 68 | if (p) |
| 69 | SCB_CleanDCache_by_Addr(p, bytes); |
| 70 | else |
| 71 | SCB_CleanDCache(); |
| 72 | } |
| 73 | |
| 74 | void ethosu_invalidate_dcache(uint32_t *p, size_t bytes) { |
| 75 | if (p) |
| 76 | SCB_InvalidateDCache_by_Addr(p, bytes); |
| 77 | else |
| 78 | SCB_InvalidateDCache(); |
| 79 | } |
| 80 | } |
| 81 | #endif |
| 82 | |
| 83 | /**************************************************************************** |
| 84 | * Init |
| 85 | ****************************************************************************/ |
| 86 | |
| 87 | namespace { |
| 88 | |
| 89 | extern "C" { |
| 90 | struct ExcContext { |
| 91 | uint32_t r0; |
| 92 | uint32_t r1; |
| 93 | uint32_t r2; |
| 94 | uint32_t r3; |
| 95 | uint32_t r12; |
| 96 | uint32_t lr; |
| 97 | uint32_t pc; |
| 98 | uint32_t xPsr; |
| 99 | }; |
| 100 | |
| 101 | void HardFault_Handler() { |
| 102 | int irq; |
| 103 | struct ExcContext *e; |
| 104 | uint32_t sp; |
| 105 | |
Ledion Daja | 204210b | 2023-08-15 13:32:07 +0200 | [diff] [blame] | 106 | asm volatile("mrs %0, ipsr \n" // Read IPSR (Exception number) |
Kristofer Jonsson | 9317581 | 2022-04-21 19:27:11 +0200 | [diff] [blame] | 107 | "sub %0, #16 \n" // Get it into IRQn_Type range |
| 108 | "tst lr, #4 \n" // Select the stack which was in use |
| 109 | "ite eq \n" |
| 110 | "mrseq %1, msp \n" |
| 111 | "mrsne %1, psp \n" |
| 112 | "mov %2, sp \n" |
| 113 | : "=r"(irq), "=r"(e), "=r"(sp)); |
| 114 | |
| 115 | printf("Hard fault. irq=%d, pc=0x%08" PRIx32 ", lr=0x%08" PRIx32 ", xpsr=0x%08" PRIx32 ", sp=0x%08" PRIx32 "\n", |
| 116 | irq, |
| 117 | e->pc, |
| 118 | e->lr, |
| 119 | e->xPsr, |
| 120 | sp); |
| 121 | printf( |
| 122 | "%11s cfsr=0x%08" PRIx32 " bfar=0x%08" PRIx32 " mmfar=0x%08" PRIx32 "\n", "", SCB->CFSR, SCB->BFAR, SCB->MMFAR); |
| 123 | exit(1); |
| 124 | } |
| 125 | } |
| 126 | |
| 127 | #ifdef ETHOSU |
| 128 | void ethosuIrqHandler() { |
| 129 | ethosu_irq_handler(ðosu0_driver); |
| 130 | } |
| 131 | #endif |
| 132 | |
| 133 | } // namespace |
| 134 | |
| 135 | namespace EthosU { |
| 136 | |
| 137 | void targetSetup() { |
| 138 | // Initialize UART driver |
| 139 | UartStdOutInit(); |
| 140 | |
| 141 | #ifdef ETHOSU |
Kristofer Jonsson | 9317581 | 2022-04-21 19:27:11 +0200 | [diff] [blame] | 142 | // Initialize Ethos-U NPU driver |
| 143 | if (ethosu_init(ðosu0_driver, |
| 144 | reinterpret_cast<void *>(ETHOSU_BASE_ADDRESS), |
| 145 | ethosu_scratch, |
| 146 | ETHOSU_FAST_MEMORY_SIZE, |
| 147 | 1, |
| 148 | 1)) { |
| 149 | printf("Failed to initialize NPU.\n"); |
| 150 | return; |
| 151 | } |
| 152 | |
| 153 | // Assumes SCB->VTOR point to RW memory |
| 154 | NVIC_SetVector(static_cast<IRQn_Type>(ETHOSU_IRQ), (uint32_t)ðosuIrqHandler); |
Jonny Svärd | 4db21c9 | 2023-05-15 11:44:05 +0200 | [diff] [blame] | 155 | NVIC_SetPriority(static_cast<IRQn_Type>(ETHOSU_IRQ), ETHOSU_IRQ_PRIORITY); |
Kristofer Jonsson | 9317581 | 2022-04-21 19:27:11 +0200 | [diff] [blame] | 156 | NVIC_EnableIRQ(static_cast<IRQn_Type>(ETHOSU_IRQ)); |
| 157 | #endif |
| 158 | |
| 159 | // MPU setup |
| 160 | const std::vector<ARM_MPU_Region_t> mpuConfig = { |
| 161 | { |
| 162 | // ITCM (NS) |
| 163 | ARM_MPU_RBAR(0x00000000, // Base |
| 164 | ARM_MPU_SH_NON, // Non-shareable |
| 165 | 1, // Read-Only |
| 166 | 1, // Non-Privileged |
| 167 | 0), // eXecute Never disabled |
| 168 | ARM_MPU_RLAR(0x00007fff, // Limit |
| 169 | Mpu::WTRA_index) // Attribute index - Write-Through, Read-allocate |
| 170 | }, |
| 171 | { |
| 172 | // ITCM (S) |
| 173 | ARM_MPU_RBAR(0x10000000, // Base |
| 174 | ARM_MPU_SH_NON, // Non-shareable |
| 175 | 1, // Read-Only |
| 176 | 1, // Non-Privileged |
| 177 | 0), // eXecute Never disabled |
| 178 | ARM_MPU_RLAR(0x10007fff, // Limit |
| 179 | Mpu::WTRA_index) // Attribute index - Write-Through, Read-allocate |
| 180 | }, |
| 181 | { |
| 182 | // DTCM (NS) |
| 183 | ARM_MPU_RBAR(0x20000000, // Base |
| 184 | ARM_MPU_SH_NON, // Non-shareable |
| 185 | 0, // Read-Write |
| 186 | 1, // Non-Privileged |
| 187 | 1), // eXecute Never enabled |
| 188 | ARM_MPU_RLAR(0x20007fff, // Limit |
| 189 | Mpu::WBWARA_index) // Attribute index - Write-Back, Write-Allocate, Read-allocate |
| 190 | }, |
| 191 | { |
| 192 | // DTCM (S) |
| 193 | ARM_MPU_RBAR(0x30000000, // Base |
| 194 | ARM_MPU_SH_NON, // Non-shareable |
| 195 | 0, // Read-Write |
| 196 | 1, // Non-Privileged |
| 197 | 1), // eXecute Never enabled |
| 198 | ARM_MPU_RLAR(0x30007fff, // Limit |
| 199 | Mpu::WBWARA_index) // Attribute index - Write-Back, Write-Allocate, Read-allocate |
| 200 | }, |
| 201 | { |
| 202 | // FPGA DATA SRAM; BRAM (NS) |
| 203 | ARM_MPU_RBAR(0x01000000, // Base |
| 204 | ARM_MPU_SH_NON, // Non-shareable |
| 205 | 0, // Read-Write |
| 206 | 1, // Non-Privileged |
| 207 | 0), // eXecute Never disabled |
| 208 | ARM_MPU_RLAR(0x011fffff, // Limit |
| 209 | Mpu::WBWARA_index) // Attribute index - Write-Back, Write-Allocate, Read-allocate |
| 210 | }, |
| 211 | { |
| 212 | // FPGA DATA SRAM; BRAM (S) |
| 213 | ARM_MPU_RBAR(0x11000000, // Base |
| 214 | ARM_MPU_SH_NON, // Non-shareable |
| 215 | 0, // Read-Write |
| 216 | 1, // Non-Privileged |
| 217 | 0), // eXecute Never disabled |
| 218 | ARM_MPU_RLAR(0x111fffff, // Limit |
| 219 | Mpu::WBWARA_index) // Attribute index - Write-Back, Write-Allocate, Read-allocate |
| 220 | }, |
| 221 | { |
| 222 | // SSE-300 internal SRAM (NS) |
| 223 | ARM_MPU_RBAR(0x21000000, // Base |
| 224 | ARM_MPU_SH_NON, // Non-shareable |
| 225 | 0, // Read-Write |
| 226 | 1, // Non-Privileged |
| 227 | 0), // eXecute Never disabled |
| 228 | ARM_MPU_RLAR(0x213fffff, // Limit |
Kristofer Jonsson | 01c32d4 | 2022-10-18 11:34:23 +0200 | [diff] [blame] | 229 | Mpu::WTWARA_index) // Attribute index - Write-Through, Write-Allocate, Read-allocate |
Kristofer Jonsson | 9317581 | 2022-04-21 19:27:11 +0200 | [diff] [blame] | 230 | }, |
| 231 | { |
| 232 | // SSE-300 internal SRAM (S) |
| 233 | ARM_MPU_RBAR(0x31000000, // Base |
| 234 | ARM_MPU_SH_NON, // Non-shareable |
| 235 | 0, // Read-Write |
| 236 | 1, // Non-Privileged |
| 237 | 0), // eXecute Never disabled |
| 238 | ARM_MPU_RLAR(0x313fffff, // Limit |
Kristofer Jonsson | 01c32d4 | 2022-10-18 11:34:23 +0200 | [diff] [blame] | 239 | Mpu::WTWARA_index) // Attribute index - Write-Through, Write-Allocate, Read-allocate |
Kristofer Jonsson | 9317581 | 2022-04-21 19:27:11 +0200 | [diff] [blame] | 240 | }, |
| 241 | { |
| 242 | // DDR (NS) |
| 243 | ARM_MPU_RBAR(0x60000000, // Base |
| 244 | ARM_MPU_SH_NON, // Non-shareable |
| 245 | 0, // Read-Write |
| 246 | 1, // Non-Privileged |
| 247 | 1), // eXecute Never enabled |
| 248 | ARM_MPU_RLAR(0x6fffffff, // Limit |
| 249 | Mpu::WBWARA_index) // Attribute index - Write-Back, Write-Allocate, Read-allocate |
| 250 | }, |
| 251 | { |
| 252 | // DDR (S) |
| 253 | ARM_MPU_RBAR(0x70000000, // Base |
| 254 | ARM_MPU_SH_NON, // Non-shareable |
| 255 | 0, // Read-Write |
| 256 | 1, // Non-Privileged |
| 257 | 1), // eXecute Never enabled |
| 258 | ARM_MPU_RLAR(0x7fffffff, // Limit |
| 259 | Mpu::WBWARA_index) // Attribute index - Write-Back, Write-Allocate, Read-allocate |
| 260 | }}; |
| 261 | |
| 262 | // Setup MPU configuration |
| 263 | Mpu::loadAndEnableConfig(&mpuConfig[0], mpuConfig.size()); |
| 264 | |
| 265 | #if defined(CPU_CACHE_ENABLE) && defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) |
| 266 | SCB_EnableICache(); |
| 267 | SCB_EnableDCache(); |
| 268 | #endif |
| 269 | } |
| 270 | |
| 271 | } // namespace EthosU |