Anton Moberg | 908a07c | 2021-04-08 09:50:57 +0200 | [diff] [blame] | 1 | /**************************************************************************** |
Per Åstrand | 79929ff | 2021-01-26 14:42:43 +0100 | [diff] [blame] | 2 | * @file partition_ARMCM55.h |
| 3 | * @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for Armv8.1-M Mainline |
| 4 | * @version V1.0.0 |
| 5 | * @date 20. March 2020 |
| 6 | ******************************************************************************/ |
| 7 | /* |
| 8 | * Copyright (c) 2020-2021 Arm Limited. All rights reserved. |
| 9 | * |
| 10 | * SPDX-License-Identifier: Apache-2.0 |
| 11 | * |
| 12 | * Licensed under the Apache License, Version 2.0 (the License); you may |
| 13 | * not use this file except in compliance with the License. |
| 14 | * You may obtain a copy of the License at |
| 15 | * |
| 16 | * www.apache.org/licenses/LICENSE-2.0 |
| 17 | * |
| 18 | * Unless required by applicable law or agreed to in writing, software |
| 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT |
| 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 21 | * See the License for the specific language governing permissions and |
| 22 | * limitations under the License. |
| 23 | */ |
| 24 | |
| 25 | #ifndef PARTITION_ARMCM55_H |
| 26 | #define PARTITION_ARMCM55_H |
| 27 | |
| 28 | #include "trustzone.h" |
| 29 | |
| 30 | #define SAU_INIT_CTRL 0 |
| 31 | #define SAU_INIT_CTRL_ENABLE 1 |
| 32 | #define SAU_INIT_CTRL_ALLNS 0 |
| 33 | |
| 34 | #define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ |
| 35 | |
| 36 | #define SAU_INIT_REGION0 1 |
| 37 | #define SAU_INIT_START0 TZ_S_ITCM_START /* start address of SAU region 0 */ |
| 38 | #define SAU_INIT_END0 (TZ_S_ITCM_START + TZ_S_ITCM_SIZE - 1) /* end address of SAU region 0 */ |
| 39 | #define SAU_INIT_NSC0 1 |
| 40 | |
| 41 | #define SAU_INIT_REGION1 1 |
| 42 | #define SAU_INIT_START1 (TZ_NS_ITCM_START) |
| 43 | #define SAU_INIT_END1 (TZ_NS_ITCM_START + TZ_NS_ITCM_SIZE - 1) |
| 44 | #define SAU_INIT_NSC1 0 |
| 45 | |
| 46 | #define SAU_INIT_REGION2 1 |
| 47 | #define SAU_INIT_START2 (TZ_S_SRAM_START) |
| 48 | #define SAU_INIT_END2 (TZ_S_SRAM_START + TZ_S_SRAM_SIZE - 1) |
| 49 | #define SAU_INIT_NSC2 1 |
| 50 | |
| 51 | #define SAU_INIT_REGION3 1 |
| 52 | #define SAU_INIT_START3 (TZ_NS_SRAM_START) |
| 53 | #define SAU_INIT_END3 (TZ_NS_SRAM_START + TZ_NS_SRAM_SIZE - 1) |
| 54 | #define SAU_INIT_NSC3 0 |
| 55 | |
| 56 | #define SAU_INIT_REGION4 1 |
| 57 | #define SAU_INIT_START4 TZ_S_DTCM_START /* start address of SAU region 4 */ |
| 58 | #define SAU_INIT_END4 (TZ_S_DTCM_START + TZ_S_DTCM_SIZE - 1) /* end address of SAU region 4 */ |
| 59 | #define SAU_INIT_NSC4 1 |
| 60 | |
| 61 | #define SAU_INIT_REGION5 1 |
| 62 | #define SAU_INIT_START5 (TZ_NS_DTCM_START) |
| 63 | #define SAU_INIT_END5 (TZ_NS_DTCM_START + TZ_NS_DTCM_SIZE - 1) |
| 64 | #define SAU_INIT_NSC5 0 |
| 65 | |
| 66 | #define SAU_INIT_REGION6 1 |
| 67 | #define SAU_INIT_START6 (TZ_NSC_START) |
| 68 | #define SAU_INIT_END6 (TZ_NSC_START + TZ_NSC_SIZE - 1) |
| 69 | #define SAU_INIT_NSC6 1 |
| 70 | |
| 71 | /* |
| 72 | // <e>Setup behaviour of Sleep and Exception Handling |
| 73 | */ |
| 74 | #define SCB_CSR_AIRCR_INIT 1 |
| 75 | |
| 76 | /* |
| 77 | // <o> Deep Sleep can be enabled by |
| 78 | // <0=>Secure and Non-Secure state |
| 79 | // <1=>Secure state only |
| 80 | // <i> Value for SCB->CSR register bit DEEPSLEEPS |
| 81 | */ |
| 82 | #define SCB_CSR_DEEPSLEEPS_VAL 1 |
| 83 | |
| 84 | /* |
| 85 | // <o>System reset request accessible from |
| 86 | // <0=> Secure and Non-Secure state |
| 87 | // <1=> Secure state only |
| 88 | // <i> Value for SCB->AIRCR register bit SYSRESETREQS |
| 89 | */ |
| 90 | #define SCB_AIRCR_SYSRESETREQS_VAL 0 |
| 91 | |
| 92 | /* |
| 93 | // <o>Priority of Non-Secure exceptions is |
| 94 | // <0=> Not altered |
| 95 | // <1=> Lowered to 0x80-0xFF |
| 96 | // <i> Value for SCB->AIRCR register bit PRIS |
| 97 | */ |
| 98 | #define SCB_AIRCR_PRIS_VAL 1 |
| 99 | |
| 100 | /* |
| 101 | // <o>BusFault, HardFault, and NMI target |
| 102 | // <0=> Secure state |
| 103 | // <1=> Non-Secure state |
| 104 | // <i> Value for SCB->AIRCR register bit BFHFNMINS |
| 105 | */ |
| 106 | #define SCB_AIRCR_BFHFNMINS_VAL 0 |
| 107 | |
| 108 | /* |
| 109 | // </e> |
| 110 | */ |
| 111 | |
| 112 | /* |
| 113 | // <e>Setup behaviour of Floating Point and Vector Unit (FPU/MVE) |
| 114 | */ |
| 115 | #define TZ_FPU_NS_USAGE 1 |
| 116 | |
| 117 | /* |
| 118 | // <o>Floating Point and Vector Unit usage |
| 119 | // <0=> Secure state only |
| 120 | // <3=> Secure and Non-Secure state |
| 121 | // <i> Value for SCB->NSACR register bits CP10, CP11 |
| 122 | */ |
| 123 | #define SCB_NSACR_CP10_11_VAL 3 |
| 124 | |
| 125 | /* |
| 126 | // <o>Treat floating-point registers as Secure |
| 127 | // <0=> Disabled |
| 128 | // <1=> Enabled |
| 129 | // <i> Value for FPU->FPCCR register bit TS |
| 130 | */ |
| 131 | #define FPU_FPCCR_TS_VAL 0 |
| 132 | |
| 133 | /* |
| 134 | // <o>Clear on return (CLRONRET) accessibility |
| 135 | // <0=> Secure and Non-Secure state |
| 136 | // <1=> Secure state only |
| 137 | // <i> Value for FPU->FPCCR register bit CLRONRETS |
| 138 | */ |
| 139 | #define FPU_FPCCR_CLRONRETS_VAL 0 |
| 140 | |
| 141 | /* |
| 142 | // <o>Clear floating-point caller saved registers on exception return |
| 143 | // <0=> Disabled |
| 144 | // <1=> Enabled |
| 145 | // <i> Value for FPU->FPCCR register bit CLRONRET |
| 146 | */ |
| 147 | #define FPU_FPCCR_CLRONRET_VAL 1 |
| 148 | |
| 149 | /* |
| 150 | // </e> |
| 151 | */ |
| 152 | |
| 153 | /* |
| 154 | // <h>Setup Interrupt Target |
| 155 | */ |
| 156 | |
| 157 | /* |
| 158 | // <e>Initialize ITNS 0 (Interrupts 0..31) |
| 159 | */ |
| 160 | #define NVIC_INIT_ITNS0 1 |
| 161 | #define NVIC_INIT_ITNS0_VAL 0x00000000 |
| 162 | |
| 163 | /* |
| 164 | // <e>Initialize ITNS 1 (Interrupts 32..63) |
| 165 | */ |
| 166 | #define NVIC_INIT_ITNS1 1 |
| 167 | #define NVIC_INIT_ITNS1_VAL 0x00000000 // 0x01000000 |
| 168 | |
| 169 | /* |
| 170 | // <e>Initialize ITNS 2 (Interrupts 64..95) |
| 171 | */ |
| 172 | #define NVIC_INIT_ITNS2 1 |
| 173 | #define NVIC_INIT_ITNS2_VAL 0x00000000 |
| 174 | /* |
| 175 | // <e>Initialize ITNS 3 (Interrupts 96..127) |
| 176 | */ |
| 177 | #define NVIC_INIT_ITNS3 0 |
| 178 | #define NVIC_INIT_ITNS3_VAL 0x00000000 |
| 179 | /* |
| 180 | // <e>Initialize ITNS 4 (Interrupts 128..159) |
| 181 | */ |
| 182 | #define NVIC_INIT_ITNS4 0 |
| 183 | #define NVIC_INIT_ITNS4_VAL 0x00000000 |
| 184 | /* |
| 185 | // <e>Initialize ITNS 5 (Interrupts 160..191) |
| 186 | */ |
| 187 | #define NVIC_INIT_ITNS5 0 |
| 188 | #define NVIC_INIT_ITNS5_VAL 0x00000000 |
| 189 | /* |
| 190 | // <e>Initialize ITNS 6 (Interrupts 192..223) |
| 191 | */ |
| 192 | #define NVIC_INIT_ITNS6 0 |
| 193 | #define NVIC_INIT_ITNS6_VAL 0x00000000 |
| 194 | |
| 195 | /* |
| 196 | // <e>Initialize ITNS 7 (Interrupts 224..255) |
| 197 | */ |
| 198 | #define NVIC_INIT_ITNS7 0 |
| 199 | #define NVIC_INIT_ITNS7_VAL 0x00000000 |
| 200 | /* |
| 201 | // <e>Initialize ITNS 8 (Interrupts 256..287) |
| 202 | */ |
| 203 | #define NVIC_INIT_ITNS8 0 |
| 204 | #define NVIC_INIT_ITNS8_VAL 0x00000000 |
| 205 | /* |
| 206 | // <e>Initialize ITNS 9 (Interrupts 288..319) |
| 207 | */ |
| 208 | #define NVIC_INIT_ITNS9 0 |
| 209 | #define NVIC_INIT_ITNS9_VAL 0x00000000 |
| 210 | /* |
| 211 | // <e>Initialize ITNS 10 (Interrupts 320..351) |
| 212 | */ |
| 213 | #define NVIC_INIT_ITNS10 0 |
| 214 | #define NVIC_INIT_ITNS10_VAL 0x00000000 |
| 215 | /* |
| 216 | // <e>Initialize ITNS 11 (Interrupts 352..383) |
| 217 | */ |
| 218 | #define NVIC_INIT_ITNS11 0 |
| 219 | #define NVIC_INIT_ITNS11_VAL 0x00000000 |
| 220 | /* |
| 221 | // <e>Initialize ITNS 12 (Interrupts 384..415) |
| 222 | */ |
| 223 | #define NVIC_INIT_ITNS12 0 |
| 224 | #define NVIC_INIT_ITNS12_VAL 0x00000000 |
| 225 | /* |
| 226 | // <e>Initialize ITNS 13 (Interrupts 416..447) |
| 227 | */ |
| 228 | #define NVIC_INIT_ITNS13 0 |
| 229 | #define NVIC_INIT_ITNS13_VAL 0x00000000 |
| 230 | /* |
| 231 | // <e>Initialize ITNS 14 (Interrupts 448..479) |
| 232 | */ |
| 233 | #define NVIC_INIT_ITNS14 0 |
| 234 | #define NVIC_INIT_ITNS14_VAL 0x00000000 |
| 235 | /* |
| 236 | // <e>Initialize ITNS 15 (Interrupts 480..511) |
| 237 | */ |
| 238 | #define NVIC_INIT_ITNS15 0 |
| 239 | #define NVIC_INIT_ITNS15_VAL 0x00000000 |
| 240 | |
| 241 | /* |
| 242 | max 128 SAU regions. |
| 243 | SAU regions are defined in partition.h |
| 244 | */ |
| 245 | |
| 246 | #define SAU_INIT_REGION(n) \ |
| 247 | SAU->RNR = (n & SAU_RNR_REGION_Msk); \ |
| 248 | SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ |
| 249 | SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U |
| 250 | |
| 251 | /** |
| 252 | \brief Setup a SAU Region |
| 253 | \details Writes the region information contained in SAU_Region to the |
| 254 | registers SAU_RNR, SAU_RBAR, and SAU_RLAR |
| 255 | */ |
| 256 | __STATIC_INLINE void TZ_SAU_Setup(void) { |
| 257 | |
| 258 | #if defined(__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) |
| 259 | |
| 260 | #if defined(SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) |
| 261 | SAU_INIT_REGION(0); |
| 262 | #endif |
| 263 | |
| 264 | #if defined(SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) |
| 265 | SAU_INIT_REGION(1); |
| 266 | #endif |
| 267 | |
| 268 | #if defined(SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) |
| 269 | SAU_INIT_REGION(2); |
| 270 | #endif |
| 271 | |
| 272 | #if defined(SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) |
| 273 | SAU_INIT_REGION(3); |
| 274 | #endif |
| 275 | |
| 276 | #if defined(SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) |
| 277 | SAU_INIT_REGION(4); |
| 278 | #endif |
| 279 | |
| 280 | #if defined(SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) |
| 281 | SAU_INIT_REGION(5); |
| 282 | #endif |
| 283 | |
| 284 | #if defined(SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) |
| 285 | SAU_INIT_REGION(6); |
| 286 | #endif |
| 287 | |
| 288 | #if defined(SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) |
| 289 | SAU_INIT_REGION(7); |
| 290 | #endif |
| 291 | |
| 292 | /* repeat this for all possible SAU regions */ |
| 293 | |
| 294 | #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ |
| 295 | |
| 296 | #if defined(SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) |
| 297 | SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | |
| 298 | ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk); |
| 299 | #endif |
| 300 | |
| 301 | #if defined(SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) |
| 302 | SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk)) | |
| 303 | ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); |
| 304 | |
| 305 | SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | SCB_AIRCR_BFHFNMINS_Msk | |
| 306 | SCB_AIRCR_PRIS_Msk)) | |
| 307 | ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | |
| 308 | ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | |
| 309 | ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | |
| 310 | ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); |
| 311 | #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ |
| 312 | |
| 313 | #if (((defined(__FPU_USED) && (__FPU_USED == 1U)) || (defined(__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0))) && \ |
| 314 | (defined(TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U))) |
| 315 | |
| 316 | SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | |
| 317 | ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); |
| 318 | |
| 319 | FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | |
| 320 | ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos) & FPU_FPCCR_TS_Msk) | |
| 321 | ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | |
| 322 | ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos) & FPU_FPCCR_CLRONRET_Msk); |
| 323 | #endif |
| 324 | #if defined(NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) |
| 325 | NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; |
| 326 | #endif |
| 327 | |
| 328 | #if defined(NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) |
| 329 | NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; |
| 330 | #endif |
| 331 | |
| 332 | #if defined(NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) |
| 333 | NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; |
| 334 | #endif |
| 335 | |
| 336 | #if defined(NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) |
| 337 | NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; |
| 338 | #endif |
| 339 | |
| 340 | #if defined(NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) |
| 341 | NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; |
| 342 | #endif |
| 343 | |
| 344 | #if defined(NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U) |
| 345 | NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL; |
| 346 | #endif |
| 347 | |
| 348 | #if defined(NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U) |
| 349 | NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL; |
| 350 | #endif |
| 351 | |
| 352 | #if defined(NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U) |
| 353 | NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL; |
| 354 | #endif |
| 355 | |
| 356 | #if defined(NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U) |
| 357 | NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL; |
| 358 | #endif |
| 359 | |
| 360 | #if defined(NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U) |
| 361 | NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL; |
| 362 | #endif |
| 363 | |
| 364 | #if defined(NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U) |
| 365 | NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL; |
| 366 | #endif |
| 367 | |
| 368 | #if defined(NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U) |
| 369 | NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL; |
| 370 | #endif |
| 371 | |
| 372 | #if defined(NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U) |
| 373 | NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL; |
| 374 | #endif |
| 375 | |
| 376 | #if defined(NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U) |
| 377 | NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL; |
| 378 | #endif |
| 379 | |
| 380 | #if defined(NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U) |
| 381 | NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL; |
| 382 | #endif |
| 383 | |
| 384 | #if defined(NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U) |
| 385 | NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL; |
| 386 | #endif |
| 387 | /* repeat this for all possible ITNS elements */ |
| 388 | } |
| 389 | |
| 390 | #endif /* PARTITION_ARMCM55_H */ |