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review.mlplatform.org / ml / ethos-u / ethos-u-core-platform / refs/tags/22.02-rc1 / . / targets / corstone-polaris / target.cpp
blob: f925b7557b81e021b30b1070f1a23e2b14804804 [file] [log] [blame]
Kristofer Jonsson6e9fdc02022-01-14 16:38:17 +0100[diff] [blame]1/*
2 * Copyright (c) 2020-2022 Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Licensed under the Apache License, Version 2.0 (the License); you may
7 * not use this file except in compliance with the License.
8 * You may obtain a copy of the License at
9 *
10 * www.apache.org/licenses/LICENSE-2.0
11 *
12 * Unless required by applicable law or agreed to in writing, software
13 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
14 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15 * See the License for the specific language governing permissions and
16 * limitations under the License.
17 */
18
19/****************************************************************************
20 * Includes
21 ****************************************************************************/
22
23#include "target.hpp"
24
25#ifdef ETHOSU
26#include <ethosu_driver.h>
27#include <timing_adapter.h>
28#endif
29
30#include "mpu.hpp"
31#include "uart_stdout.h"
32
33#include <inttypes.h>
34#include <stdio.h>
35#include <stdlib.h>
36#include <vector>
37
38using namespace EthosU;
39
40/****************************************************************************
41 * Defines
42 ****************************************************************************/
43
44#define ETHOSU_BASE_ADDRESS 0x40004000
45#define ETHOSU_IRQ 16
46
47#define ETHOSU0_TA0_BASE_ADDRESS 0x48103000
48#define ETHOSU0_TA1_BASE_ADDRESS 0x48103200
49
50/****************************************************************************
51 * Variables
52 ****************************************************************************/
53
54#if defined(ETHOSU_FAST_MEMORY_SIZE) && ETHOSU_FAST_MEMORY_SIZE > 0
55__attribute__((aligned(16), section(".bss.ethosu_scratch"))) uint8_t ethosu_scratch[ETHOSU_FAST_MEMORY_SIZE];
56#else
57#define ethosu_scratch 0
58#define ETHOSU_FAST_MEMORY_SIZE 0
59#endif
60
61#ifdef ETHOSU
62struct ethosu_driver ethosu0_driver;
63#endif
64
65/****************************************************************************
66 * Timing Adapters
67 ****************************************************************************/
68
69#ifdef ETHOSU
70
71#ifndef ETHOSU_TA_MAXR_0
72#define ETHOSU_TA_MAXR_0 0
73#endif
74
75#ifndef ETHOSU_TA_MAXW_0
76#define ETHOSU_TA_MAXW_0 0
77#endif
78
79#ifndef ETHOSU_TA_MAXRW_0
80#define ETHOSU_TA_MAXRW_0 0
81#endif
82
83#ifndef ETHOSU_TA_RLATENCY_0
84#define ETHOSU_TA_RLATENCY_0 0
85#endif
86
87#ifndef ETHOSU_TA_WLATENCY_0
88#define ETHOSU_TA_WLATENCY_0 0
89#endif
90
91#ifndef ETHOSU_TA_PULSE_ON_0
92#define ETHOSU_TA_PULSE_ON_0 0
93#endif
94
95#ifndef ETHOSU_TA_PULSE_OFF_0
96#define ETHOSU_TA_PULSE_OFF_0 0
97#endif
98
99#ifndef ETHOSU_TA_BWCAP_0
100#define ETHOSU_TA_BWCAP_0 0
101#endif
102
103#ifndef ETHOSU_TA_PERFCTRL_0
104#define ETHOSU_TA_PERFCTRL_0 0
105#endif
106
107#ifndef ETHOSU_TA_PERFCNT_0
108#define ETHOSU_TA_PERFCNT_0 0
109#endif
110
111#ifndef ETHOSU_TA_MODE_0
112#define ETHOSU_TA_MODE_0 1
113#endif
114
115#ifndef ETHOSU_TA_HISTBIN_0
116#define ETHOSU_TA_HISTBIN_0 0
117#endif
118
119#ifndef ETHOSU_TA_HISTCNT_0
120#define ETHOSU_TA_HISTCNT_0 0
121#endif
122
123#ifndef ETHOSU_TA_MAXR_1
124#define ETHOSU_TA_MAXR_1 0
125#endif
126
127#ifndef ETHOSU_TA_MAXW_1
128#define ETHOSU_TA_MAXW_1 0
129#endif
130
131#ifndef ETHOSU_TA_MAXRW_1
132#define ETHOSU_TA_MAXRW_1 0
133#endif
134
135#ifndef ETHOSU_TA_RLATENCY_1
136#define ETHOSU_TA_RLATENCY_1 0
137#endif
138
139#ifndef ETHOSU_TA_WLATENCY_1
140#define ETHOSU_TA_WLATENCY_1 0
141#endif
142
143#ifndef ETHOSU_TA_PULSE_ON_1
144#define ETHOSU_TA_PULSE_ON_1 0
145#endif
146
147#ifndef ETHOSU_TA_PULSE_OFF_1
148#define ETHOSU_TA_PULSE_OFF_1 0
149#endif
150
151#ifndef ETHOSU_TA_BWCAP_1
152#define ETHOSU_TA_BWCAP_1 0
153#endif
154
155#ifndef ETHOSU_TA_PERFCTRL_1
156#define ETHOSU_TA_PERFCTRL_1 0
157#endif
158
159#ifndef ETHOSU_TA_PERFCNT_1
160#define ETHOSU_TA_PERFCNT_1 0
161#endif
162
163#ifndef ETHOSU_TA_MODE_1
164#define ETHOSU_TA_MODE_1 1
165#endif
166
167#ifndef ETHOSU_TA_HISTBIN_1
168#define ETHOSU_TA_HISTBIN_1 0
169#endif
170
171#ifndef ETHOSU_TA_HISTCNT_1
172#define ETHOSU_TA_HISTCNT_1 0
173#endif
174
175static uintptr_t ethosu_ta_base_addrs[ETHOSU_NPU_COUNT][ETHOSU_NPU_TA_COUNT] = {
176 {ETHOSU0_TA0_BASE_ADDRESS, ETHOSU0_TA1_BASE_ADDRESS}};
177struct timing_adapter ethosu_ta[ETHOSU_NPU_COUNT][ETHOSU_NPU_TA_COUNT];
178struct timing_adapter_settings ethosu_ta_settings[ETHOSU_NPU_TA_COUNT] = {{ETHOSU_TA_MAXR_0,
179 ETHOSU_TA_MAXW_0,
180 ETHOSU_TA_MAXRW_0,
181 ETHOSU_TA_RLATENCY_0,
182 ETHOSU_TA_WLATENCY_0,
183 ETHOSU_TA_PULSE_ON_0,
184 ETHOSU_TA_PULSE_OFF_0,
185 ETHOSU_TA_BWCAP_0,
186 ETHOSU_TA_PERFCTRL_0,
187 ETHOSU_TA_PERFCNT_0,
188 ETHOSU_TA_MODE_0,
189 0, // Read only register
190 ETHOSU_TA_HISTBIN_0,
191 ETHOSU_TA_HISTCNT_0},
192 {ETHOSU_TA_MAXR_1,
193 ETHOSU_TA_MAXW_1,
194 ETHOSU_TA_MAXRW_1,
195 ETHOSU_TA_RLATENCY_1,
196 ETHOSU_TA_WLATENCY_1,
197 ETHOSU_TA_PULSE_ON_1,
198 ETHOSU_TA_PULSE_OFF_1,
199 ETHOSU_TA_BWCAP_1,
200 ETHOSU_TA_PERFCTRL_1,
201 ETHOSU_TA_PERFCNT_1,
202 ETHOSU_TA_MODE_1,
203 0, // Read only register
204 ETHOSU_TA_HISTBIN_1,
205 ETHOSU_TA_HISTCNT_1}};
206
207#endif
208
209/****************************************************************************
210 * Cache maintenance
211 ****************************************************************************/
212
213#if defined(CPU_CACHE_ENABLE) && defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
214extern "C" {
215void ethosu_flush_dcache(uint32_t *p, size_t bytes) {
216 if (p)
217 SCB_CleanDCache_by_Addr(p, bytes);
218 else
219 SCB_CleanDCache();
220}
221
222void ethosu_invalidate_dcache(uint32_t *p, size_t bytes) {
223 if (p)
224 SCB_InvalidateDCache_by_Addr(p, bytes);
225 else
226 SCB_InvalidateDCache();
227}
228}
229#endif
230
231/****************************************************************************
232 * Init
233 ****************************************************************************/
234
235namespace {
236
237extern "C" {
238struct ExcContext {
239 uint32_t r0;
240 uint32_t r1;
241 uint32_t r2;
242 uint32_t r3;
243 uint32_t r12;
244 uint32_t lr;
245 uint32_t pc;
246 uint32_t xPsr;
247};
248
249void HardFault_Handler() {
250 int irq;
251 struct ExcContext *e;
252 uint32_t sp;
253
254 asm volatile("mrs %0, ipsr \n" // Read IPSR (Exceptio number)
255 "sub %0, #16 \n" // Get it into IRQn_Type range
256 "tst lr, #4 \n" // Select the stack which was in use
257 "ite eq \n"
258 "mrseq %1, msp \n"
259 "mrsne %1, psp \n"
260 "mov %2, sp \n"
261 : "=r"(irq), "=r"(e), "=r"(sp));
262
263 printf("Hard fault. irq=%d, pc=0x%08" PRIx32 ", lr=0x%08" PRIx32 ", xpsr=0x%08" PRIx32 ", sp=0x%08" PRIx32 "\n",
264 irq,
265 e->pc,
266 e->lr,
267 e->xPsr,
268 sp);
269 printf(
270 "%11s cfsr=0x%08" PRIx32 " bfar=0x%08" PRIx32 " mmfar=0x%08" PRIx32 "\n", "", SCB->CFSR, SCB->BFAR, SCB->MMFAR);
271 exit(1);
272}
273}
274
275#ifdef ETHOSU
276void ethosuIrqHandler() {
277 ethosu_irq_handler(&ethosu0_driver);
278}
279#endif
280
281} // namespace
282
283namespace EthosU {
284
285void targetSetup() {
286 // Initialize UART driver
287 UartStdOutInit();
288
289#ifdef ETHOSU
290 // Initialize timing adapter(s)
291 for (int i = 0; i < ETHOSU_NPU_COUNT; i++) {
292 for (int j = 0; j < ETHOSU_NPU_TA_COUNT; j++) {
293 if (ta_init(&ethosu_ta[i][j], ethosu_ta_base_addrs[i][j])) {
294 printf("Failed to initialize timing-adapter %d for NPU %d\n", j, i);
295 } else {
296 // Set the updated configuration
297 ta_set_all(&ethosu_ta[i][j], &ethosu_ta_settings[j]);
298 }
299 }
300 }
301
302 // Initialize Ethos-U NPU driver
303 if (ethosu_init(&ethosu0_driver,
304 reinterpret_cast<void *>(ETHOSU_BASE_ADDRESS),
305 ethosu_scratch,
306 ETHOSU_FAST_MEMORY_SIZE,
307 1,
308 1)) {
309 printf("Failed to initialize NPU.\n");
310 return;
311 }
312
313 // Assumes SCB->VTOR point to RW memory
314 NVIC_SetVector(static_cast<IRQn_Type>(ETHOSU_IRQ), (uint32_t)&ethosuIrqHandler);
315 NVIC_EnableIRQ(static_cast<IRQn_Type>(ETHOSU_IRQ));
316#endif
317
318 // MPU setup
319 const std::vector<ARM_MPU_Region_t> mpuConfig = {
320 {
321 // ITCM (NS)
322 ARM_MPU_RBAR(0x00000000, // Base
323 ARM_MPU_SH_NON, // Non-shareable
324 1, // Read-Only
325 1, // Non-Privileged
326 0), // eXecute Never disabled
327 ARM_MPU_RLAR(0x00007fff, // Limit
328 Mpu::WTRA_index) // Attribute index - Write-Through, Read-allocate
329 },
330 {
331 // ITCM (S)
332 ARM_MPU_RBAR(0x10000000, // Base
333 ARM_MPU_SH_NON, // Non-shareable
334 1, // Read-Only
335 1, // Non-Privileged
336 0), // eXecute Never disabled
337 ARM_MPU_RLAR(0x10007fff, // Limit
338 Mpu::WTRA_index) // Attribute index - Write-Through, Read-allocate
339 },
340 {
341 // FPGA DATA SRAM; BRAM (NS)
342 ARM_MPU_RBAR(0x01000000, // Base
343 ARM_MPU_SH_NON, // Non-shareable
344 0, // Read-Write
345 1, // Non-Privileged
346 0), // eXecute Never disabled
347 ARM_MPU_RLAR(0x011fffff, // Limit
348 Mpu::WBWARA_index) // Attribute index - Write-Back, Write-Allocate, Read-allocate
349 },
350 {
351 // FPGA DATA SRAM; BRAM (S)
352 ARM_MPU_RBAR(0x11000000, // Base
353 ARM_MPU_SH_NON, // Non-shareable
354 0, // Read-Write
355 1, // Non-Privileged
356 0), // eXecute Never disabled
357 ARM_MPU_RLAR(0x111fffff, // Limit
358 Mpu::WBWARA_index) // Attribute index - Write-Back, Write-Allocate, Read-allocate
359 },
360 {
361 // DTCM (NS)
362 ARM_MPU_RBAR(0x20000000, // Base
363 ARM_MPU_SH_NON, // Non-shareable
364 0, // Read-Write
365 1, // Non-Privileged
366 1), // eXecute Never enabled
367 ARM_MPU_RLAR(0x20007fff, // Limit
368 Mpu::WBWARA_index) // Attribute index - Write-Back, Write-Allocate, Read-allocate
369 },
370 {
371 // DTCM (S)
372 ARM_MPU_RBAR(0x30000000, // Base
373 ARM_MPU_SH_NON, // Non-shareable
374 0, // Read-Write
375 1, // Non-Privileged
376 1), // eXecute Never enabled
377 ARM_MPU_RLAR(0x30007fff, // Limit
378 Mpu::WBWARA_index) // Attribute index - Write-Back, Write-Allocate, Read-allocate
379 },
380 {
381 // SSE-300 internal SRAM (NS)
382 ARM_MPU_RBAR(0x21000000, // Base
383 ARM_MPU_SH_NON, // Non-shareable
384 0, // Read-Write
385 1, // Non-Privileged
386 0), // eXecute Never disabled
387 ARM_MPU_RLAR(0x211fffff, // Limit
388 Mpu::WBWARA_index) // Attribute index - Write-Back, Write-Allocate, Read-allocate
389 },
390 {
391 // SSE-300 internal SRAM (S)
392 ARM_MPU_RBAR(0x31000000, // Base
393 ARM_MPU_SH_NON, // Non-shareable
394 0, // Read-Write
395 1, // Non-Privileged
396 0), // eXecute Never disabled
397 ARM_MPU_RLAR(0x311fffff, // Limit
398 Mpu::WBWARA_index) // Attribute index - Write-Back, Write-Allocate, Read-allocate
399 },
400 {
401 // DDR (NS)
402 ARM_MPU_RBAR(0x60000000, // Base
403 ARM_MPU_SH_NON, // Non-shareable
404 0, // Read-Write
405 1, // Non-Privileged
406 1), // eXecute Never enabled
407 ARM_MPU_RLAR(0x6fffffff, // Limit
408 Mpu::WBWARA_index) // Attribute index - Write-Back, Write-Allocate, Read-allocate
409 },
410 {
411 // DDR (S)
412 ARM_MPU_RBAR(0x70000000, // Base
413 ARM_MPU_SH_NON, // Non-shareable
414 0, // Read-Write
415 1, // Non-Privileged
416 1), // eXecute Never enabled
417 ARM_MPU_RLAR(0x7fffffff, // Limit
418 Mpu::WBWARA_index) // Attribute index - Write-Back, Write-Allocate, Read-allocate
419 }};
420
421 // Setup MPU configuration
422 Mpu::loadAndEnableConfig(&mpuConfig[0], mpuConfig.size());
423
424#if defined(CPU_CACHE_ENABLE) && defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
425 SCB_EnableICache();
426 SCB_EnableDCache();
427#endif
428}
429
430} // namespace EthosU