Kristofer Jonsson | f62c3d7 | 2021-01-21 17:39:03 +0100 | [diff] [blame] | 1 | /* |
Jonny Svärd | 4db21c9 | 2023-05-15 11:44:05 +0200 | [diff] [blame] | 2 | * SPDX-FileCopyrightText: Copyright 2020-2021, 2023 Arm Limited and/or its affiliates <open-source-office@arm.com> |
Kristofer Jonsson | f62c3d7 | 2021-01-21 17:39:03 +0100 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: Apache-2.0 |
| 5 | * |
| 6 | * Licensed under the Apache License, Version 2.0 (the License); you may |
| 7 | * not use this file except in compliance with the License. |
| 8 | * You may obtain a copy of the License at |
| 9 | * |
| 10 | * www.apache.org/licenses/LICENSE-2.0 |
| 11 | * |
| 12 | * Unless required by applicable law or agreed to in writing, software |
| 13 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT |
| 14 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 15 | * See the License for the specific language governing permissions and |
| 16 | * limitations under the License. |
| 17 | */ |
| 18 | |
| 19 | /**************************************************************************** |
| 20 | * Includes |
| 21 | ****************************************************************************/ |
| 22 | |
| 23 | #include "target.hpp" |
| 24 | |
| 25 | #ifdef ETHOSU |
| 26 | #include <ethosu_driver.h> |
Kristofer Jonsson | 7b8fa5e | 2021-12-16 14:02:56 +0100 | [diff] [blame] | 27 | #include <timing_adapter.h> |
Kristofer Jonsson | f62c3d7 | 2021-01-21 17:39:03 +0100 | [diff] [blame] | 28 | #endif |
| 29 | |
Jonny Svärd | 991af2b | 2021-04-15 17:31:01 +0200 | [diff] [blame] | 30 | #include "mpu.hpp" |
Yulia Garbovich | e9cdc63 | 2021-11-23 20:00:04 +0200 | [diff] [blame] | 31 | #include "uart_stdout.h" |
Kristofer Jonsson | f62c3d7 | 2021-01-21 17:39:03 +0100 | [diff] [blame] | 32 | |
Jonny Svärd | d667090 | 2021-03-18 15:49:27 +0100 | [diff] [blame] | 33 | #include <inttypes.h> |
Kristofer Jonsson | f62c3d7 | 2021-01-21 17:39:03 +0100 | [diff] [blame] | 34 | #include <stdio.h> |
Per Åstrand | 174e98d | 2021-02-09 17:48:53 +0100 | [diff] [blame] | 35 | #include <stdlib.h> |
Jonny Svärd | 991af2b | 2021-04-15 17:31:01 +0200 | [diff] [blame] | 36 | #include <vector> |
Kristofer Jonsson | f62c3d7 | 2021-01-21 17:39:03 +0100 | [diff] [blame] | 37 | |
| 38 | using namespace EthosU; |
| 39 | |
| 40 | /**************************************************************************** |
| 41 | * Defines |
| 42 | ****************************************************************************/ |
| 43 | |
| 44 | #define ETHOSU_BASE_ADDRESS 0x48102000 |
Jonny Svärd | d667090 | 2021-03-18 15:49:27 +0100 | [diff] [blame] | 45 | #define ETHOSU_IRQ 56 |
Jonny Svärd | 4db21c9 | 2023-05-15 11:44:05 +0200 | [diff] [blame] | 46 | #define ETHOSU_IRQ_PRIORITY 5 |
Kristofer Jonsson | f62c3d7 | 2021-01-21 17:39:03 +0100 | [diff] [blame] | 47 | |
Jonny Svärd | d667090 | 2021-03-18 15:49:27 +0100 | [diff] [blame] | 48 | #define ETHOSU0_TA0_BASE_ADDRESS 0x48103000 |
| 49 | #define ETHOSU0_TA1_BASE_ADDRESS 0x48103200 |
Kristofer Jonsson | f62c3d7 | 2021-01-21 17:39:03 +0100 | [diff] [blame] | 50 | |
| 51 | /**************************************************************************** |
| 52 | * Variables |
| 53 | ****************************************************************************/ |
| 54 | |
| 55 | #if defined(ETHOSU_FAST_MEMORY_SIZE) && ETHOSU_FAST_MEMORY_SIZE > 0 |
| 56 | __attribute__((aligned(16), section(".bss.ethosu_scratch"))) uint8_t ethosu_scratch[ETHOSU_FAST_MEMORY_SIZE]; |
| 57 | #else |
| 58 | #define ethosu_scratch 0 |
| 59 | #define ETHOSU_FAST_MEMORY_SIZE 0 |
| 60 | #endif |
| 61 | |
Jonny Svärd | 991af2b | 2021-04-15 17:31:01 +0200 | [diff] [blame] | 62 | #ifdef ETHOSU |
Jonny Svärd | c5941c4 | 2021-06-01 18:40:45 +0200 | [diff] [blame] | 63 | struct ethosu_driver ethosu0_driver; |
Jonny Svärd | 991af2b | 2021-04-15 17:31:01 +0200 | [diff] [blame] | 64 | #endif |
| 65 | |
Nir Ekhauz | a58edd8 | 2021-10-04 12:21:17 +0300 | [diff] [blame] | 66 | /**************************************************************************** |
| 67 | * Timing Adapters |
| 68 | ****************************************************************************/ |
| 69 | |
Kristofer Jonsson | 7b8fa5e | 2021-12-16 14:02:56 +0100 | [diff] [blame] | 70 | #ifdef ETHOSU |
| 71 | |
Kristofer Jonsson | 64f37cd | 2021-10-19 10:54:47 +0200 | [diff] [blame] | 72 | #ifndef ETHOSU_TA_MAXR_0 |
Nir Ekhauz | a58edd8 | 2021-10-04 12:21:17 +0300 | [diff] [blame] | 73 | #define ETHOSU_TA_MAXR_0 0 |
| 74 | #endif |
Kristofer Jonsson | 64f37cd | 2021-10-19 10:54:47 +0200 | [diff] [blame] | 75 | |
| 76 | #ifndef ETHOSU_TA_MAXW_0 |
Nir Ekhauz | a58edd8 | 2021-10-04 12:21:17 +0300 | [diff] [blame] | 77 | #define ETHOSU_TA_MAXW_0 0 |
| 78 | #endif |
Kristofer Jonsson | 64f37cd | 2021-10-19 10:54:47 +0200 | [diff] [blame] | 79 | |
| 80 | #ifndef ETHOSU_TA_MAXRW_0 |
Nir Ekhauz | a58edd8 | 2021-10-04 12:21:17 +0300 | [diff] [blame] | 81 | #define ETHOSU_TA_MAXRW_0 0 |
| 82 | #endif |
Kristofer Jonsson | 64f37cd | 2021-10-19 10:54:47 +0200 | [diff] [blame] | 83 | |
| 84 | #ifndef ETHOSU_TA_RLATENCY_0 |
Nir Ekhauz | a58edd8 | 2021-10-04 12:21:17 +0300 | [diff] [blame] | 85 | #define ETHOSU_TA_RLATENCY_0 0 |
| 86 | #endif |
Kristofer Jonsson | 64f37cd | 2021-10-19 10:54:47 +0200 | [diff] [blame] | 87 | |
| 88 | #ifndef ETHOSU_TA_WLATENCY_0 |
Nir Ekhauz | a58edd8 | 2021-10-04 12:21:17 +0300 | [diff] [blame] | 89 | #define ETHOSU_TA_WLATENCY_0 0 |
| 90 | #endif |
Kristofer Jonsson | 64f37cd | 2021-10-19 10:54:47 +0200 | [diff] [blame] | 91 | |
| 92 | #ifndef ETHOSU_TA_PULSE_ON_0 |
Nir Ekhauz | a58edd8 | 2021-10-04 12:21:17 +0300 | [diff] [blame] | 93 | #define ETHOSU_TA_PULSE_ON_0 0 |
| 94 | #endif |
Kristofer Jonsson | 64f37cd | 2021-10-19 10:54:47 +0200 | [diff] [blame] | 95 | |
| 96 | #ifndef ETHOSU_TA_PULSE_OFF_0 |
Nir Ekhauz | a58edd8 | 2021-10-04 12:21:17 +0300 | [diff] [blame] | 97 | #define ETHOSU_TA_PULSE_OFF_0 0 |
| 98 | #endif |
Kristofer Jonsson | 64f37cd | 2021-10-19 10:54:47 +0200 | [diff] [blame] | 99 | |
| 100 | #ifndef ETHOSU_TA_BWCAP_0 |
Nir Ekhauz | a58edd8 | 2021-10-04 12:21:17 +0300 | [diff] [blame] | 101 | #define ETHOSU_TA_BWCAP_0 0 |
| 102 | #endif |
Kristofer Jonsson | 64f37cd | 2021-10-19 10:54:47 +0200 | [diff] [blame] | 103 | |
| 104 | #ifndef ETHOSU_TA_PERFCTRL_0 |
Nir Ekhauz | a58edd8 | 2021-10-04 12:21:17 +0300 | [diff] [blame] | 105 | #define ETHOSU_TA_PERFCTRL_0 0 |
| 106 | #endif |
Kristofer Jonsson | 64f37cd | 2021-10-19 10:54:47 +0200 | [diff] [blame] | 107 | |
| 108 | #ifndef ETHOSU_TA_PERFCNT_0 |
Nir Ekhauz | a58edd8 | 2021-10-04 12:21:17 +0300 | [diff] [blame] | 109 | #define ETHOSU_TA_PERFCNT_0 0 |
| 110 | #endif |
Kristofer Jonsson | 64f37cd | 2021-10-19 10:54:47 +0200 | [diff] [blame] | 111 | |
| 112 | #ifndef ETHOSU_TA_MODE_0 |
| 113 | #define ETHOSU_TA_MODE_0 1 |
Nir Ekhauz | a58edd8 | 2021-10-04 12:21:17 +0300 | [diff] [blame] | 114 | #endif |
Kristofer Jonsson | 64f37cd | 2021-10-19 10:54:47 +0200 | [diff] [blame] | 115 | |
| 116 | #ifndef ETHOSU_TA_HISTBIN_0 |
Nir Ekhauz | a58edd8 | 2021-10-04 12:21:17 +0300 | [diff] [blame] | 117 | #define ETHOSU_TA_HISTBIN_0 0 |
| 118 | #endif |
Kristofer Jonsson | 64f37cd | 2021-10-19 10:54:47 +0200 | [diff] [blame] | 119 | |
| 120 | #ifndef ETHOSU_TA_HISTCNT_0 |
Nir Ekhauz | a58edd8 | 2021-10-04 12:21:17 +0300 | [diff] [blame] | 121 | #define ETHOSU_TA_HISTCNT_0 0 |
| 122 | #endif |
| 123 | |
Kristofer Jonsson | 64f37cd | 2021-10-19 10:54:47 +0200 | [diff] [blame] | 124 | #ifndef ETHOSU_TA_MAXR_1 |
Nir Ekhauz | a58edd8 | 2021-10-04 12:21:17 +0300 | [diff] [blame] | 125 | #define ETHOSU_TA_MAXR_1 0 |
| 126 | #endif |
Kristofer Jonsson | 64f37cd | 2021-10-19 10:54:47 +0200 | [diff] [blame] | 127 | |
| 128 | #ifndef ETHOSU_TA_MAXW_1 |
Nir Ekhauz | a58edd8 | 2021-10-04 12:21:17 +0300 | [diff] [blame] | 129 | #define ETHOSU_TA_MAXW_1 0 |
| 130 | #endif |
Kristofer Jonsson | 64f37cd | 2021-10-19 10:54:47 +0200 | [diff] [blame] | 131 | |
| 132 | #ifndef ETHOSU_TA_MAXRW_1 |
Nir Ekhauz | a58edd8 | 2021-10-04 12:21:17 +0300 | [diff] [blame] | 133 | #define ETHOSU_TA_MAXRW_1 0 |
| 134 | #endif |
Kristofer Jonsson | 64f37cd | 2021-10-19 10:54:47 +0200 | [diff] [blame] | 135 | |
| 136 | #ifndef ETHOSU_TA_RLATENCY_1 |
Nir Ekhauz | a58edd8 | 2021-10-04 12:21:17 +0300 | [diff] [blame] | 137 | #define ETHOSU_TA_RLATENCY_1 0 |
| 138 | #endif |
Kristofer Jonsson | 64f37cd | 2021-10-19 10:54:47 +0200 | [diff] [blame] | 139 | |
| 140 | #ifndef ETHOSU_TA_WLATENCY_1 |
Nir Ekhauz | a58edd8 | 2021-10-04 12:21:17 +0300 | [diff] [blame] | 141 | #define ETHOSU_TA_WLATENCY_1 0 |
| 142 | #endif |
Kristofer Jonsson | 64f37cd | 2021-10-19 10:54:47 +0200 | [diff] [blame] | 143 | |
| 144 | #ifndef ETHOSU_TA_PULSE_ON_1 |
Nir Ekhauz | a58edd8 | 2021-10-04 12:21:17 +0300 | [diff] [blame] | 145 | #define ETHOSU_TA_PULSE_ON_1 0 |
| 146 | #endif |
Kristofer Jonsson | 64f37cd | 2021-10-19 10:54:47 +0200 | [diff] [blame] | 147 | |
| 148 | #ifndef ETHOSU_TA_PULSE_OFF_1 |
Nir Ekhauz | a58edd8 | 2021-10-04 12:21:17 +0300 | [diff] [blame] | 149 | #define ETHOSU_TA_PULSE_OFF_1 0 |
| 150 | #endif |
Kristofer Jonsson | 64f37cd | 2021-10-19 10:54:47 +0200 | [diff] [blame] | 151 | |
| 152 | #ifndef ETHOSU_TA_BWCAP_1 |
Nir Ekhauz | a58edd8 | 2021-10-04 12:21:17 +0300 | [diff] [blame] | 153 | #define ETHOSU_TA_BWCAP_1 0 |
| 154 | #endif |
Kristofer Jonsson | 64f37cd | 2021-10-19 10:54:47 +0200 | [diff] [blame] | 155 | |
| 156 | #ifndef ETHOSU_TA_PERFCTRL_1 |
Nir Ekhauz | a58edd8 | 2021-10-04 12:21:17 +0300 | [diff] [blame] | 157 | #define ETHOSU_TA_PERFCTRL_1 0 |
| 158 | #endif |
Kristofer Jonsson | 64f37cd | 2021-10-19 10:54:47 +0200 | [diff] [blame] | 159 | |
| 160 | #ifndef ETHOSU_TA_PERFCNT_1 |
Nir Ekhauz | a58edd8 | 2021-10-04 12:21:17 +0300 | [diff] [blame] | 161 | #define ETHOSU_TA_PERFCNT_1 0 |
| 162 | #endif |
Kristofer Jonsson | 64f37cd | 2021-10-19 10:54:47 +0200 | [diff] [blame] | 163 | |
| 164 | #ifndef ETHOSU_TA_MODE_1 |
| 165 | #define ETHOSU_TA_MODE_1 1 |
Nir Ekhauz | a58edd8 | 2021-10-04 12:21:17 +0300 | [diff] [blame] | 166 | #endif |
Kristofer Jonsson | 64f37cd | 2021-10-19 10:54:47 +0200 | [diff] [blame] | 167 | |
| 168 | #ifndef ETHOSU_TA_HISTBIN_1 |
Nir Ekhauz | a58edd8 | 2021-10-04 12:21:17 +0300 | [diff] [blame] | 169 | #define ETHOSU_TA_HISTBIN_1 0 |
| 170 | #endif |
Kristofer Jonsson | 64f37cd | 2021-10-19 10:54:47 +0200 | [diff] [blame] | 171 | |
| 172 | #ifndef ETHOSU_TA_HISTCNT_1 |
Nir Ekhauz | a58edd8 | 2021-10-04 12:21:17 +0300 | [diff] [blame] | 173 | #define ETHOSU_TA_HISTCNT_1 0 |
| 174 | #endif |
| 175 | |
Jonny Svärd | d667090 | 2021-03-18 15:49:27 +0100 | [diff] [blame] | 176 | static uintptr_t ethosu_ta_base_addrs[ETHOSU_NPU_COUNT][ETHOSU_NPU_TA_COUNT] = { |
| 177 | {ETHOSU0_TA0_BASE_ADDRESS, ETHOSU0_TA1_BASE_ADDRESS}}; |
| 178 | struct timing_adapter ethosu_ta[ETHOSU_NPU_COUNT][ETHOSU_NPU_TA_COUNT]; |
Nir Ekhauz | a58edd8 | 2021-10-04 12:21:17 +0300 | [diff] [blame] | 179 | struct timing_adapter_settings ethosu_ta_settings[ETHOSU_NPU_TA_COUNT] = {{ETHOSU_TA_MAXR_0, |
| 180 | ETHOSU_TA_MAXW_0, |
| 181 | ETHOSU_TA_MAXRW_0, |
| 182 | ETHOSU_TA_RLATENCY_0, |
| 183 | ETHOSU_TA_WLATENCY_0, |
| 184 | ETHOSU_TA_PULSE_ON_0, |
| 185 | ETHOSU_TA_PULSE_OFF_0, |
| 186 | ETHOSU_TA_BWCAP_0, |
| 187 | ETHOSU_TA_PERFCTRL_0, |
| 188 | ETHOSU_TA_PERFCNT_0, |
| 189 | ETHOSU_TA_MODE_0, |
Kristofer Jonsson | 29467e0 | 2021-11-26 16:10:43 +0100 | [diff] [blame] | 190 | 0, // Read only register |
Nir Ekhauz | a58edd8 | 2021-10-04 12:21:17 +0300 | [diff] [blame] | 191 | ETHOSU_TA_HISTBIN_0, |
| 192 | ETHOSU_TA_HISTCNT_0}, |
| 193 | {ETHOSU_TA_MAXR_1, |
| 194 | ETHOSU_TA_MAXW_1, |
| 195 | ETHOSU_TA_MAXRW_1, |
| 196 | ETHOSU_TA_RLATENCY_1, |
| 197 | ETHOSU_TA_WLATENCY_1, |
| 198 | ETHOSU_TA_PULSE_ON_1, |
| 199 | ETHOSU_TA_PULSE_OFF_1, |
| 200 | ETHOSU_TA_BWCAP_1, |
| 201 | ETHOSU_TA_PERFCTRL_1, |
| 202 | ETHOSU_TA_PERFCNT_1, |
| 203 | ETHOSU_TA_MODE_1, |
Kristofer Jonsson | 29467e0 | 2021-11-26 16:10:43 +0100 | [diff] [blame] | 204 | 0, // Read only register |
Nir Ekhauz | a58edd8 | 2021-10-04 12:21:17 +0300 | [diff] [blame] | 205 | ETHOSU_TA_HISTBIN_1, |
| 206 | ETHOSU_TA_HISTCNT_1}}; |
Kristofer Jonsson | 29467e0 | 2021-11-26 16:10:43 +0100 | [diff] [blame] | 207 | |
Kristofer Jonsson | 7b8fa5e | 2021-12-16 14:02:56 +0100 | [diff] [blame] | 208 | #endif |
| 209 | |
Kristofer Jonsson | f62c3d7 | 2021-01-21 17:39:03 +0100 | [diff] [blame] | 210 | /**************************************************************************** |
| 211 | * Cache maintenance |
| 212 | ****************************************************************************/ |
| 213 | |
| 214 | #if defined(CPU_CACHE_ENABLE) && defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) |
| 215 | extern "C" { |
| 216 | void ethosu_flush_dcache(uint32_t *p, size_t bytes) { |
| 217 | if (p) |
| 218 | SCB_CleanDCache_by_Addr(p, bytes); |
| 219 | else |
| 220 | SCB_CleanDCache(); |
| 221 | } |
| 222 | |
| 223 | void ethosu_invalidate_dcache(uint32_t *p, size_t bytes) { |
| 224 | if (p) |
| 225 | SCB_InvalidateDCache_by_Addr(p, bytes); |
| 226 | else |
| 227 | SCB_InvalidateDCache(); |
| 228 | } |
| 229 | } |
| 230 | #endif |
| 231 | |
| 232 | /**************************************************************************** |
| 233 | * Init |
| 234 | ****************************************************************************/ |
| 235 | |
| 236 | namespace { |
| 237 | |
Per Åstrand | 174e98d | 2021-02-09 17:48:53 +0100 | [diff] [blame] | 238 | extern "C" { |
| 239 | struct ExcContext { |
| 240 | uint32_t r0; |
| 241 | uint32_t r1; |
| 242 | uint32_t r2; |
| 243 | uint32_t r3; |
| 244 | uint32_t r12; |
| 245 | uint32_t lr; |
| 246 | uint32_t pc; |
| 247 | uint32_t xPsr; |
| 248 | }; |
| 249 | |
| 250 | void HardFault_Handler() { |
| 251 | int irq; |
| 252 | struct ExcContext *e; |
| 253 | uint32_t sp; |
| 254 | |
| 255 | asm volatile("mrs %0, ipsr \n" // Read IPSR (Exceptio number) |
| 256 | "sub %0, #16 \n" // Get it into IRQn_Type range |
| 257 | "tst lr, #4 \n" // Select the stack which was in use |
| 258 | "ite eq \n" |
| 259 | "mrseq %1, msp \n" |
| 260 | "mrsne %1, psp \n" |
| 261 | "mov %2, sp \n" |
| 262 | : "=r"(irq), "=r"(e), "=r"(sp)); |
| 263 | |
| 264 | printf("Hard fault. irq=%d, pc=0x%08" PRIx32 ", lr=0x%08" PRIx32 ", xpsr=0x%08" PRIx32 ", sp=0x%08" PRIx32 "\n", |
| 265 | irq, |
| 266 | e->pc, |
| 267 | e->lr, |
| 268 | e->xPsr, |
| 269 | sp); |
| 270 | printf( |
| 271 | "%11s cfsr=0x%08" PRIx32 " bfar=0x%08" PRIx32 " mmfar=0x%08" PRIx32 "\n", "", SCB->CFSR, SCB->BFAR, SCB->MMFAR); |
| 272 | exit(1); |
| 273 | } |
| 274 | } |
| 275 | |
Kristofer Jonsson | f62c3d7 | 2021-01-21 17:39:03 +0100 | [diff] [blame] | 276 | #ifdef ETHOSU |
| 277 | void ethosuIrqHandler() { |
Jonny Svärd | c5941c4 | 2021-06-01 18:40:45 +0200 | [diff] [blame] | 278 | ethosu_irq_handler(ðosu0_driver); |
Kristofer Jonsson | f62c3d7 | 2021-01-21 17:39:03 +0100 | [diff] [blame] | 279 | } |
| 280 | #endif |
| 281 | |
| 282 | } // namespace |
| 283 | |
| 284 | namespace EthosU { |
| 285 | |
| 286 | void targetSetup() { |
| 287 | // Initialize UART driver |
Yulia Garbovich | e9cdc63 | 2021-11-23 20:00:04 +0200 | [diff] [blame] | 288 | UartStdOutInit(); |
Kristofer Jonsson | f62c3d7 | 2021-01-21 17:39:03 +0100 | [diff] [blame] | 289 | |
Kristofer Jonsson | 7b8fa5e | 2021-12-16 14:02:56 +0100 | [diff] [blame] | 290 | #ifdef ETHOSU |
Jonny Svärd | d667090 | 2021-03-18 15:49:27 +0100 | [diff] [blame] | 291 | // Initialize timing adapter(s) |
| 292 | for (int i = 0; i < ETHOSU_NPU_COUNT; i++) { |
| 293 | for (int j = 0; j < ETHOSU_NPU_TA_COUNT; j++) { |
| 294 | if (ta_init(ðosu_ta[i][j], ethosu_ta_base_addrs[i][j])) { |
| 295 | printf("Failed to initialize timing-adapter %d for NPU %d\n", j, i); |
Nir Ekhauz | a58edd8 | 2021-10-04 12:21:17 +0300 | [diff] [blame] | 296 | } else { |
| 297 | // Set the updated configuration |
| 298 | ta_set_all(ðosu_ta[i][j], ðosu_ta_settings[j]); |
Jonny Svärd | d667090 | 2021-03-18 15:49:27 +0100 | [diff] [blame] | 299 | } |
| 300 | } |
| 301 | } |
| 302 | |
Kristofer Jonsson | f62c3d7 | 2021-01-21 17:39:03 +0100 | [diff] [blame] | 303 | // Initialize Ethos-U NPU driver |
Jonny Svärd | c5941c4 | 2021-06-01 18:40:45 +0200 | [diff] [blame] | 304 | if (ethosu_init(ðosu0_driver, |
Anton Moberg | ebe9a15 | 2021-05-03 09:28:52 +0200 | [diff] [blame] | 305 | reinterpret_cast<void *>(ETHOSU_BASE_ADDRESS), |
| 306 | ethosu_scratch, |
| 307 | ETHOSU_FAST_MEMORY_SIZE, |
| 308 | 1, |
| 309 | 1)) { |
Kristofer Jonsson | f62c3d7 | 2021-01-21 17:39:03 +0100 | [diff] [blame] | 310 | printf("Failed to initialize NPU.\n"); |
| 311 | return; |
| 312 | } |
| 313 | |
Jonny Svärd | 991af2b | 2021-04-15 17:31:01 +0200 | [diff] [blame] | 314 | // Assumes SCB->VTOR point to RW memory |
Kristofer Jonsson | f62c3d7 | 2021-01-21 17:39:03 +0100 | [diff] [blame] | 315 | NVIC_SetVector(static_cast<IRQn_Type>(ETHOSU_IRQ), (uint32_t)ðosuIrqHandler); |
Jonny Svärd | 4db21c9 | 2023-05-15 11:44:05 +0200 | [diff] [blame] | 316 | NVIC_SetPriority(static_cast<IRQn_Type>(ETHOSU_IRQ), ETHOSU_IRQ_PRIORITY); |
Kristofer Jonsson | f62c3d7 | 2021-01-21 17:39:03 +0100 | [diff] [blame] | 317 | NVIC_EnableIRQ(static_cast<IRQn_Type>(ETHOSU_IRQ)); |
| 318 | #endif |
Jonny Svärd | 991af2b | 2021-04-15 17:31:01 +0200 | [diff] [blame] | 319 | |
| 320 | // MPU setup |
| 321 | const std::vector<ARM_MPU_Region_t> mpuConfig = { |
| 322 | { |
Jonny Svärd | e3b6b96 | 2021-04-27 11:32:31 +0200 | [diff] [blame] | 323 | // ITCM (NS) |
Jonny Svärd | 991af2b | 2021-04-15 17:31:01 +0200 | [diff] [blame] | 324 | ARM_MPU_RBAR(0x00000000, // Base |
| 325 | ARM_MPU_SH_NON, // Non-shareable |
| 326 | 1, // Read-Only |
| 327 | 1, // Non-Privileged |
| 328 | 0), // eXecute Never disabled |
| 329 | ARM_MPU_RLAR(0x0007ffff, // Limit |
| 330 | Mpu::WTRA_index) // Attribute index - Write-Through, Read-allocate |
| 331 | }, |
| 332 | { |
Jonny Svärd | e3b6b96 | 2021-04-27 11:32:31 +0200 | [diff] [blame] | 333 | // ITCM (S) |
Jonny Svärd | 991af2b | 2021-04-15 17:31:01 +0200 | [diff] [blame] | 334 | ARM_MPU_RBAR(0x10000000, // Base |
| 335 | ARM_MPU_SH_NON, // Non-shareable |
| 336 | 1, // Read-Only |
| 337 | 1, // Non-Privileged |
| 338 | 0), // eXecute Never disabled |
| 339 | ARM_MPU_RLAR(0x1007ffff, // Limit |
| 340 | Mpu::WTRA_index) // Attribute index - Write-Through, Read-allocate |
| 341 | }, |
| 342 | { |
Jonny Svärd | e3b6b96 | 2021-04-27 11:32:31 +0200 | [diff] [blame] | 343 | // FPGA DATA SRAM; BRAM (NS) |
| 344 | ARM_MPU_RBAR(0x01000000, // Base |
| 345 | ARM_MPU_SH_NON, // Non-shareable |
| 346 | 0, // Read-Write |
| 347 | 1, // Non-Privileged |
| 348 | 0), // eXecute Never disabled |
| 349 | ARM_MPU_RLAR(0x011fffff, // Limit |
| 350 | Mpu::WBWARA_index) // Attribute index - Write-Back, Write-Allocate, Read-allocate |
| 351 | }, |
| 352 | { |
| 353 | // FPGA DATA SRAM; BRAM (S) |
Jonny Svärd | 991af2b | 2021-04-15 17:31:01 +0200 | [diff] [blame] | 354 | ARM_MPU_RBAR(0x11000000, // Base |
| 355 | ARM_MPU_SH_NON, // Non-shareable |
| 356 | 0, // Read-Write |
| 357 | 1, // Non-Privileged |
| 358 | 0), // eXecute Never disabled |
| 359 | ARM_MPU_RLAR(0x111fffff, // Limit |
| 360 | Mpu::WBWARA_index) // Attribute index - Write-Back, Write-Allocate, Read-allocate |
| 361 | }, |
| 362 | { |
Jonny Svärd | e3b6b96 | 2021-04-27 11:32:31 +0200 | [diff] [blame] | 363 | // DTCM (NS) |
| 364 | ARM_MPU_RBAR(0x20000000, // Base |
| 365 | ARM_MPU_SH_NON, // Non-shareable |
| 366 | 0, // Read-Write |
| 367 | 1, // Non-Privileged |
| 368 | 1), // eXecute Never enabled |
| 369 | ARM_MPU_RLAR(0x2007ffff, // Limit |
| 370 | Mpu::WBWARA_index) // Attribute index - Write-Back, Write-Allocate, Read-allocate |
| 371 | }, |
| 372 | { |
| 373 | // DTCM (S) |
Jonny Svärd | 991af2b | 2021-04-15 17:31:01 +0200 | [diff] [blame] | 374 | ARM_MPU_RBAR(0x30000000, // Base |
| 375 | ARM_MPU_SH_NON, // Non-shareable |
| 376 | 0, // Read-Write |
| 377 | 1, // Non-Privileged |
| 378 | 1), // eXecute Never enabled |
| 379 | ARM_MPU_RLAR(0x3007ffff, // Limit |
| 380 | Mpu::WBWARA_index) // Attribute index - Write-Back, Write-Allocate, Read-allocate |
| 381 | }, |
| 382 | { |
Jonny Svärd | e3b6b96 | 2021-04-27 11:32:31 +0200 | [diff] [blame] | 383 | // SSE-300 internal SRAM (NS) |
| 384 | ARM_MPU_RBAR(0x21000000, // Base |
| 385 | ARM_MPU_SH_NON, // Non-shareable |
| 386 | 0, // Read-Write |
| 387 | 1, // Non-Privileged |
| 388 | 1), // eXecute Never enabled |
| 389 | ARM_MPU_RLAR(0x213fffff, // Limit |
| 390 | Mpu::WBWARA_index) // Attribute index - Write-Back, Write-Allocate, Read-allocate |
| 391 | }, |
| 392 | { |
| 393 | // SSE-300 internal SRAM (S) |
Jonny Svärd | 991af2b | 2021-04-15 17:31:01 +0200 | [diff] [blame] | 394 | ARM_MPU_RBAR(0x31000000, // Base |
| 395 | ARM_MPU_SH_NON, // Non-shareable |
| 396 | 0, // Read-Write |
| 397 | 1, // Non-Privileged |
| 398 | 1), // eXecute Never enabled |
| 399 | ARM_MPU_RLAR(0x313fffff, // Limit |
| 400 | Mpu::WBWARA_index) // Attribute index - Write-Back, Write-Allocate, Read-allocate |
| 401 | }, |
| 402 | { |
Jonny Svärd | e3b6b96 | 2021-04-27 11:32:31 +0200 | [diff] [blame] | 403 | // DDR (NS) |
| 404 | ARM_MPU_RBAR(0x60000000, // Base |
| 405 | ARM_MPU_SH_NON, // Non-shareable |
| 406 | 0, // Read-Write |
| 407 | 1, // Non-Privileged |
| 408 | 1), // eXecute Never enabled |
| 409 | ARM_MPU_RLAR(0x6fffffff, // Limit |
| 410 | Mpu::WBWARA_index) // Attribute index - Write-Back, Write-Allocate, Read-allocate |
| 411 | }, |
| 412 | { |
| 413 | // DDR (S) |
Jonny Svärd | 991af2b | 2021-04-15 17:31:01 +0200 | [diff] [blame] | 414 | ARM_MPU_RBAR(0x70000000, // Base |
| 415 | ARM_MPU_SH_NON, // Non-shareable |
| 416 | 0, // Read-Write |
| 417 | 1, // Non-Privileged |
| 418 | 1), // eXecute Never enabled |
| 419 | ARM_MPU_RLAR(0x7fffffff, // Limit |
| 420 | Mpu::WBWARA_index) // Attribute index - Write-Back, Write-Allocate, Read-allocate |
| 421 | }}; |
| 422 | |
| 423 | // Setup MPU configuration |
| 424 | Mpu::loadAndEnableConfig(&mpuConfig[0], mpuConfig.size()); |
| 425 | |
| 426 | #if defined(CPU_CACHE_ENABLE) && defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) |
| 427 | SCB_EnableICache(); |
| 428 | SCB_EnableDCache(); |
| 429 | #endif |
Kristofer Jonsson | f62c3d7 | 2021-01-21 17:39:03 +0100 | [diff] [blame] | 430 | } |
| 431 | |
| 432 | } // namespace EthosU |