Per Åstrand | d748336 | 2020-10-07 13:50:46 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | |
Per Åstrand | be87baf | 2020-10-07 13:47:24 +0200 | [diff] [blame] | 3 | /* |
| 4 | * Message Handling Unit version 2 controller driver |
Per Åstrand | 8fac4a4 | 2020-10-12 13:37:16 +0200 | [diff] [blame] | 5 | * Copyright (C) 2019-2020 ARM Ltd. |
Per Åstrand | be87baf | 2020-10-07 13:47:24 +0200 | [diff] [blame] | 6 | * |
| 7 | * Based on drivers/mailbox/arm_mhu.c |
| 8 | * |
| 9 | */ |
| 10 | |
| 11 | #include <linux/interrupt.h> |
| 12 | #include <linux/mutex.h> |
| 13 | #include <linux/slab.h> |
| 14 | #include <linux/err.h> |
| 15 | #include <linux/io.h> |
| 16 | #include <linux/module.h> |
| 17 | #include <linux/amba/bus.h> |
| 18 | #include <linux/mailbox_controller.h> |
| 19 | #include <linux/of_device.h> |
| 20 | #include <linux/of_address.h> |
Anton Moberg | bdcb622 | 2021-08-25 14:06:24 +0200 | [diff] [blame] | 21 | #include <linux/version.h> |
Per Åstrand | be87baf | 2020-10-07 13:47:24 +0200 | [diff] [blame] | 22 | |
Per Åstrand | d748336 | 2020-10-07 13:50:46 +0200 | [diff] [blame] | 23 | #define MHU_V2_REG_STAT_OFS 0x0 |
| 24 | #define MHU_V2_REG_CLR_OFS 0x8 |
| 25 | #define MHU_V2_REG_SET_OFS 0xC |
| 26 | #define MHU_V2_REG_MSG_NO_CAP_OFS 0xF80 |
| 27 | #define MHU_V2_REG_ACC_REQ_OFS 0xF88 |
| 28 | #define MHU_V2_REG_ACC_RDY_OFS 0xF8C |
| 29 | #define MHU_V2_INT_EN_OFS 0xF98 |
| 30 | #define MHU_V2_AIDR_OFS 0xFCC |
Per Åstrand | be87baf | 2020-10-07 13:47:24 +0200 | [diff] [blame] | 31 | |
Per Åstrand | d748336 | 2020-10-07 13:50:46 +0200 | [diff] [blame] | 32 | #define MHU_V2_CHCOMB BIT(2) |
| 33 | #define MHU_V2_AIDR_MINOR(_reg) ((_reg) & 0xF) |
Per Åstrand | be87baf | 2020-10-07 13:47:24 +0200 | [diff] [blame] | 34 | |
Per Åstrand | d748336 | 2020-10-07 13:50:46 +0200 | [diff] [blame] | 35 | #define MHU_V2_EACH_CHANNEL_SIZE 0x20 |
Per Åstrand | be87baf | 2020-10-07 13:47:24 +0200 | [diff] [blame] | 36 | |
| 37 | #define mbox_to_arm_mhuv2(c) container_of(c, struct arm_mhuv2, mbox) |
| 38 | |
| 39 | struct mhuv2_link { |
| 40 | unsigned int irq; |
| 41 | void __iomem *tx_reg; |
| 42 | void __iomem *rx_reg; |
| 43 | }; |
| 44 | |
| 45 | struct arm_mhuv2 { |
Per Åstrand | d748336 | 2020-10-07 13:50:46 +0200 | [diff] [blame] | 46 | void __iomem *base; |
| 47 | struct mhuv2_link *mlink; |
| 48 | struct mbox_chan *chan; |
Per Åstrand | be87baf | 2020-10-07 13:47:24 +0200 | [diff] [blame] | 49 | struct mbox_controller mbox; |
| 50 | }; |
| 51 | |
Per Åstrand | d748336 | 2020-10-07 13:50:46 +0200 | [diff] [blame] | 52 | static irqreturn_t mhuv2_rx_interrupt(int irq, |
| 53 | void *p) |
Per Åstrand | be87baf | 2020-10-07 13:47:24 +0200 | [diff] [blame] | 54 | { |
| 55 | struct mbox_chan *chan = p; |
| 56 | struct mhuv2_link *mlink = chan->con_priv; |
| 57 | u32 val; |
| 58 | |
| 59 | val = readl_relaxed(mlink->rx_reg + MHU_V2_REG_STAT_OFS); |
| 60 | if (!val) |
| 61 | return IRQ_NONE; |
| 62 | |
| 63 | mbox_chan_received_data(chan, (void *)&val); |
| 64 | |
| 65 | writel_relaxed(val, mlink->rx_reg + MHU_V2_REG_CLR_OFS); |
| 66 | |
| 67 | return IRQ_HANDLED; |
| 68 | } |
| 69 | |
| 70 | static bool mhuv2_last_tx_done(struct mbox_chan *chan) |
| 71 | { |
| 72 | struct mhuv2_link *mlink = chan->con_priv; |
| 73 | u32 val = readl_relaxed(mlink->tx_reg + MHU_V2_REG_STAT_OFS); |
| 74 | |
| 75 | return (val == 0); |
| 76 | } |
| 77 | |
Per Åstrand | d748336 | 2020-10-07 13:50:46 +0200 | [diff] [blame] | 78 | static int mhuv2_send_data(struct mbox_chan *chan, |
| 79 | void *data) |
Per Åstrand | be87baf | 2020-10-07 13:47:24 +0200 | [diff] [blame] | 80 | { |
| 81 | struct mhuv2_link *mlink = chan->con_priv; |
Per Åstrand | 8fac4a4 | 2020-10-12 13:37:16 +0200 | [diff] [blame] | 82 | struct arm_mhuv2 *mhuv2 = mbox_to_arm_mhuv2(chan->mbox); |
Per Åstrand | be87baf | 2020-10-07 13:47:24 +0200 | [diff] [blame] | 83 | u32 *arg = data; |
Per Åstrand | 8fac4a4 | 2020-10-12 13:37:16 +0200 | [diff] [blame] | 84 | u32 tmo = 100000; |
| 85 | |
| 86 | /* If ACCESS_REQUEST is low, we have to wait for the other side |
| 87 | * to relase ACCESS_READY before continuing. */ |
| 88 | if (!readl_relaxed(mhuv2->base + MHU_V2_REG_ACC_REQ_OFS)) { |
| 89 | while (readl_relaxed(mhuv2->base + MHU_V2_REG_ACC_RDY_OFS) && |
| 90 | --tmo != 0) |
| 91 | continue; |
| 92 | |
| 93 | if (!tmo) |
| 94 | goto err; |
| 95 | |
| 96 | /* Request access and wait for other side to ack */ |
| 97 | writel_relaxed(0x1, mhuv2->base + MHU_V2_REG_ACC_REQ_OFS); |
| 98 | tmo = 100000; |
| 99 | while (!readl_relaxed(mhuv2->base + MHU_V2_REG_ACC_RDY_OFS) && |
| 100 | --tmo != 0) |
| 101 | continue; |
| 102 | |
| 103 | if (!tmo) |
| 104 | goto err; |
| 105 | } else { |
| 106 | while (!readl_relaxed(mhuv2->base + MHU_V2_REG_ACC_RDY_OFS) && |
| 107 | --tmo != 0) |
| 108 | continue; |
| 109 | |
| 110 | if (!tmo) |
| 111 | goto err; |
| 112 | } |
Per Åstrand | be87baf | 2020-10-07 13:47:24 +0200 | [diff] [blame] | 113 | |
| 114 | writel_relaxed(*arg, mlink->tx_reg + MHU_V2_REG_SET_OFS); |
| 115 | |
| 116 | return 0; |
Per Åstrand | 8fac4a4 | 2020-10-12 13:37:16 +0200 | [diff] [blame] | 117 | |
| 118 | err: |
| 119 | dev_err(chan->mbox->dev, "Failed to acquire access to mhu.\n"); |
| 120 | |
| 121 | return 1; |
Per Åstrand | be87baf | 2020-10-07 13:47:24 +0200 | [diff] [blame] | 122 | } |
| 123 | |
| 124 | static int mhuv2_startup(struct mbox_chan *chan) |
| 125 | { |
| 126 | struct mhuv2_link *mlink = chan->con_priv; |
| 127 | u32 val; |
| 128 | int ret; |
| 129 | struct arm_mhuv2 *mhuv2 = mbox_to_arm_mhuv2(chan->mbox); |
| 130 | |
| 131 | writel_relaxed(0x1, mhuv2->base + MHU_V2_REG_ACC_REQ_OFS); |
| 132 | |
| 133 | val = readl_relaxed(mlink->tx_reg + MHU_V2_REG_STAT_OFS); |
| 134 | writel_relaxed(val, mlink->tx_reg + MHU_V2_REG_CLR_OFS); |
| 135 | |
| 136 | ret = request_irq(mlink->irq, mhuv2_rx_interrupt, |
| 137 | IRQF_SHARED, "mhuv2_link", chan); |
| 138 | if (ret) { |
| 139 | dev_err(chan->mbox->dev, |
| 140 | "unable to acquire IRQ %d\n", mlink->irq); |
Per Åstrand | d748336 | 2020-10-07 13:50:46 +0200 | [diff] [blame] | 141 | |
Per Åstrand | be87baf | 2020-10-07 13:47:24 +0200 | [diff] [blame] | 142 | return ret; |
| 143 | } |
| 144 | |
| 145 | return 0; |
| 146 | } |
| 147 | |
| 148 | static void mhuv2_shutdown(struct mbox_chan *chan) |
| 149 | { |
| 150 | struct mhuv2_link *mlink = chan->con_priv; |
| 151 | struct arm_mhuv2 *mhuv2 = mbox_to_arm_mhuv2(chan->mbox); |
| 152 | |
| 153 | writel_relaxed(0x0, mhuv2->base + MHU_V2_REG_ACC_REQ_OFS); |
| 154 | |
| 155 | free_irq(mlink->irq, chan); |
| 156 | } |
| 157 | |
| 158 | static const struct mbox_chan_ops mhuv2_ops = { |
Per Åstrand | d748336 | 2020-10-07 13:50:46 +0200 | [diff] [blame] | 159 | .send_data = mhuv2_send_data, |
| 160 | .startup = mhuv2_startup, |
| 161 | .shutdown = mhuv2_shutdown, |
Per Åstrand | be87baf | 2020-10-07 13:47:24 +0200 | [diff] [blame] | 162 | .last_tx_done = mhuv2_last_tx_done, |
| 163 | }; |
| 164 | |
| 165 | void mhuv2_check_enable_cmbint(struct mhuv2_link *link) |
| 166 | { |
| 167 | const u32 aidr = readl_relaxed(link->rx_reg + MHU_V2_AIDR_OFS); |
| 168 | |
Per Åstrand | d748336 | 2020-10-07 13:50:46 +0200 | [diff] [blame] | 169 | if (MHU_V2_AIDR_MINOR(aidr) == 1) |
| 170 | /* Enable combined receiver interrupt for MHUv2.1 */ |
Per Åstrand | be87baf | 2020-10-07 13:47:24 +0200 | [diff] [blame] | 171 | writel_relaxed(MHU_V2_CHCOMB, link->rx_reg + MHU_V2_INT_EN_OFS); |
Per Åstrand | be87baf | 2020-10-07 13:47:24 +0200 | [diff] [blame] | 172 | } |
| 173 | |
Per Åstrand | d748336 | 2020-10-07 13:50:46 +0200 | [diff] [blame] | 174 | static int mhuv2_probe(struct amba_device *adev, |
| 175 | const struct amba_id *id) |
Per Åstrand | be87baf | 2020-10-07 13:47:24 +0200 | [diff] [blame] | 176 | { |
| 177 | int i, err; |
| 178 | struct arm_mhuv2 *mhuv2; |
| 179 | struct device *dev = &adev->dev; |
| 180 | void __iomem *rx_base, *tx_base; |
| 181 | const struct device_node *np = dev->of_node; |
| 182 | unsigned int pchans; |
| 183 | struct mhuv2_link *mlink; |
| 184 | struct mbox_chan *chan; |
| 185 | |
Per Åstrand | be87baf | 2020-10-07 13:47:24 +0200 | [diff] [blame] | 186 | /* Allocate memory for device */ |
| 187 | mhuv2 = devm_kzalloc(dev, sizeof(*mhuv2), GFP_KERNEL); |
| 188 | if (!mhuv2) |
| 189 | return -ENOMEM; |
| 190 | |
| 191 | tx_base = of_iomap((struct device_node *)np, 0); |
| 192 | if (!tx_base) { |
| 193 | dev_err(dev, "failed to map tx registers\n"); |
Per Åstrand | be87baf | 2020-10-07 13:47:24 +0200 | [diff] [blame] | 194 | return -ENOMEM; |
| 195 | } |
| 196 | |
| 197 | rx_base = of_iomap((struct device_node *)np, 1); |
| 198 | if (!rx_base) { |
| 199 | dev_err(dev, "failed to map rx registers\n"); |
Jonny Svärd | 44c507e | 2021-02-09 16:37:40 +0100 | [diff] [blame] | 200 | iounmap(tx_base); |
Per Åstrand | be87baf | 2020-10-07 13:47:24 +0200 | [diff] [blame] | 201 | return -ENOMEM; |
| 202 | } |
| 203 | |
| 204 | pchans = readl_relaxed(tx_base + MHU_V2_REG_MSG_NO_CAP_OFS); |
| 205 | if (pchans == 0 || pchans % 2) { |
| 206 | dev_err(dev, "invalid number of channels %d\n", pchans); |
| 207 | iounmap(rx_base); |
| 208 | iounmap(tx_base); |
Per Åstrand | d748336 | 2020-10-07 13:50:46 +0200 | [diff] [blame] | 209 | |
Per Åstrand | be87baf | 2020-10-07 13:47:24 +0200 | [diff] [blame] | 210 | return -EINVAL; |
| 211 | } |
| 212 | |
| 213 | mhuv2->mlink = devm_kcalloc(dev, pchans, sizeof(*mlink), GFP_KERNEL); |
| 214 | if (!mhuv2->mlink) { |
| 215 | iounmap(rx_base); |
| 216 | iounmap(tx_base); |
Per Åstrand | d748336 | 2020-10-07 13:50:46 +0200 | [diff] [blame] | 217 | |
Per Åstrand | be87baf | 2020-10-07 13:47:24 +0200 | [diff] [blame] | 218 | return -ENOMEM; |
| 219 | } |
| 220 | |
| 221 | mhuv2->chan = devm_kcalloc(dev, pchans, sizeof(*chan), GFP_KERNEL); |
| 222 | if (!mhuv2->chan) { |
| 223 | iounmap(rx_base); |
| 224 | iounmap(tx_base); |
| 225 | kfree(mhuv2->mlink); |
Per Åstrand | d748336 | 2020-10-07 13:50:46 +0200 | [diff] [blame] | 226 | |
Per Åstrand | be87baf | 2020-10-07 13:47:24 +0200 | [diff] [blame] | 227 | return -ENOMEM; |
| 228 | } |
| 229 | |
| 230 | for (i = 0; i < pchans; i++) { |
| 231 | mlink = mhuv2->mlink + i; |
| 232 | chan = mhuv2->chan + i; |
| 233 | chan->con_priv = mlink; |
| 234 | mlink->rx_reg = rx_base + (i * MHU_V2_EACH_CHANNEL_SIZE); |
| 235 | mlink->tx_reg = tx_base + (i * MHU_V2_EACH_CHANNEL_SIZE); |
| 236 | } |
| 237 | |
| 238 | mhuv2->mlink->irq = adev->irq[0]; |
| 239 | mhuv2_check_enable_cmbint(mhuv2->mlink); |
| 240 | |
| 241 | mhuv2->base = tx_base; |
| 242 | mhuv2->mbox.dev = dev; |
| 243 | mhuv2->mbox.chans = mhuv2->chan; |
| 244 | mhuv2->mbox.num_chans = pchans; |
| 245 | mhuv2->mbox.ops = &mhuv2_ops; |
| 246 | mhuv2->mbox.txdone_irq = false; |
| 247 | mhuv2->mbox.txdone_poll = true; |
| 248 | mhuv2->mbox.txpoll_period = 1; |
| 249 | |
| 250 | amba_set_drvdata(adev, mhuv2); |
| 251 | |
| 252 | err = mbox_controller_register(&mhuv2->mbox); |
| 253 | if (err) { |
| 254 | dev_err(dev, "failed to register mailboxes %d\n", err); |
| 255 | iounmap(rx_base); |
| 256 | iounmap(tx_base); |
| 257 | kfree(mhuv2->mlink); |
| 258 | kfree(mhuv2->chan); |
Per Åstrand | d748336 | 2020-10-07 13:50:46 +0200 | [diff] [blame] | 259 | |
Per Åstrand | be87baf | 2020-10-07 13:47:24 +0200 | [diff] [blame] | 260 | return err; |
| 261 | } |
| 262 | |
| 263 | dev_info(dev, "ARM MHUv2 Mailbox driver registered\n"); |
Per Åstrand | d748336 | 2020-10-07 13:50:46 +0200 | [diff] [blame] | 264 | |
Per Åstrand | be87baf | 2020-10-07 13:47:24 +0200 | [diff] [blame] | 265 | return 0; |
| 266 | } |
| 267 | |
Anton Moberg | bdcb622 | 2021-08-25 14:06:24 +0200 | [diff] [blame] | 268 | #if KERNEL_VERSION(5, 12, 0) <= LINUX_VERSION_CODE |
| 269 | static void mhuv2_remove(struct amba_device *adev) |
| 270 | { |
| 271 | struct arm_mhuv2 *mhuv2 = amba_get_drvdata(adev); |
| 272 | |
| 273 | mbox_controller_unregister(&mhuv2->mbox); |
| 274 | } |
| 275 | #else |
Per Åstrand | be87baf | 2020-10-07 13:47:24 +0200 | [diff] [blame] | 276 | static int mhuv2_remove(struct amba_device *adev) |
| 277 | { |
| 278 | struct arm_mhuv2 *mhuv2 = amba_get_drvdata(adev); |
| 279 | |
| 280 | mbox_controller_unregister(&mhuv2->mbox); |
| 281 | |
| 282 | return 0; |
| 283 | } |
Anton Moberg | bdcb622 | 2021-08-25 14:06:24 +0200 | [diff] [blame] | 284 | #endif |
| 285 | |
Per Åstrand | be87baf | 2020-10-07 13:47:24 +0200 | [diff] [blame] | 286 | |
| 287 | static struct amba_id mhuv2_ids[] = { |
| 288 | { |
Per Åstrand | d748336 | 2020-10-07 13:50:46 +0200 | [diff] [blame] | 289 | .id = 0x4b0d1, |
| 290 | .mask = 0xfffff, |
Per Åstrand | be87baf | 2020-10-07 13:47:24 +0200 | [diff] [blame] | 291 | }, |
| 292 | { |
Per Åstrand | d748336 | 2020-10-07 13:50:46 +0200 | [diff] [blame] | 293 | .id = 0xbb0d1, |
| 294 | .mask = 0xfffff, |
Per Åstrand | be87baf | 2020-10-07 13:47:24 +0200 | [diff] [blame] | 295 | }, |
| 296 | { |
Per Åstrand | d748336 | 2020-10-07 13:50:46 +0200 | [diff] [blame] | 297 | .id = 0xbb076, |
| 298 | .mask = 0xfffff, |
Per Åstrand | be87baf | 2020-10-07 13:47:24 +0200 | [diff] [blame] | 299 | }, |
| 300 | { 0, 0 }, |
| 301 | }; |
| 302 | MODULE_DEVICE_TABLE(amba, mhuv2_ids); |
| 303 | |
| 304 | static struct amba_driver arm_mhuv2_driver = { |
Per Åstrand | d748336 | 2020-10-07 13:50:46 +0200 | [diff] [blame] | 305 | .drv = { |
| 306 | .name = "mhuv2", |
Per Åstrand | be87baf | 2020-10-07 13:47:24 +0200 | [diff] [blame] | 307 | }, |
Per Åstrand | d748336 | 2020-10-07 13:50:46 +0200 | [diff] [blame] | 308 | .id_table = mhuv2_ids, |
| 309 | .probe = mhuv2_probe, |
| 310 | .remove = mhuv2_remove, |
Per Åstrand | be87baf | 2020-10-07 13:47:24 +0200 | [diff] [blame] | 311 | }; |
| 312 | module_amba_driver(arm_mhuv2_driver); |
| 313 | |
| 314 | MODULE_LICENSE("GPL v2"); |
| 315 | MODULE_DESCRIPTION("ARM MHUv2 Driver"); |
| 316 | MODULE_AUTHOR("Samarth Parikh <samarthp@ymail.com>"); |