blob: 102fd44676fc84fe0458290099a55fd20b0806c5 [file] [log] [blame]
Kristofer Jonsson116a6352020-08-20 17:25:23 +02001/*
2 * Copyright (C) 2013-2015 Fujitsu Semiconductor Ltd.
3 * Copyright (C) 2015 Linaro Ltd.
4 * Copyright (C) 2020 Arm Ltd.
5 * Author: Jassi Brar <jaswinder.singh@linaro.org>
6 *
7 * This program is free software and is provided to you under the terms of the
8 * GNU General Public License version 2 as published by the Free Software
9 * Foundation, and any use by you of this program is subject to the terms
10 * of such GNU licence.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, you can access it online at
19 * http://www.gnu.org/licenses/gpl-2.0.html.
20 *
21 * SPDX-License-Identifier: GPL-2.0-only
22 */
23
24#include <linux/interrupt.h>
25#include <linux/spinlock.h>
26#include <linux/mutex.h>
27#include <linux/delay.h>
28#include <linux/slab.h>
29#include <linux/err.h>
30#include <linux/io.h>
31#include <linux/module.h>
32#include <linux/amba/bus.h>
33#include <linux/mailbox_controller.h>
Anton Mobergbdcb6222021-08-25 14:06:24 +020034#include <linux/version.h>
Kristofer Jonsson116a6352020-08-20 17:25:23 +020035
36struct mhu_register_offsets {
37 uint8_t intr_stat_ofs;
38 uint8_t intr_set_ofs;
39 uint8_t intr_clr_ofs;
40};
41
42#define MHU_MAX_CHANS 3
43struct mhu_cfg {
44 uint32_t id;
45 uint8_t channels;
46 struct mhu_register_offsets offsets;
47 uint16_t tx_offset;
48 uint16_t rx_offset;
49 uint32_t channel_offsets[MHU_MAX_CHANS];
50};
51
52struct mhu_link {
53 unsigned irq;
54 void __iomem *tx_reg;
55 void __iomem *rx_reg;
56 struct mhu_register_offsets *offsets;
57};
58
59#define MHU_LP_OFFSET 0x0
60#define MHU_HP_OFFSET 0x20
61#define MHU_SEC_OFFSET 0x200
62static struct mhu_cfg mhu_cfgs[] = {
63 {
64 /* MHUv1 */
65 .id = 0x1bb098,
66 .channels = 3,
67 .offsets = {
68 .intr_stat_ofs = 0x0,
69 .intr_set_ofs = 0x8,
70 .intr_clr_ofs = 0x10,
71 },
72 .tx_offset = 0x100,
73 .rx_offset = 0x0,
74 .channel_offsets = {MHU_LP_OFFSET, MHU_HP_OFFSET, MHU_SEC_OFFSET}
75 },
76 {
77 /* MHU found on CoreLink SSE200 */
78 .id = 0x0bb856,
79 .channels = 1,
80 .offsets = {
81 .intr_stat_ofs = 0x0,
82 .intr_set_ofs = 0x4,
83 .intr_clr_ofs = 0x8,
84 },
85 .tx_offset = 0x0,
86 .rx_offset = 0x10,
87 .channel_offsets = {0}
88 }
89};
90
91struct arm_mhu {
92 void __iomem *base;
93 struct mhu_link mlink[MHU_MAX_CHANS];
94 struct mbox_chan chan[MHU_MAX_CHANS];
95 struct mbox_controller mbox;
96};
97
98static irqreturn_t mhu_rx_interrupt(int irq, void *p)
99{
100 struct mbox_chan *chan = p;
101 struct mhu_link *mlink = chan->con_priv;
102 u32 val;
103
104 val = readl_relaxed(mlink->rx_reg + mlink->offsets->intr_stat_ofs);
105 if (!val)
106 return IRQ_NONE;
107
108 mbox_chan_received_data(chan, (void *)&val);
109
110 writel_relaxed(val, mlink->rx_reg + mlink->offsets->intr_clr_ofs);
111
112 return IRQ_HANDLED;
113}
114
115static bool mhu_last_tx_done(struct mbox_chan *chan)
116{
117 struct mhu_link *mlink = chan->con_priv;
118 u32 val = readl_relaxed(mlink->tx_reg + mlink->offsets->intr_stat_ofs);
119
120 return (val == 0);
121}
122
123static int mhu_send_data(struct mbox_chan *chan, void *data)
124{
125 struct mhu_link *mlink = chan->con_priv;
126 u32 *arg = data;
127
128 writel_relaxed(*arg, mlink->tx_reg + mlink->offsets->intr_set_ofs);
129
130 return 0;
131}
132
133static int mhu_startup(struct mbox_chan *chan)
134{
135 struct mhu_link *mlink = chan->con_priv;
136 u32 val;
137 int ret;
138
139 val = readl_relaxed(mlink->tx_reg + mlink->offsets->intr_stat_ofs);
140 writel_relaxed(val, mlink->tx_reg + mlink->offsets->intr_clr_ofs);
141
142 ret = request_irq(mlink->irq, mhu_rx_interrupt,
143 IRQF_SHARED, "mhu_link", chan);
144 if (ret) {
145 dev_err(chan->mbox->dev,
146 "Unable to acquire IRQ %d\n", mlink->irq);
147 return ret;
148 }
149
150 return 0;
151}
152
153static void mhu_shutdown(struct mbox_chan *chan)
154{
155 struct mhu_link *mlink = chan->con_priv;
156
157 free_irq(mlink->irq, chan);
158}
159
160static const struct mbox_chan_ops mhu_ops = {
161 .send_data = mhu_send_data,
162 .startup = mhu_startup,
163 .shutdown = mhu_shutdown,
164 .last_tx_done = mhu_last_tx_done,
165};
166
167static int mhu_probe(struct amba_device *adev, const struct amba_id *id)
168{
169 int i, err;
170 struct arm_mhu *mhu;
171 struct device *dev = &adev->dev;
172 struct mhu_cfg *cfg = NULL;
173
174 /* Allocate memory for device */
175 mhu = devm_kzalloc(dev, sizeof(*mhu), GFP_KERNEL);
176 if (!mhu)
177 return -ENOMEM;
178
179 mhu->base = devm_ioremap_resource(dev, &adev->res);
180 if (IS_ERR(mhu->base)) {
181 dev_err(dev, "ioremap failed\n");
182 return PTR_ERR(mhu->base);
183 }
184
185 for (i = 0; i < ARRAY_SIZE(mhu_cfgs); i++) {
186 if ((mhu_cfgs[i].id & id->mask) == id->id) {
187 cfg = &mhu_cfgs[i];
188 break;
189 }
190 }
191
192 if (!cfg) {
193 dev_err(dev, "Failed to match id %x to configuration\n", id->id);
194 return -EINVAL;
195 }
196
197 for (i = 0; i < cfg->channels; i++) {
198 mhu->chan[i].con_priv = &mhu->mlink[i];
199 mhu->mlink[i].irq = adev->irq[i];
200 mhu->mlink[i].rx_reg = mhu->base + cfg->channel_offsets[i]
201 + cfg->rx_offset;
202 mhu->mlink[i].tx_reg = mhu->base + cfg->channel_offsets[i]
203 + cfg->tx_offset;
204 mhu->mlink[i].offsets = &cfg->offsets;
205 }
206
207 mhu->mbox.dev = dev;
208 mhu->mbox.chans = &mhu->chan[0];
209 mhu->mbox.num_chans = cfg->channels;
210 mhu->mbox.ops = &mhu_ops;
211 mhu->mbox.txdone_irq = false;
212 mhu->mbox.txdone_poll = true;
213 mhu->mbox.txpoll_period = 1;
214
215 amba_set_drvdata(adev, mhu);
216
217 err = mbox_controller_register(&mhu->mbox);
218 if (err) {
219 dev_err(dev, "Failed to register mailboxes %d\n", err);
220 return err;
221 }
222
223 dev_info(dev, "ARM MHU Mailbox registered\n");
224 return 0;
225}
226
Anton Mobergbdcb6222021-08-25 14:06:24 +0200227#if KERNEL_VERSION(5, 12, 0) <= LINUX_VERSION_CODE
228static void mhu_remove(struct amba_device *adev)
229{
230 struct arm_mhu *mhu = amba_get_drvdata(adev);
231
232 mbox_controller_unregister(&mhu->mbox);
233}
234#else
Kristofer Jonsson116a6352020-08-20 17:25:23 +0200235static int mhu_remove(struct amba_device *adev)
236{
237 struct arm_mhu *mhu = amba_get_drvdata(adev);
238
239 mbox_controller_unregister(&mhu->mbox);
240
241 return 0;
242}
Anton Mobergbdcb6222021-08-25 14:06:24 +0200243#endif
244
Kristofer Jonsson116a6352020-08-20 17:25:23 +0200245
246static struct amba_id mhu_ids[] = {
247 {
248 .id = 0x1bb098,
249 .mask = 0xffffff,
250 },
251 {
252 .id = 0x0bb856,
253 .mask = 0xffffff,
254 },
255 { 0, 0 },
256};
257MODULE_DEVICE_TABLE(amba, mhu_ids);
258
259static struct amba_driver arm_mhu_driver = {
260 .drv = {
261 /* Change name from "mhu" to "mhu_v1" to avoid conflict with
262 * upstream version of kernel module.
263 */
264 .name = "mhu_v1",
265 },
266 .id_table = mhu_ids,
267 .probe = mhu_probe,
268 .remove = mhu_remove,
269};
270module_amba_driver(arm_mhu_driver);
271
272MODULE_LICENSE("GPL v2");
273MODULE_DESCRIPTION("ARM MHU Driver");
274MODULE_AUTHOR("Jassi Brar <jassisinghbrar@gmail.com>");