Per Åstrand | 9f36f2e | 2021-09-30 09:57:34 +0200 | [diff] [blame] | 1 | /* |
Mikael Olsson | 3875fa7 | 2023-09-11 14:01:58 +0200 | [diff] [blame] | 2 | * SPDX-FileCopyrightText: Copyright 2021, 2023 Arm Limited and/or its affiliates <open-source-office@arm.com> |
| 3 | * SPDX-License-Identifier: GPL-2.0-only |
Per Åstrand | 9f36f2e | 2021-09-30 09:57:34 +0200 | [diff] [blame] | 4 | * |
| 5 | * This program is free software and is provided to you under the terms of the |
| 6 | * GNU General Public License version 2 as published by the Free Software |
| 7 | * Foundation, and any use by you of this program is subject to the terms |
| 8 | * of such GNU licence. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, you can access it online at |
| 17 | * http://www.gnu.org/licenses/gpl-2.0.html. |
Per Åstrand | 9f36f2e | 2021-09-30 09:57:34 +0200 | [diff] [blame] | 18 | */ |
| 19 | |
| 20 | #include <linux/io.h> |
| 21 | #include <linux/kernel.h> |
| 22 | #include <linux/module.h> |
| 23 | #include <linux/of.h> |
| 24 | #include <linux/of_device.h> |
| 25 | #include <linux/platform_device.h> |
| 26 | #include <linux/reset-controller.h> |
| 27 | |
Mikael Olsson | a45260e | 2023-09-11 14:07:31 +0200 | [diff] [blame] | 28 | #define JUNO_FPGA_RESET_DRIVER_VERSION "0.1.0" |
Per Åstrand | 9f36f2e | 2021-09-30 09:57:34 +0200 | [diff] [blame] | 29 | |
| 30 | struct juno_fpga_reset { |
| 31 | struct reset_controller_dev rst; |
| 32 | struct device *dev; |
| 33 | void __iomem *base; |
| 34 | }; |
| 35 | |
Mikael Olsson | a45260e | 2023-09-11 14:07:31 +0200 | [diff] [blame] | 36 | /* Supported controller IDs */ |
| 37 | #define JUNO_FPGA_RESET_MIN_SUPPORTED_ID 0x2010f |
| 38 | #define JUNO_FPGA_RESET_MAX_SUPPORTED_ID 0x20113 |
| 39 | |
Per Åstrand | 9f36f2e | 2021-09-30 09:57:34 +0200 | [diff] [blame] | 40 | #define JUNO_FPGA_RESET_ID(base) (base) |
| 41 | #define JUNO_FPGA_RESET_SOFT_RESET(base) ((base) + 0x140) |
| 42 | #define JUNO_FPGA_RESET_CPU_WAIT(base) ((base) + 0x144) |
| 43 | |
| 44 | #define JUNO_FPGA_RESET_SET_RESET (0x1) |
| 45 | #define JUNO_FPGA_RESET_UNSET_RESET (0x0) |
| 46 | #define JUNO_FPGA_RESET_SET_CPUWAIT (0x1) |
| 47 | #define JUNO_FPGA_RESET_UNSET_CPUWAIT (0x0) |
| 48 | |
| 49 | static void __iomem *verify_and_remap(struct device *dev, |
| 50 | struct resource *res) |
| 51 | { |
| 52 | void __iomem *base = devm_ioremap_resource(dev, res); |
| 53 | u32 id; |
| 54 | |
| 55 | if (IS_ERR(base)) |
| 56 | return base; |
| 57 | |
| 58 | id = readl(JUNO_FPGA_RESET_ID(base)); |
| 59 | |
Mikael Olsson | a45260e | 2023-09-11 14:07:31 +0200 | [diff] [blame] | 60 | if (id < JUNO_FPGA_RESET_MIN_SUPPORTED_ID || |
| 61 | id > JUNO_FPGA_RESET_MAX_SUPPORTED_ID) { |
| 62 | dev_err(dev, "Unknown controller ID: %u", id); |
Mikael Olsson | 3875fa7 | 2023-09-11 14:01:58 +0200 | [diff] [blame] | 63 | |
Per Åstrand | 9f36f2e | 2021-09-30 09:57:34 +0200 | [diff] [blame] | 64 | return IOMEM_ERR_PTR(-EINVAL); |
Mikael Olsson | 3875fa7 | 2023-09-11 14:01:58 +0200 | [diff] [blame] | 65 | } |
Per Åstrand | 9f36f2e | 2021-09-30 09:57:34 +0200 | [diff] [blame] | 66 | |
| 67 | return base; |
| 68 | } |
| 69 | |
Mikael Olsson | 404a536 | 2023-11-14 10:42:14 +0100 | [diff] [blame] | 70 | static int juno_fpga_reset_assert(struct reset_controller_dev *rcdev, |
| 71 | unsigned long id) |
Per Åstrand | 9f36f2e | 2021-09-30 09:57:34 +0200 | [diff] [blame] | 72 | { |
Mikael Olsson | 3875fa7 | 2023-09-11 14:01:58 +0200 | [diff] [blame] | 73 | struct juno_fpga_reset *reset = container_of(rcdev, |
| 74 | struct juno_fpga_reset, |
| 75 | rst); |
Per Åstrand | 9f36f2e | 2021-09-30 09:57:34 +0200 | [diff] [blame] | 76 | |
| 77 | /* pull reset */ |
| 78 | dev_dbg(reset->dev, "Asserting reset"); |
| 79 | |
| 80 | /* set wait and reset */ |
| 81 | writel(JUNO_FPGA_RESET_SET_RESET, |
| 82 | JUNO_FPGA_RESET_SOFT_RESET(reset->base)); |
| 83 | writel(JUNO_FPGA_RESET_SET_CPUWAIT, |
| 84 | JUNO_FPGA_RESET_CPU_WAIT(reset->base)); |
| 85 | |
| 86 | writel(JUNO_FPGA_RESET_UNSET_RESET, |
| 87 | JUNO_FPGA_RESET_SOFT_RESET(reset->base)); |
Mikael Olsson | 3875fa7 | 2023-09-11 14:01:58 +0200 | [diff] [blame] | 88 | |
Per Åstrand | 9f36f2e | 2021-09-30 09:57:34 +0200 | [diff] [blame] | 89 | return 0; |
| 90 | } |
| 91 | |
Mikael Olsson | 404a536 | 2023-11-14 10:42:14 +0100 | [diff] [blame] | 92 | static int juno_fpga_reset_deassert(struct reset_controller_dev *rcdev, |
| 93 | unsigned long id) |
Per Åstrand | 9f36f2e | 2021-09-30 09:57:34 +0200 | [diff] [blame] | 94 | { |
Mikael Olsson | 3875fa7 | 2023-09-11 14:01:58 +0200 | [diff] [blame] | 95 | struct juno_fpga_reset *reset = container_of(rcdev, |
| 96 | struct juno_fpga_reset, |
| 97 | rst); |
Per Åstrand | 9f36f2e | 2021-09-30 09:57:34 +0200 | [diff] [blame] | 98 | |
| 99 | /* release wait */ |
| 100 | dev_dbg(reset->dev, "Deasserting reset"); |
| 101 | |
| 102 | writel(JUNO_FPGA_RESET_UNSET_CPUWAIT, |
| 103 | JUNO_FPGA_RESET_CPU_WAIT(reset->base)); |
Mikael Olsson | 3875fa7 | 2023-09-11 14:01:58 +0200 | [diff] [blame] | 104 | |
Per Åstrand | 9f36f2e | 2021-09-30 09:57:34 +0200 | [diff] [blame] | 105 | return 0; |
| 106 | } |
| 107 | |
| 108 | static struct reset_control_ops juno_fpga_reset_ops = { |
| 109 | .assert = juno_fpga_reset_assert, |
| 110 | .deassert = juno_fpga_reset_deassert, |
| 111 | }; |
| 112 | |
| 113 | static const struct of_device_id juno_fpga_reset_match[] = { |
Mikael Olsson | c4ec925 | 2023-11-14 10:42:46 +0100 | [diff] [blame] | 114 | { .compatible = "arm,mali_fpga_sysctl", .data = NULL }, |
Per Åstrand | 9f36f2e | 2021-09-30 09:57:34 +0200 | [diff] [blame] | 115 | { /* sentinel */ }, |
| 116 | }; |
| 117 | |
| 118 | static int juno_fpga_reset_probe(struct platform_device *pdev) |
| 119 | { |
| 120 | struct device *dev = &pdev->dev; |
| 121 | struct juno_fpga_reset *reset; |
| 122 | struct resource *res; |
| 123 | |
| 124 | reset = devm_kzalloc(&pdev->dev, sizeof(*reset), GFP_KERNEL); |
| 125 | if (!reset) |
| 126 | return -ENOMEM; |
| 127 | |
| 128 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 129 | |
| 130 | reset->base = verify_and_remap(dev, res); |
| 131 | reset->dev = dev; |
| 132 | |
Per Åstrand | 049c59b | 2021-11-02 15:23:18 +0100 | [diff] [blame] | 133 | if (IS_ERR(reset->base)) { |
Mikael Olsson | 3875fa7 | 2023-09-11 14:01:58 +0200 | [diff] [blame] | 134 | dev_err(dev, "Failed to verify and remap base address (%ld)", |
| 135 | PTR_ERR(reset->base)); |
| 136 | |
Per Åstrand | 9f36f2e | 2021-09-30 09:57:34 +0200 | [diff] [blame] | 137 | return PTR_ERR(reset->base); |
Mikael Olsson | 3875fa7 | 2023-09-11 14:01:58 +0200 | [diff] [blame] | 138 | } |
Per Åstrand | 9f36f2e | 2021-09-30 09:57:34 +0200 | [diff] [blame] | 139 | |
| 140 | platform_set_drvdata(pdev, reset); |
| 141 | |
| 142 | reset->rst.owner = THIS_MODULE; |
| 143 | reset->rst.nr_resets = 1; |
| 144 | reset->rst.ops = &juno_fpga_reset_ops; |
| 145 | reset->rst.of_node = pdev->dev.of_node; |
| 146 | |
Per Åstrand | 049c59b | 2021-11-02 15:23:18 +0100 | [diff] [blame] | 147 | dev_info(dev, "registering to reset controller core"); |
Per Åstrand | 9f36f2e | 2021-09-30 09:57:34 +0200 | [diff] [blame] | 148 | |
| 149 | return devm_reset_controller_register(dev, &reset->rst); |
| 150 | } |
| 151 | |
| 152 | static int juno_fpga_reset_remove(struct platform_device *pdev) |
| 153 | { |
| 154 | return 0; |
| 155 | } |
| 156 | |
| 157 | static struct platform_driver juno_fpga_reset_driver = { |
| 158 | .probe = juno_fpga_reset_probe, |
| 159 | .remove = juno_fpga_reset_remove, |
| 160 | .driver = { |
| 161 | .name = "juno-fpga-reset", |
| 162 | .of_match_table = of_match_ptr(juno_fpga_reset_match), |
| 163 | }, |
| 164 | }; |
| 165 | |
| 166 | module_platform_driver(juno_fpga_reset_driver); |
| 167 | |
| 168 | MODULE_LICENSE("GPL v2"); |
| 169 | MODULE_AUTHOR("Arm Ltd"); |
| 170 | MODULE_DESCRIPTION("Arm Juno FPGA Reset Driver"); |
| 171 | MODULE_VERSION(JUNO_FPGA_RESET_DRIVER_VERSION); |