vela: Fix Ethos-U65 maximum address range
- Changed Ethos-65 AXI port address width from 48 to 40-bits
- Fixed the use of arena_cache_size in mem_type_size() to cover the
arena as well as the cache memory area
Signed-off-by: Tim Hall <tim.hall@arm.com>
Change-Id: I826462a0cbd0c061cccbc7c83dde446778a2b1ca
diff --git a/ethosu/vela/test/extapi/test_extapi_generate_commands.py b/ethosu/vela/test/extapi/test_extapi_generate_commands.py
index ee13430..a520789 100644
--- a/ethosu/vela/test/extapi/test_extapi_generate_commands.py
+++ b/ethosu/vela/test/extapi/test_extapi_generate_commands.py
@@ -380,11 +380,11 @@
npu_generate_register_command_stream([conv_op], NpuAccelerator.Ethos_U65_512)
# weights with end address out of range
conv_op = create_fully_connected_op()
- conv_op.weights = [NpuAddressRange(region=0, address=(1 << 48) - 960, length=1000)]
+ conv_op.weights = [NpuAddressRange(region=0, address=(1 << 40) - 960, length=1000)]
with pytest.raises(VelaError):
npu_generate_register_command_stream([conv_op], NpuAccelerator.Ethos_U65_256)
# bias with high end address, but still within range
- addr = (1 << 48) - 1024
+ addr = (1 << 40) - 1024
conv_op = create_fully_connected_op()
conv_op.biases = [NpuAddressRange(region=0, address=addr, length=1000)]
cmds = npu_generate_register_command_stream([conv_op], NpuAccelerator.Ethos_U65_512)